usb: ehci: do not set the LSB of Current qTD pointer
[karo-tx-uboot.git] / board / freescale / mx6sxsabresd / mx6sxsabresd.c
1 /*
2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
3  *
4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/io.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <linux/sizes.h>
20 #include <common.h>
21 #include <fsl_esdhc.h>
22 #include <mmc.h>
23 #include <i2c.h>
24 #include <miiphy.h>
25 #include <netdev.h>
26 #include <power/pmic.h>
27 #include <power/pfuze100_pmic.h>
28 #include <usb.h>
29 #include <usb/ehci-fsl.h>
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
34         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
35         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
36
37 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
38         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
39         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
40
41 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
42         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
43         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
44         PAD_CTL_ODE)
45
46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
47         PAD_CTL_SPEED_HIGH   |                                   \
48         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
49
50 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
51         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
52
53 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
54         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
55
56 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
57         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
58         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
59         PAD_CTL_ODE)
60
61 int dram_init(void)
62 {
63         gd->ram_size = PHYS_SDRAM_SIZE;
64
65         return 0;
66 }
67
68 static iomux_v3_cfg_t const uart1_pads[] = {
69         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
70         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
71 };
72
73 static iomux_v3_cfg_t const usdhc4_pads[] = {
74         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80         MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
81 };
82
83 static iomux_v3_cfg_t const fec1_pads[] = {
84         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
85         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
86         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
87         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
88         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
89         MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
90         MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
91         MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
92         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
93         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
94         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
95         MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
96         MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
97         MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 };
99
100 static iomux_v3_cfg_t const peri_3v3_pads[] = {
101         MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
102 };
103
104 static iomux_v3_cfg_t const phy_control_pads[] = {
105         /* 25MHz Ethernet PHY Clock */
106         MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
107
108         /* ENET PHY Power */
109         MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
110
111         /* AR8031 PHY Reset */
112         MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
113 };
114
115 static void setup_iomux_uart(void)
116 {
117         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
118 }
119
120 static int setup_fec(void)
121 {
122         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
123         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
124         int ret;
125         int reg;
126
127         /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
128         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
129
130         imx_iomux_v3_setup_multiple_pads(phy_control_pads,
131                                          ARRAY_SIZE(phy_control_pads));
132
133         /* Enable the ENET power, active low */
134         gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
135
136         /* Reset AR8031 PHY */
137         gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
138         udelay(500);
139         gpio_set_value(IMX_GPIO_NR(2, 7), 1);
140
141         reg = readl(&anatop->pll_enet);
142         reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
143         writel(reg, &anatop->pll_enet);
144
145         ret = enable_fec_anatop_clock(ENET_125MHz);
146         if (ret)
147                 return ret;
148
149         return 0;
150 }
151
152 int board_eth_init(bd_t *bis)
153 {
154         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
155         setup_fec();
156
157         return cpu_eth_init(bis);
158 }
159
160 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
161 /* I2C1 for PMIC */
162 static struct i2c_pads_info i2c_pad_info1 = {
163         .scl = {
164                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
165                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
166                 .gp = IMX_GPIO_NR(1, 0),
167         },
168         .sda = {
169                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
170                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
171                 .gp = IMX_GPIO_NR(1, 1),
172         },
173 };
174
175 static int pfuze_init(void)
176 {
177         struct pmic *p;
178         int ret;
179         unsigned int reg;
180
181         ret = power_pfuze100_init(I2C_PMIC);
182         if (ret)
183                 return ret;
184
185         p = pmic_get("PFUZE100");
186         ret = pmic_probe(p);
187         if (ret)
188                 return ret;
189
190         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
191         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
192
193         /* Set SW1AB standby voltage to 0.975V */
194         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
195         reg &= ~0x3f;
196         reg |= 0x1b;
197         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
198
199         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
200         pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
201         reg &= ~0xc0;
202         reg |= 0x40;
203         pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
204
205         /* Set SW1C standby voltage to 0.975V */
206         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
207         reg &= ~0x3f;
208         reg |= 0x1b;
209         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
210
211         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
212         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
213         reg &= ~0xc0;
214         reg |= 0x40;
215         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
216
217         /* Enable power of VGEN5 3V3, needed for SD3 */
218         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
219         reg &= ~0x1F;
220         reg |= 0x1F;
221         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
222
223         return 0;
224 }
225
226 int board_phy_config(struct phy_device *phydev)
227 {
228         /*
229          * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
230          * Phy control debug reg 0
231          */
232         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
233         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
234
235         /* rgmii tx clock delay enable */
236         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
237         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
238
239         if (phydev->drv->config)
240                 phydev->drv->config(phydev);
241
242         return 0;
243 }
244
245 int board_early_init_f(void)
246 {
247         setup_iomux_uart();
248         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
249
250         /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
251         imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
252                                          ARRAY_SIZE(peri_3v3_pads));
253
254         /* Active high for ncp692 */
255         gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
256
257 #ifdef CONFIG_USB_EHCI_MX6
258         setup_usb();
259 #endif
260
261         return 0;
262 }
263
264 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
265         {USDHC4_BASE_ADDR},
266 };
267
268 int board_mmc_getcd(struct mmc *mmc)
269 {
270         return 1;       /* Assume boot SD always present */
271 }
272
273 int board_mmc_init(bd_t *bis)
274 {
275         imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
276
277         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
278         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
279 }
280
281 #ifdef CONFIG_USB_EHCI_MX6
282 #define USB_OTHERREGS_OFFSET    0x800
283 #define UCTRL_PWR_POL           (1 << 9)
284
285 static iomux_v3_cfg_t const usb_otg_pads[] = {
286         /* OGT1 */
287         MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
288         MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
289         /* OTG2 */
290         MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
291 };
292
293 static void setup_usb(void)
294 {
295         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
296                                          ARRAY_SIZE(usb_otg_pads));
297 }
298
299 int board_usb_phy_mode(int port)
300 {
301         if (port == 1)
302                 return USB_INIT_HOST;
303         else
304                 return usb_phy_mode(port);
305 }
306
307 int board_ehci_hcd_init(int port)
308 {
309         u32 *usbnc_usb_ctrl;
310
311         if (port > 1)
312                 return -EINVAL;
313
314         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
315                                  port * 4);
316
317         /* Set Power polarity */
318         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
319
320         return 0;
321 }
322 #endif
323
324 int board_init(void)
325 {
326         /* Address of boot parameters */
327         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
328
329         return 0;
330 }
331
332 int board_late_init(void)
333 {
334         pfuze_init();
335
336         return 0;
337 }
338
339 int checkboard(void)
340 {
341         puts("Board: MX6SX SABRE SDB\n");
342
343         return 0;
344 }