board/freescale/mx6sxsabresd/mx6sxsabresd.c

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/iomux-v3.h>
  16 #include <asm/io.h>
  17 #include <asm/imx-common/mxc_i2c.h>
  18 #include <linux/sizes.h>
  19 #include <common.h>
  20 #include <fsl_esdhc.h>
  21 #include <mmc.h>
  22 #include <i2c.h>
  23 #include <power/pmic.h>
  24 #include <power/pfuze100_pmic.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  29         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  30         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  31
  32 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  33         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  34         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  37         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  38         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  39         PAD_CTL_ODE)
  40
  41 int dram_init(void)
  42 {
  43         gd->ram_size = PHYS_SDRAM_SIZE;
  44
  45         return 0;
  46 }
  47
  48 static iomux_v3_cfg_t const uart1_pads[] = {
  49         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  50         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  51 };
  52
  53 static iomux_v3_cfg_t const usdhc4_pads[] = {
  54         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  55         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  56         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  57         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60         MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  61 };
  62
  63 static void setup_iomux_uart(void)
  64 {
  65         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  66 }
  67
  68 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  69 /* I2C1 for PMIC */
  70 struct i2c_pads_info i2c_pad_info1 = {
  71         .scl = {
  72                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  73                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  74                 .gp = IMX_GPIO_NR(1, 0),
  75         },
  76         .sda = {
  77                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  78                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  79                 .gp = IMX_GPIO_NR(1, 1),
  80         },
  81 };
  82
  83 static int pfuze_init(void)
  84 {
  85         struct pmic *p;
  86         int ret;
  87         unsigned int reg;
  88
  89         ret = power_pfuze100_init(I2C_PMIC);
  90         if (ret)
  91                 return ret;
  92
  93         p = pmic_get("PFUZE100");
  94         ret = pmic_probe(p);
  95         if (ret)
  96                 return ret;
  97
  98         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  99         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 100
 101         /* Set SW1AB standby voltage to 0.975V */
 102         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 103         reg &= ~0x3f;
 104         reg |= 0x1b;
 105         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 106
 107         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 108         pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
 109         reg &= ~0xc0;
 110         reg |= 0x40;
 111         pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
 112
 113         /* Set SW1C standby voltage to 0.975V */
 114         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 115         reg &= ~0x3f;
 116         reg |= 0x1b;
 117         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 118
 119         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 120         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 121         reg &= ~0xc0;
 122         reg |= 0x40;
 123         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 124
 125         /* Enable power of VGEN5 3V3, needed for SD3 */
 126         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 127         reg &= ~0x1F;
 128         reg |= 0x1F;
 129         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 130
 131         return 0;
 132 }
 133
 134 int board_early_init_f(void)
 135 {
 136         setup_iomux_uart();
 137         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 138
 139         return 0;
 140 }
 141
 142 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 143         {USDHC4_BASE_ADDR},
 144 };
 145
 146 int board_mmc_getcd(struct mmc *mmc)
 147 {
 148         return 1;       /* Assume boot SD always present */
 149 }
 150
 151 int board_mmc_init(bd_t *bis)
 152 {
 153         imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 154
 155         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 156         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 157 }
 158
 159 int board_init(void)
 160 {
 161         /* Address of boot parameters */
 162         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 163
 164         return 0;
 165 }
 166
 167 int board_late_init(void)
 168 {
 169         pfuze_init();
 170
 171         return 0;
 172 }
 173
 174 int checkboard(void)
 175 {
 176         puts("Board: MX6SX SABRE SDB\n");
 177
 178         return 0;
 179 }