board/freescale/mx6sxsabresd/mx6sxsabresd.c

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/imx-common/iomux-v3.h>
  17 #include <asm/io.h>
  18 #include <asm/imx-common/mxc_i2c.h>
  19 #include <linux/sizes.h>
  20 #include <common.h>
  21 #include <fsl_esdhc.h>
  22 #include <mmc.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <netdev.h>
  26 #include <power/pmic.h>
  27 #include <power/pfuze100_pmic.h>
  28 #include "../common/pfuze.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  33         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  34         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  37         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  38         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  41         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  42         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  43         PAD_CTL_ODE)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  46         PAD_CTL_SPEED_HIGH   |                                   \
  47         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  48
  49 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
  50         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
  51
  52 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  53         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  54
  55 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  56         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  57         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  58         PAD_CTL_ODE)
  59
  60 int dram_init(void)
  61 {
  62         gd->ram_size = PHYS_SDRAM_SIZE;
  63
  64         return 0;
  65 }
  66
  67 static iomux_v3_cfg_t const uart1_pads[] = {
  68         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  69         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  70 };
  71
  72 static iomux_v3_cfg_t const usdhc2_pads[] = {
  73         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77         MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78         MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79 };
  80
  81 static iomux_v3_cfg_t const usdhc3_pads[] = {
  82         MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92
  93         /* CD pin */
  94         MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  95
  96         /* RST_B, used for power reset cycle */
  97         MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  98 };
  99
 100 static iomux_v3_cfg_t const usdhc4_pads[] = {
 101         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 108 };
 109
 110 static iomux_v3_cfg_t const fec1_pads[] = {
 111         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
 113         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 114         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 115         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 116         MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 117         MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 118         MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 119         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 122         MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 123         MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 124         MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 125 };
 126
 127 static iomux_v3_cfg_t const peri_3v3_pads[] = {
 128         MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 129 };
 130
 131 static iomux_v3_cfg_t const phy_control_pads[] = {
 132         /* 25MHz Ethernet PHY Clock */
 133         MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 134
 135         /* ENET PHY Power */
 136         MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
 137
 138         /* AR8031 PHY Reset */
 139         MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
 140 };
 141
 142 static void setup_iomux_uart(void)
 143 {
 144         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 145 }
 146
 147 static int setup_fec(void)
 148 {
 149         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 150         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 151         int reg;
 152
 153         /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
 154         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
 155
 156         imx_iomux_v3_setup_multiple_pads(phy_control_pads,
 157                                          ARRAY_SIZE(phy_control_pads));
 158
 159         /* Enable the ENET power, active low */
 160         gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
 161
 162         /* Reset AR8031 PHY */
 163         gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
 164         udelay(500);
 165         gpio_set_value(IMX_GPIO_NR(2, 7), 1);
 166
 167         reg = readl(&anatop->pll_enet);
 168         reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 169         writel(reg, &anatop->pll_enet);
 170
 171         return enable_fec_anatop_clock(ENET_125MHZ);
 172 }
 173
 174 int board_eth_init(bd_t *bis)
 175 {
 176         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 177         setup_fec();
 178
 179         return cpu_eth_init(bis);
 180 }
 181
 182 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 183 /* I2C1 for PMIC */
 184 static struct i2c_pads_info i2c_pad_info1 = {
 185         .scl = {
 186                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
 187                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
 188                 .gp = IMX_GPIO_NR(1, 0),
 189         },
 190         .sda = {
 191                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
 192                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
 193                 .gp = IMX_GPIO_NR(1, 1),
 194         },
 195 };
 196
 197 int power_init_board(void)
 198 {
 199         struct pmic *p;
 200         unsigned int reg;
 201
 202         p = pfuze_common_init(I2C_PMIC);
 203         if (!p)
 204                 return -ENODEV;
 205
 206         /* Enable power of VGEN5 3V3, needed for SD3 */
 207         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 208         reg &= ~LDO_VOL_MASK;
 209         reg |= (LDOB_3_30V | (1 << LDO_EN));
 210         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 211
 212         return 0;
 213 }
 214
 215 int board_phy_config(struct phy_device *phydev)
 216 {
 217         /*
 218          * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
 219          * Phy control debug reg 0
 220          */
 221         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 222         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 223
 224         /* rgmii tx clock delay enable */
 225         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 226         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 227
 228         if (phydev->drv->config)
 229                 phydev->drv->config(phydev);
 230
 231         return 0;
 232 }
 233
 234 int board_early_init_f(void)
 235 {
 236         setup_iomux_uart();
 237
 238         /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
 239         imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
 240                                          ARRAY_SIZE(peri_3v3_pads));
 241
 242         /* Active high for ncp692 */
 243         gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
 244
 245         return 0;
 246 }
 247
 248 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 249         {USDHC2_BASE_ADDR, 0, 4},
 250         {USDHC3_BASE_ADDR},
 251         {USDHC4_BASE_ADDR},
 252 };
 253
 254 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 10)
 255 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
 256 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 21)
 257
 258 int board_mmc_getcd(struct mmc *mmc)
 259 {
 260         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 261         int ret = 0;
 262
 263         switch (cfg->esdhc_base) {
 264         case USDHC2_BASE_ADDR:
 265                 ret = 1; /* Assume uSDHC2 is always present */
 266                 break;
 267         case USDHC3_BASE_ADDR:
 268                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 269                 break;
 270         case USDHC4_BASE_ADDR:
 271                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 272                 break;
 273         }
 274
 275         return ret;
 276 }
 277
 278 int board_mmc_init(bd_t *bis)
 279 {
 280         int i, ret;
 281
 282         /*
 283          * According to the board_mmc_init() the following map is done:
 284          * (U-boot device node)    (Physical Port)
 285          * mmc0                    USDHC2
 286          * mmc1                    USDHC3
 287          * mmc2                    USDHC4
 288          */
 289         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 290                 switch (i) {
 291                 case 0:
 292                         imx_iomux_v3_setup_multiple_pads(
 293                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 294                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 295                         break;
 296                 case 1:
 297                         imx_iomux_v3_setup_multiple_pads(
 298                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 299                         gpio_direction_input(USDHC3_CD_GPIO);
 300                         gpio_direction_output(USDHC3_PWR_GPIO, 1);
 301                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 302                         break;
 303                 case 2:
 304                         imx_iomux_v3_setup_multiple_pads(
 305                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 306                         gpio_direction_input(USDHC4_CD_GPIO);
 307                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 308                         break;
 309                 default:
 310                         printf("Warning: you configured more USDHC controllers"
 311                                 "(%d) than supported by the board\n", i + 1);
 312                         return -EINVAL;
 313                         }
 314
 315                         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 316                         if (ret) {
 317                                 printf("Warning: failed to initialize mmc dev %d\n", i);
 318                                 return ret;
 319                         }
 320         }
 321
 322         return 0;
 323 }
 324
 325
 326 int board_init(void)
 327 {
 328         /* Address of boot parameters */
 329         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 330
 331 #ifdef CONFIG_SYS_I2C_MXC
 332         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 333 #endif
 334
 335         return 0;
 336 }
 337
 338 int board_late_init(void)
 339 {
 340         return 0;
 341 }
 342
 343 int checkboard(void)
 344 {
 345         puts("Board: MX6SX SABRE SDB\n");
 346
 347         return 0;
 348 }