board/freescale/p2020ds/ddr.c

   1 /*
   2  * Copyright 2008-2009 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11
  12 #include <asm/fsl_ddr_sdram.h>
  13 #include <asm/fsl_ddr_dimm_params.h>
  14
  15 static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address)
  16 {
  17         i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
  18 }
  19
  20 unsigned int fsl_ddr_get_mem_data_rate(void)
  21 {
  22         return get_ddr_freq(0);
  23 }
  24
  25 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  26                       unsigned int ctrl_num)
  27 {
  28         unsigned int i;
  29         unsigned int i2c_address = 0;
  30
  31         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  32                 if (ctrl_num == 0 && i == 0)
  33                         i2c_address = SPD_EEPROM_ADDRESS1;
  34                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  35         }
  36 }
  37
  38 typedef struct {
  39         u32 datarate_mhz_low;
  40         u32 datarate_mhz_high;
  41         u32 n_ranks;
  42         u32 clk_adjust;
  43         u32 cpo;
  44         u32 write_data_delay;
  45         u32 force_2T;
  46 } board_specific_parameters_t;
  47
  48 /* ranges for parameters:
  49  *  wr_data_delay = 0-6
  50  *  clk adjust = 0-8
  51  *  cpo 2-0x1E (30)
  52  */
  53
  54 const board_specific_parameters_t board_specific_parameters[][20] = {
  55         {
  56         /*      memory controller 0                     */
  57         /*        lo|  hi|  num|  clk| cpo|wrdata|2T    */
  58         /*       mhz| mhz|ranks|adjst|    | delay|      */
  59 #ifdef CONFIG_FSL_DDR2
  60                 {  0, 333,    2,    4,   0x1f,    2,  0},
  61                 {334, 400,    2,    4,   0x1f,    2,  0},
  62                 {401, 549,    2,    4,   0x1f,    2,  0},
  63                 {550, 680,    2,    4,   0x1f,    3,  0},
  64                 {681, 850,    2,    4,   0x1f,    4,  0},
  65                 {  0, 333,    1,    4,   0x1f,    2,  0},
  66                 {334, 400,    1,    4,   0x1f,    2,  0},
  67                 {401, 549,    1,    4,   0x1f,    2,  0},
  68                 {550, 680,    1,    4,   0x1f,    3,  0},
  69                 {681, 850,    1,    4,   0x1f,    4,  0}
  70 #else
  71                 {  0, 850,    2,    4,   0x1f,    4,  0},
  72                 {  0, 850,    1,    4,   0x1f,    4,  0}
  73 #endif
  74         },
  75 };
  76
  77 void fsl_ddr_board_options(memctl_options_t *popts,
  78                                 dimm_params_t *pdimm,
  79                                 unsigned int ctrl_num)
  80 {
  81         const board_specific_parameters_t *pbsp =
  82                                 &(board_specific_parameters[ctrl_num][0]);
  83         u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
  84                                 sizeof(board_specific_parameters[0][0]);
  85         u32 i;
  86         ulong ddr_freq;
  87
  88         /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
  89          * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
  90          * there are two dimms in the controller, set odt_rd_cfg to 3 and
  91          * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
  92          */
  93         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  94                         popts->cs_local_opts[i].odt_rd_cfg = 0;
  95                         popts->cs_local_opts[i].odt_wr_cfg = 1;
  96         }
  97
  98         /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  99          * freqency and n_banks specified in board_specific_parameters table.
 100          */
 101         ddr_freq = get_ddr_freq(0) / 1000000;
 102         for (i = 0; i < num_params; i++) {
 103                 if (ddr_freq >= pbsp->datarate_mhz_low &&
 104                     ddr_freq <= pbsp->datarate_mhz_high &&
 105                     pdimm->n_ranks == pbsp->n_ranks) {
 106                         popts->clk_adjust = pbsp->clk_adjust;
 107                         popts->cpo_override = pbsp->cpo;
 108                         popts->write_data_delay = pbsp->write_data_delay;
 109                         popts->twoT_en = pbsp->force_2T;
 110                 }
 111                 pbsp++;
 112         }
 113
 114         /*
 115          * Factors to consider for half-strength driver enable:
 116          *      - number of DIMMs installed
 117          */
 118         popts->half_strength_driver_enable = 0;
 119         popts->wrlvl_en = 1;
 120         /* Write leveling override */
 121         popts->wrlvl_override = 1;
 122         popts->wrlvl_sample = 0xa;
 123         popts->wrlvl_start = 0x7;
 124         /* Rtt and Rtt_WR override */
 125         popts->rtt_override = 1;
 126         popts->rtt_override_value = DDR3_RTT_120_OHM;
 127         popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
 128 }