board/freescale/p2020ds/p2020ds.c

   1 /*
   2  * Copyright 2007-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <pci.h>
  10 #include <asm/processor.h>
  11 #include <asm/mmu.h>
  12 #include <asm/cache.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/fsl_pci.h>
  15 #include <fsl_ddr_sdram.h>
  16 #include <asm/io.h>
  17 #include <asm/fsl_serdes.h>
  18 #include <miiphy.h>
  19 #include <libfdt.h>
  20 #include <fdt_support.h>
  21 #include <fsl_mdio.h>
  22 #include <tsec.h>
  23 #include <asm/fsl_law.h>
  24 #include <netdev.h>
  25
  26 #include "../common/ngpixis.h"
  27 #include "../common/sgmii_riser.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 int board_early_init_f(void)
  32 {
  33 #ifdef CONFIG_MMC
  34         ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  35
  36         setbits_be32(&gur->pmuxcr,
  37                          (MPC85xx_PMUXCR_SDHC_CD |
  38                          MPC85xx_PMUXCR_SDHC_WP));
  39 #endif
  40
  41         return 0;
  42 }
  43
  44 int checkboard(void)
  45 {
  46         u8 sw;
  47
  48         printf("Board: P2020DS Sys ID: 0x%02x, "
  49                "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  50                 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  51
  52         sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  53         sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  54
  55         if (sw < 0x8)
  56                 /* The lower two bits are the actual vbank number */
  57                 printf("vBank: %d\n", sw & 3);
  58         else
  59                 puts("Promjet\n");
  60
  61         return 0;
  62 }
  63
  64 #if !defined(CONFIG_DDR_SPD)
  65 /*
  66  * Fixed sdram init -- doesn't use serial presence detect.
  67  */
  68
  69 phys_size_t fixed_sdram(void)
  70 {
  71         struct ccsr_ddr __iomem *ddr =
  72                 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
  73         uint d_init;
  74
  75         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  76         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  77         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  78         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  79         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  80         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
  81         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  82         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  83         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  84         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
  85         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
  86         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
  87         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
  88         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
  89         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
  90
  91         if (!strcmp("performance", getenv("perf_mode"))) {
  92                 /* Performance Mode Values */
  93
  94                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
  95                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
  96                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
  97                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
  98                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
  99
 100                 asm("sync;isync");
 101
 102                 udelay(500);
 103
 104                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
 105         } else {
 106                 /* Stable Mode Values */
 107
 108                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 109                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 110                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 111                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 112                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 113
 114                 /* ECC will be assumed in stable mode */
 115                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 116                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 117                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 118
 119                 asm("sync;isync");
 120
 121                 udelay(500);
 122
 123                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 124         }
 125
 126 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 127         d_init = 1;
 128         debug("DDR - 1st controller: memory initializing\n");
 129         /*
 130          * Poll until memory is initialized.
 131          * 512 Meg at 400 might hit this 200 times or so.
 132          */
 133         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 134                 udelay(1000);
 135         debug("DDR: memory initialized\n\n");
 136         asm("sync; isync");
 137         udelay(500);
 138 #endif
 139
 140         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
 141                          CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
 142                          LAW_TRGT_IF_DDR) < 0) {
 143                 printf("ERROR setting Local Access Windows for DDR\n");
 144                 return 0;
 145         };
 146
 147         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 148 }
 149
 150 #endif
 151
 152 #ifdef CONFIG_PCI
 153 void pci_init_board(void)
 154 {
 155         fsl_pcie_init_board(0);
 156 }
 157 #endif
 158
 159 int board_early_init_r(void)
 160 {
 161         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 162         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 163
 164         /*
 165          * Remap Boot flash + PROMJET region to caching-inhibited
 166          * so that flash can be erased properly.
 167          */
 168
 169         /* Flush d-cache and invalidate i-cache of any FLASH data */
 170         flush_dcache();
 171         invalidate_icache();
 172
 173         /* invalidate existing TLB entry for flash + promjet */
 174         disable_tlb(flash_esel);
 175
 176         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 177                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 178                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 179
 180         return 0;
 181 }
 182
 183 #ifdef CONFIG_TSEC_ENET
 184 int board_eth_init(bd_t *bis)
 185 {
 186         struct fsl_pq_mdio_info mdio_info;
 187         struct tsec_info_struct tsec_info[4];
 188         int num = 0;
 189
 190 #ifdef CONFIG_TSEC1
 191         SET_STD_TSEC_INFO(tsec_info[num], 1);
 192         num++;
 193 #endif
 194 #ifdef CONFIG_TSEC2
 195         SET_STD_TSEC_INFO(tsec_info[num], 2);
 196         if (is_serdes_configured(SGMII_TSEC2)) {
 197                 puts("eTSEC2 is in sgmii mode.\n");
 198                 tsec_info[num].flags |= TSEC_SGMII;
 199         }
 200         num++;
 201 #endif
 202 #ifdef CONFIG_TSEC3
 203         SET_STD_TSEC_INFO(tsec_info[num], 3);
 204         if (is_serdes_configured(SGMII_TSEC3)) {
 205                 puts("eTSEC3 is in sgmii mode.\n");
 206                 tsec_info[num].flags |= TSEC_SGMII;
 207 }
 208         num++;
 209 #endif
 210
 211         if (!num) {
 212                 printf("No TSECs initialized\n");
 213
 214                 return 0;
 215         }
 216
 217 #ifdef CONFIG_FSL_SGMII_RISER
 218         fsl_sgmii_riser_init(tsec_info, num);
 219 #endif
 220
 221         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 222         mdio_info.name = DEFAULT_MII_NAME;
 223
 224         fsl_pq_mdio_init(bis, &mdio_info);
 225
 226         tsec_eth_init(bis, tsec_info, num);
 227
 228         return pci_eth_init(bis);
 229 }
 230 #endif
 231
 232 #if defined(CONFIG_OF_BOARD_SETUP)
 233 void ft_board_setup(void *blob, bd_t *bd)
 234 {
 235         phys_addr_t base;
 236         phys_size_t size;
 237
 238         ft_cpu_setup(blob, bd);
 239
 240         base = getenv_bootm_low();
 241         size = getenv_bootm_size();
 242
 243         fdt_fixup_memory(blob, (u64)base, (u64)size);
 244
 245 #ifdef CONFIG_HAS_FSL_DR_USB
 246         fdt_fixup_dr_usb(blob, bd);
 247 #endif
 248
 249         FT_FSL_PCI_SETUP;
 250
 251 #ifdef CONFIG_FSL_SGMII_RISER
 252         fsl_sgmii_riser_fdt_fixup(blob);
 253 #endif
 254 }
 255 #endif