4d0979632a0b90f7ccef5e671dab5a6dfaaf74c7
[karo-tx-uboot.git] / board / freescale / vf610twr / vf610twr.c
1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux-vf610.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/clock.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <miiphy.h>
16 #include <netdev.h>
17 #include <i2c.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
22                         PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
23
24 #define ESDHC_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
25                         PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
26
27 #define ENET_PAD_CTRL   (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
28                         PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
29
30 void setup_iomux_ddr(void)
31 {
32         static const iomux_v3_cfg_t ddr_pads[] = {
33                 VF610_PAD_DDR_A15__DDR_A_15,
34                 VF610_PAD_DDR_A14__DDR_A_14,
35                 VF610_PAD_DDR_A13__DDR_A_13,
36                 VF610_PAD_DDR_A12__DDR_A_12,
37                 VF610_PAD_DDR_A11__DDR_A_11,
38                 VF610_PAD_DDR_A10__DDR_A_10,
39                 VF610_PAD_DDR_A9__DDR_A_9,
40                 VF610_PAD_DDR_A8__DDR_A_8,
41                 VF610_PAD_DDR_A7__DDR_A_7,
42                 VF610_PAD_DDR_A6__DDR_A_6,
43                 VF610_PAD_DDR_A5__DDR_A_5,
44                 VF610_PAD_DDR_A4__DDR_A_4,
45                 VF610_PAD_DDR_A3__DDR_A_3,
46                 VF610_PAD_DDR_A2__DDR_A_2,
47                 VF610_PAD_DDR_A1__DDR_A_1,
48                 VF610_PAD_DDR_BA2__DDR_BA_2,
49                 VF610_PAD_DDR_BA1__DDR_BA_1,
50                 VF610_PAD_DDR_BA0__DDR_BA_0,
51                 VF610_PAD_DDR_CAS__DDR_CAS_B,
52                 VF610_PAD_DDR_CKE__DDR_CKE_0,
53                 VF610_PAD_DDR_CLK__DDR_CLK_0,
54                 VF610_PAD_DDR_CS__DDR_CS_B_0,
55                 VF610_PAD_DDR_D15__DDR_D_15,
56                 VF610_PAD_DDR_D14__DDR_D_14,
57                 VF610_PAD_DDR_D13__DDR_D_13,
58                 VF610_PAD_DDR_D12__DDR_D_12,
59                 VF610_PAD_DDR_D11__DDR_D_11,
60                 VF610_PAD_DDR_D10__DDR_D_10,
61                 VF610_PAD_DDR_D9__DDR_D_9,
62                 VF610_PAD_DDR_D8__DDR_D_8,
63                 VF610_PAD_DDR_D7__DDR_D_7,
64                 VF610_PAD_DDR_D6__DDR_D_6,
65                 VF610_PAD_DDR_D5__DDR_D_5,
66                 VF610_PAD_DDR_D4__DDR_D_4,
67                 VF610_PAD_DDR_D3__DDR_D_3,
68                 VF610_PAD_DDR_D2__DDR_D_2,
69                 VF610_PAD_DDR_D1__DDR_D_1,
70                 VF610_PAD_DDR_D0__DDR_D_0,
71                 VF610_PAD_DDR_DQM1__DDR_DQM_1,
72                 VF610_PAD_DDR_DQM0__DDR_DQM_0,
73                 VF610_PAD_DDR_DQS1__DDR_DQS_1,
74                 VF610_PAD_DDR_DQS0__DDR_DQS_0,
75                 VF610_PAD_DDR_RAS__DDR_RAS_B,
76                 VF610_PAD_DDR_WE__DDR_WE_B,
77                 VF610_PAD_DDR_ODT1__DDR_ODT_0,
78                 VF610_PAD_DDR_ODT0__DDR_ODT_1,
79         };
80
81         imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
82 }
83
84 void ddr_phy_init(void)
85 {
86         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
87
88         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
89         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
90         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
91         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
92
93         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
94         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
95         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
96         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
97
98         writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
99         writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
100         writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
101         writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
102
103         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
104         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
105         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
106         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
107
108         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
109         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
110         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
111         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
112
113         writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
114                 &ddrmr->phy[50]);
115 }
116
117 void ddr_ctrl_init(void)
118 {
119         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
120
121         writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
122         writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
123         writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
124
125         writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
126         writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
127         writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
128                 DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
129         writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
130                 DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
131         writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
132         writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
133                 &ddrmr->cr[17]);
134         writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
135
136         writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
137         writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
138                 DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
139
140         writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
141         writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
142         writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
143
144         writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
145         writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
146         writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
147         writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
148
149         writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
150         writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
151         writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
152         writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
153
154         writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
155         writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
156                 DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
157
158         writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
159         writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
160                 &ddrmr->cr[48]);
161
162         writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
163         writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
164         writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
165
166         writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
167         writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
168
169         writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
170                 DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
171         writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
172                 DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
173                 &ddrmr->cr[74]);
174         writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
175                 DDRMC_CR75_PLEN, &ddrmr->cr[75]);
176         writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
177                 DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
178         writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
179                 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
180         writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
181         writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
182
183         writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
184
185         writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
186                 &ddrmr->cr[87]);
187         writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
188         writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
189
190         writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
191         writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
192
193         writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
194         writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
195         writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
196
197         writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
198                 &ddrmr->cr[117]);
199         writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
200                 &ddrmr->cr[118]);
201
202         writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
203                 &ddrmr->cr[120]);
204         writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
205                 &ddrmr->cr[121]);
206         writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
207                 DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
208         writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
209                 &ddrmr->cr[123]);
210         writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
211
212         writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
213         writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
214                 &ddrmr->cr[132]);
215         writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
216                 DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
217                 &ddrmr->cr[139]);
218
219         writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
220                 DDRMC_CR154_PAD_ZQ_MODE(1) |
221                 DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]);
222         writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
223                 &ddrmr->cr[155]);
224         writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
225
226         ddr_phy_init();
227
228         writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
229
230         udelay(200);
231 }
232
233 int dram_init(void)
234 {
235         setup_iomux_ddr();
236
237         ddr_ctrl_init();
238         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
239
240         return 0;
241 }
242
243 static void setup_iomux_uart(void)
244 {
245         static const iomux_v3_cfg_t uart1_pads[] = {
246                 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
247                 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
248         };
249
250         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
251 }
252
253 static void setup_iomux_enet(void)
254 {
255         static const iomux_v3_cfg_t enet0_pads[] = {
256                 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
257                 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
258                 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
259                 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
260                 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
261                 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
262                 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
263                 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
264                 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
265                 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
266         };
267
268         imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
269 }
270
271 static void setup_iomux_i2c(void)
272 {
273         static const iomux_v3_cfg_t i2c0_pads[] = {
274                 VF610_PAD_PTB14__I2C0_SCL,
275                 VF610_PAD_PTB15__I2C0_SDA,
276         };
277
278         imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
279 }
280
281 #ifdef CONFIG_NAND_VF610_NFC
282 static void setup_iomux_nfc(void)
283 {
284         static const iomux_v3_cfg_t nfc_pads[] = {
285                 VF610_PAD_PTD31__NF_IO15,
286                 VF610_PAD_PTD30__NF_IO14,
287                 VF610_PAD_PTD29__NF_IO13,
288                 VF610_PAD_PTD28__NF_IO12,
289                 VF610_PAD_PTD27__NF_IO11,
290                 VF610_PAD_PTD26__NF_IO10,
291                 VF610_PAD_PTD25__NF_IO9,
292                 VF610_PAD_PTD24__NF_IO8,
293                 VF610_PAD_PTD23__NF_IO7,
294                 VF610_PAD_PTD22__NF_IO6,
295                 VF610_PAD_PTD21__NF_IO5,
296                 VF610_PAD_PTD20__NF_IO4,
297                 VF610_PAD_PTD19__NF_IO3,
298                 VF610_PAD_PTD18__NF_IO2,
299                 VF610_PAD_PTD17__NF_IO1,
300                 VF610_PAD_PTD16__NF_IO0,
301                 VF610_PAD_PTB24__NF_WE_B,
302                 VF610_PAD_PTB25__NF_CE0_B,
303                 VF610_PAD_PTB27__NF_RE_B,
304                 VF610_PAD_PTC26__NF_RB_B,
305                 VF610_PAD_PTC27__NF_ALE,
306                 VF610_PAD_PTC28__NF_CLE
307         };
308
309         imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
310 }
311 #endif
312
313
314 static void setup_iomux_qspi(void)
315 {
316         static const iomux_v3_cfg_t qspi0_pads[] = {
317                 VF610_PAD_PTD0__QSPI0_A_QSCK,
318                 VF610_PAD_PTD1__QSPI0_A_CS0,
319                 VF610_PAD_PTD2__QSPI0_A_DATA3,
320                 VF610_PAD_PTD3__QSPI0_A_DATA2,
321                 VF610_PAD_PTD4__QSPI0_A_DATA1,
322                 VF610_PAD_PTD5__QSPI0_A_DATA0,
323                 VF610_PAD_PTD7__QSPI0_B_QSCK,
324                 VF610_PAD_PTD8__QSPI0_B_CS0,
325                 VF610_PAD_PTD9__QSPI0_B_DATA3,
326                 VF610_PAD_PTD10__QSPI0_B_DATA2,
327                 VF610_PAD_PTD11__QSPI0_B_DATA1,
328                 VF610_PAD_PTD12__QSPI0_B_DATA0,
329         };
330
331         imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
332 }
333
334 #ifdef CONFIG_FSL_ESDHC
335 struct fsl_esdhc_cfg esdhc_cfg[1] = {
336         {ESDHC1_BASE_ADDR},
337 };
338
339 int board_mmc_getcd(struct mmc *mmc)
340 {
341         /* eSDHC1 is always present */
342         return 1;
343 }
344
345 int board_mmc_init(bd_t *bis)
346 {
347         static const iomux_v3_cfg_t esdhc1_pads[] = {
348                 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
349                 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
350                 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
351                 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
352                 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
353                 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
354         };
355
356         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
357
358         imx_iomux_v3_setup_multiple_pads(
359                 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
360
361         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
362 }
363 #endif
364
365 static void clock_init(void)
366 {
367         struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
368         struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
369
370         clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
371                 CCM_CCGR0_UART1_CTRL_MASK);
372         clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
373                 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
374         clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
375                 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
376                 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
377                 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
378                 CCM_CCGR2_QSPI0_CTRL_MASK);
379         clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
380                 CCM_CCGR3_ANADIG_CTRL_MASK);
381         clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
382                 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
383                 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
384         clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
385                 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
386         clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
387                 CCM_CCGR7_SDHC1_CTRL_MASK);
388         clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
389                 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
390         clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
391                 CCM_CCGR10_NFC_CTRL_MASK);
392
393         clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
394                 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
395         clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
396                 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
397
398         clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
399                 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
400         clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
401                 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
402                 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
403                 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
404                 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
405                 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
406                 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
407         clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
408                 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
409                 CCM_CACRR_ARM_CLK_DIV(0));
410         clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
411                 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
412                 CCM_CSCMR1_NFC_CLK_SEL(0));
413         clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
414                 CCM_CSCDR1_RMII_CLK_EN);
415         clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
416                 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
417                 CCM_CSCDR2_NFC_EN);
418         clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
419                 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
420                 CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
421                 CCM_CSCDR3_NFC_PRE_DIV(5));
422         clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
423                 CCM_CSCMR2_RMII_CLK_SEL(0));
424 }
425
426 static void mscm_init(void)
427 {
428         struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
429         int i;
430
431         for (i = 0; i < MSCM_IRSPRC_NUM; i++)
432                 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
433 }
434
435 int board_phy_config(struct phy_device *phydev)
436 {
437         if (phydev->drv->config)
438                 phydev->drv->config(phydev);
439
440         return 0;
441 }
442
443 int board_early_init_f(void)
444 {
445         clock_init();
446         mscm_init();
447
448         setup_iomux_uart();
449         setup_iomux_enet();
450         setup_iomux_i2c();
451         setup_iomux_qspi();
452 #ifdef CONFIG_NAND_VF610_NFC
453         setup_iomux_nfc();
454 #endif
455
456         return 0;
457 }
458
459 int board_init(void)
460 {
461         /* address of boot parameters */
462         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
463
464         return 0;
465 }
466
467 int checkboard(void)
468 {
469         puts("Board: vf610twr\n");
470
471         return 0;
472 }