board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/video.h>
  24 #include <jffs2/load_kernel.h>
  25 #include <hwconfig.h>
  26 #include <i2c.h>
  27 #include <linux/ctype.h>
  28 #include <fdt_support.h>
  29 #include <fsl_esdhc.h>
  30 #include <miiphy.h>
  31 #include <mmc.h>
  32 #include <mtd_node.h>
  33 #include <netdev.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "ventana_eeprom.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* GPIO's common to all baseboards */
  47 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  48 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  49 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  50 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  51 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  52
  53 /* I2C bus numbers */
  54 #define I2C_GSC         0
  55 #define I2C_PMIC        1
  56
  57 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  58         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  59         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  60
  61 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  62         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  63         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  64
  65 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  66         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  67         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  68
  69 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  70         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  71         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  72
  73 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  74         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  75         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  76
  77 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  78         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  79         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  80
  81 /*
  82  * EEPROM board info struct populated by read_eeprom so that we only have to
  83  * read it once.
  84  */
  85 static struct ventana_board_info ventana_info;
  86
  87 int board_type;
  88
  89 /* UART1: Function varies per baseboard */
  90 iomux_v3_cfg_t const uart1_pads[] = {
  91         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  92         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  93 };
  94
  95 /* UART2: Serial Console */
  96 iomux_v3_cfg_t const uart2_pads[] = {
  97         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  98         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  99 };
 100
 101 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 102
 103 /* I2C1: GSC */
 104 struct i2c_pads_info mx6q_i2c_pad_info0 = {
 105         .scl = {
 106                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 107                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 108                 .gp = IMX_GPIO_NR(3, 21)
 109         },
 110         .sda = {
 111                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 112                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 113                 .gp = IMX_GPIO_NR(3, 28)
 114         }
 115 };
 116 struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 117         .scl = {
 118                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 119                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 120                 .gp = IMX_GPIO_NR(3, 21)
 121         },
 122         .sda = {
 123                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 124                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 125                 .gp = IMX_GPIO_NR(3, 28)
 126         }
 127 };
 128
 129 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 130 struct i2c_pads_info mx6q_i2c_pad_info1 = {
 131         .scl = {
 132                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 133                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 134                 .gp = IMX_GPIO_NR(4, 12)
 135         },
 136         .sda = {
 137                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 138                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 139                 .gp = IMX_GPIO_NR(4, 13)
 140         }
 141 };
 142 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 143         .scl = {
 144                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 145                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 146                 .gp = IMX_GPIO_NR(4, 12)
 147         },
 148         .sda = {
 149                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 150                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 151                 .gp = IMX_GPIO_NR(4, 13)
 152         }
 153 };
 154
 155 /* I2C3: Misc/Expansion */
 156 struct i2c_pads_info mx6q_i2c_pad_info2 = {
 157         .scl = {
 158                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 159                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 160                 .gp = IMX_GPIO_NR(1, 3)
 161         },
 162         .sda = {
 163                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 164                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 165                 .gp = IMX_GPIO_NR(1, 6)
 166         }
 167 };
 168 struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 169         .scl = {
 170                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 171                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 172                 .gp = IMX_GPIO_NR(1, 3)
 173         },
 174         .sda = {
 175                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 176                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 177                 .gp = IMX_GPIO_NR(1, 6)
 178         }
 179 };
 180
 181 /* MMC */
 182 iomux_v3_cfg_t const usdhc3_pads[] = {
 183         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 184         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 185         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 186         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 187         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 188         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 189         /* CD */
 190         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 191 };
 192
 193 /* ENET */
 194 iomux_v3_cfg_t const enet_pads[] = {
 195         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 196         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 197         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 198         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 199         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 200         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 201         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 202         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 203                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 205                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 206         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 208         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 210         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 212                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         /* PHY nRST */
 214         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 215 };
 216
 217 /* NAND */
 218 iomux_v3_cfg_t const nfc_pads[] = {
 219         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 220         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 221         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 222         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 223         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 224         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 225         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 226         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234 };
 235
 236 #ifdef CONFIG_CMD_NAND
 237 static void setup_gpmi_nand(void)
 238 {
 239         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 240
 241         /* config gpmi nand iomux */
 242         SETUP_IOMUX_PADS(nfc_pads);
 243
 244         /* config gpmi and bch clock to 100 MHz */
 245         clrsetbits_le32(&mxc_ccm->cs2cdr,
 246                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 247                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 248                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 249                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 250                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 251                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 252
 253         /* enable gpmi and bch clock gating */
 254         setbits_le32(&mxc_ccm->CCGR4,
 255                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 256                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 257                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 258                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 259                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 260
 261         /* enable apbh clock gating */
 262         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 263 }
 264 #endif
 265
 266 static void setup_iomux_enet(void)
 267 {
 268         SETUP_IOMUX_PADS(enet_pads);
 269
 270         /* toggle PHY_RST# */
 271         gpio_direction_output(GP_PHY_RST, 0);
 272         mdelay(2);
 273         gpio_set_value(GP_PHY_RST, 1);
 274 }
 275
 276 static void setup_iomux_uart(void)
 277 {
 278         SETUP_IOMUX_PADS(uart1_pads);
 279         SETUP_IOMUX_PADS(uart2_pads);
 280 }
 281
 282 #ifdef CONFIG_USB_EHCI_MX6
 283 iomux_v3_cfg_t const usb_pads[] = {
 284         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | MUX_PAD_CTRL(DIO_PAD_CTRL)),
 285         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)),
 286         /* OTG PWR */
 287         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | MUX_PAD_CTRL(DIO_PAD_CTRL)),
 288 };
 289
 290 int board_ehci_hcd_init(int port)
 291 {
 292         struct ventana_board_info *info = &ventana_info;
 293
 294         SETUP_IOMUX_PADS(usb_pads);
 295
 296         /* Reset USB HUB (present on GW54xx/GW53xx) */
 297         switch (info->model[3]) {
 298         case '3': /* GW53xx */
 299                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 |
 300                                 MUX_PAD_CTRL(NO_PAD_CTRL));
 301                 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 302                 mdelay(2);
 303                 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 304                 break;
 305         case '4': /* GW54xx */
 306                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 |
 307                                 MUX_PAD_CTRL(NO_PAD_CTRL));
 308                 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 309                 mdelay(2);
 310                 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 311                 break;
 312         }
 313
 314         return 0;
 315 }
 316
 317 int board_ehci_power(int port, int on)
 318 {
 319         if (port)
 320                 return 0;
 321         gpio_set_value(GP_USB_OTG_PWR, on);
 322         return 0;
 323 }
 324 #endif /* CONFIG_USB_EHCI_MX6 */
 325
 326 #ifdef CONFIG_FSL_ESDHC
 327 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 328
 329 int board_mmc_getcd(struct mmc *mmc)
 330 {
 331         /* Card Detect */
 332         gpio_direction_input(GP_SD3_CD);
 333         return !gpio_get_value(GP_SD3_CD);
 334 }
 335
 336 int board_mmc_init(bd_t *bis)
 337 {
 338         /* Only one USDHC controller on Ventana */
 339         SETUP_IOMUX_PADS(usdhc3_pads);
 340         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 341         usdhc_cfg.max_bus_width = 4;
 342
 343         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 344 }
 345 #endif /* CONFIG_FSL_ESDHC */
 346
 347 #ifdef CONFIG_MXC_SPI
 348 iomux_v3_cfg_t const ecspi1_pads[] = {
 349         /* SS1 */
 350         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 351         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 352         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 353         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 354 };
 355
 356 static void setup_spi(void)
 357 {
 358         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 359         SETUP_IOMUX_PADS(ecspi1_pads);
 360 }
 361 #endif
 362
 363 /* configure eth0 PHY board-specific LED behavior */
 364 int board_phy_config(struct phy_device *phydev)
 365 {
 366         unsigned short val;
 367
 368         /* Marvel 88E1510 */
 369         if (phydev->phy_id == 0x1410dd1) {
 370                 /*
 371                  * Page 3, Register 16: LED[2:0] Function Control Register
 372                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 373                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 374                  */
 375                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 376                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 377                 val &= 0xff00;
 378                 val |= 0x0017;
 379                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 380                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 381         }
 382
 383         if (phydev->drv->config)
 384                 phydev->drv->config(phydev);
 385
 386         return 0;
 387 }
 388
 389 int board_eth_init(bd_t *bis)
 390 {
 391         setup_iomux_enet();
 392
 393 #ifdef CONFIG_FEC_MXC
 394         cpu_eth_init(bis);
 395 #endif
 396
 397 #ifdef CONFIG_CI_UDC
 398         /* For otg ethernet*/
 399         usb_eth_initialize(bis);
 400 #endif
 401
 402         return 0;
 403 }
 404
 405 #if defined(CONFIG_VIDEO_IPUV3)
 406
 407 static void enable_hdmi(struct display_info_t const *dev)
 408 {
 409         imx_enable_hdmi_phy();
 410 }
 411
 412 static int detect_i2c(struct display_info_t const *dev)
 413 {
 414         return i2c_set_bus_num(dev->bus) == 0 &&
 415                 i2c_probe(dev->addr) == 0;
 416 }
 417
 418 static void enable_lvds(struct display_info_t const *dev)
 419 {
 420         struct iomuxc *iomux = (struct iomuxc *)
 421                                 IOMUXC_BASE_ADDR;
 422
 423         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 424         u32 reg = readl(&iomux->gpr[2]);
 425         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 426         writel(reg, &iomux->gpr[2]);
 427
 428         /* Enable Backlight */
 429         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL));
 430         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 431 }
 432
 433 struct display_info_t const displays[] = {{
 434         /* HDMI Output */
 435         .bus    = -1,
 436         .addr   = 0,
 437         .pixfmt = IPU_PIX_FMT_RGB24,
 438         .detect = detect_hdmi,
 439         .enable = enable_hdmi,
 440         .mode   = {
 441                 .name           = "HDMI",
 442                 .refresh        = 60,
 443                 .xres           = 1024,
 444                 .yres           = 768,
 445                 .pixclock       = 15385,
 446                 .left_margin    = 220,
 447                 .right_margin   = 40,
 448                 .upper_margin   = 21,
 449                 .lower_margin   = 7,
 450                 .hsync_len      = 60,
 451                 .vsync_len      = 10,
 452                 .sync           = FB_SYNC_EXT,
 453                 .vmode          = FB_VMODE_NONINTERLACED
 454 } }, {
 455         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 456         .bus    = 2,
 457         .addr   = 0x4,
 458         .pixfmt = IPU_PIX_FMT_LVDS666,
 459         .detect = detect_i2c,
 460         .enable = enable_lvds,
 461         .mode   = {
 462                 .name           = "Hannstar-XGA",
 463                 .refresh        = 60,
 464                 .xres           = 1024,
 465                 .yres           = 768,
 466                 .pixclock       = 15385,
 467                 .left_margin    = 220,
 468                 .right_margin   = 40,
 469                 .upper_margin   = 21,
 470                 .lower_margin   = 7,
 471                 .hsync_len      = 60,
 472                 .vsync_len      = 10,
 473                 .sync           = FB_SYNC_EXT,
 474                 .vmode          = FB_VMODE_NONINTERLACED
 475 } } };
 476 size_t display_count = ARRAY_SIZE(displays);
 477
 478 static void setup_display(void)
 479 {
 480         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 481         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 482         int reg;
 483
 484         enable_ipu_clock();
 485         imx_setup_hdmi();
 486         /* Turn on LDB0,IPU,IPU DI0 clocks */
 487         reg = __raw_readl(&mxc_ccm->CCGR3);
 488         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 489         writel(reg, &mxc_ccm->CCGR3);
 490
 491         /* set LDB0, LDB1 clk select to 011/011 */
 492         reg = readl(&mxc_ccm->cs2cdr);
 493         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 494                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 495         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 496               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 497         writel(reg, &mxc_ccm->cs2cdr);
 498
 499         reg = readl(&mxc_ccm->cscmr2);
 500         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 501         writel(reg, &mxc_ccm->cscmr2);
 502
 503         reg = readl(&mxc_ccm->chsccdr);
 504         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 505                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 506         writel(reg, &mxc_ccm->chsccdr);
 507
 508         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 509              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 510              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 511              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 512              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 513              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 514              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 515              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 516              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 517         writel(reg, &iomux->gpr[2]);
 518
 519         reg = readl(&iomux->gpr[3]);
 520         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 521             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 522                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 523         writel(reg, &iomux->gpr[3]);
 524
 525         /* Backlight CABEN on LVDS connector */
 526         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL));
 527         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 528 }
 529 #endif /* CONFIG_VIDEO_IPUV3 */
 530
 531 /*
 532  * Baseboard specific GPIO
 533  */
 534
 535 /* common to add baseboards */
 536 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 537         /* MSATA_EN */
 538         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 539         /* RS232_EN# */
 540         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 541 };
 542
 543 /* prototype */
 544 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 545         /* PANLEDG# */
 546         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 547         /* PANLEDR# */
 548         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 549         /* LOCLED# */
 550         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 551         /* RS485_EN */
 552         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 553         /* IOEXP_PWREN# */
 554         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 555         /* IOEXP_IRQ# */
 556         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 557         /* VID_EN */
 558         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 559         /* DIOI2C_DIS# */
 560         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 561         /* PCICK_SSON */
 562         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 563         /* PCI_RST# */
 564         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 565 };
 566
 567 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 568         /* PANLEDG# */
 569         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 570         /* PANLEDR# */
 571         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 572         /* IOEXP_PWREN# */
 573         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 574         /* IOEXP_IRQ# */
 575         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 576
 577         /* GPS_SHDN */
 578         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 579         /* VID_PWR */
 580         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 581         /* PCI_RST# */
 582         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 583 };
 584
 585 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 586         /* PANLEDG# */
 587         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 588         /* PANLEDR# */
 589         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 590         /* IOEXP_PWREN# */
 591         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 592         /* IOEXP_IRQ# */
 593         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 594
 595         /* MX6_LOCLED# */
 596         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 597         /* GPS_SHDN */
 598         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 599         /* USBOTG_SEL */
 600         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 601         /* VID_PWR */
 602         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 603         /* PCI_RST# */
 604         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 605 };
 606
 607 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 608         /* PANLEDG# */
 609         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 610         /* PANLEDR# */
 611         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 612         /* IOEXP_PWREN# */
 613         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 614         /* IOEXP_IRQ# */
 615         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 616
 617         /* MX6_LOCLED# */
 618         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 619         /* GPS_SHDN */
 620         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 621         /* VID_EN */
 622         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 623         /* PCI_RST# */
 624         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 625 };
 626
 627 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 628         /* PANLEDG# */
 629         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 630         /* PANLEDR# */
 631         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 632         /* MX6_LOCLED# */
 633         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 634         /* MIPI_DIO */
 635         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 636         /* RS485_EN */
 637         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 638         /* IOEXP_PWREN# */
 639         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 640         /* IOEXP_IRQ# */
 641         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 642         /* DIOI2C_DIS# */
 643         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 644         /* DIOI2C_DIS# */
 645         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 646         /* PCICK_SSON */
 647         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 648         /* PCI_RST# */
 649         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 650 };
 651
 652 /*
 653  * each baseboard has 4 user configurable Digital IO lines which can
 654  * be pinmuxed as a GPIO or in some cases a PWM
 655  */
 656 struct dio_cfg {
 657         iomux_v3_cfg_t gpio_padmux[2];
 658         unsigned gpio_param;
 659         iomux_v3_cfg_t pwm_padmux[2];
 660         unsigned pwm_param;
 661 };
 662
 663 struct ventana {
 664         /* pinmux */
 665         iomux_v3_cfg_t const *gpio_pads;
 666         int num_pads;
 667         /* DIO pinmux/val */
 668         struct dio_cfg dio_cfg[4];
 669         /* various gpios (0 if non-existent) */
 670         int leds[3];
 671         int pcie_rst;
 672         int mezz_pwren;
 673         int mezz_irq;
 674         int rs485en;
 675         int gps_shdn;
 676         int vidin_en;
 677         int dioi2c_en;
 678         int pcie_sson;
 679         int usb_sel;
 680 };
 681
 682 struct ventana gpio_cfg[] = {
 683         /* GW5400proto */
 684         {
 685                 .gpio_pads = gw54xx_gpio_pads,
 686                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 687                 .dio_cfg = {
 688                         {
 689                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 690                                 IMX_GPIO_NR(1, 9),
 691                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 692                                 1
 693                         },
 694                         {
 695                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 696                                 IMX_GPIO_NR(1, 19),
 697                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 698                                 2
 699                         },
 700                         {
 701                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 702                                 IMX_GPIO_NR(2, 9),
 703                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 704                                 3
 705                         },
 706                         {
 707                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 708                                 IMX_GPIO_NR(2, 10),
 709                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 710                                 4
 711                         },
 712                 },
 713                 .leds = {
 714                         IMX_GPIO_NR(4, 6),
 715                         IMX_GPIO_NR(4, 10),
 716                         IMX_GPIO_NR(4, 15),
 717                 },
 718                 .pcie_rst = IMX_GPIO_NR(1, 29),
 719                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 720                 .mezz_irq = IMX_GPIO_NR(4, 9),
 721                 .rs485en = IMX_GPIO_NR(3, 24),
 722                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 723                 .pcie_sson = IMX_GPIO_NR(1, 20),
 724         },
 725
 726         /* GW51xx */
 727         {
 728                 .gpio_pads = gw51xx_gpio_pads,
 729                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 730                 .dio_cfg = {
 731                         {
 732                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 733                                 IMX_GPIO_NR(1, 16),
 734                                 { 0, 0 },
 735                                 0
 736                         },
 737                         {
 738                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 739                                 IMX_GPIO_NR(1, 19),
 740                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 741                                 2
 742                         },
 743                         {
 744                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 745                                 IMX_GPIO_NR(1, 17),
 746                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 747                                 3
 748                         },
 749                         {
 750                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 751                                 IMX_GPIO_NR(1, 18),
 752                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 753                                 4
 754                         },
 755                 },
 756                 .leds = {
 757                         IMX_GPIO_NR(4, 6),
 758                         IMX_GPIO_NR(4, 10),
 759                 },
 760                 .pcie_rst = IMX_GPIO_NR(1, 0),
 761                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 762                 .mezz_irq = IMX_GPIO_NR(2, 18),
 763                 .gps_shdn = IMX_GPIO_NR(1, 2),
 764                 .vidin_en = IMX_GPIO_NR(5, 20),
 765         },
 766
 767         /* GW52xx */
 768         {
 769                 .gpio_pads = gw52xx_gpio_pads,
 770                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 771                 .dio_cfg = {
 772                         {
 773                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 774                                 IMX_GPIO_NR(1, 16),
 775                                 { 0, 0 },
 776                                 0
 777                         },
 778                         {
 779                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 780                                 IMX_GPIO_NR(1, 19),
 781                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 782                                 2
 783                         },
 784                         {
 785                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 786                                 IMX_GPIO_NR(1, 17),
 787                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 788                                 3
 789                         },
 790                         {
 791                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 792                                 IMX_GPIO_NR(1, 20),
 793                                 { 0, 0 },
 794                                 0
 795                         },
 796                 },
 797                 .leds = {
 798                         IMX_GPIO_NR(4, 6),
 799                         IMX_GPIO_NR(4, 7),
 800                         IMX_GPIO_NR(4, 15),
 801                 },
 802                 .pcie_rst = IMX_GPIO_NR(1, 29),
 803                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 804                 .mezz_irq = IMX_GPIO_NR(2, 18),
 805                 .gps_shdn = IMX_GPIO_NR(1, 27),
 806                 .vidin_en = IMX_GPIO_NR(3, 31),
 807                 .usb_sel = IMX_GPIO_NR(1, 2),
 808         },
 809
 810         /* GW53xx */
 811         {
 812                 .gpio_pads = gw53xx_gpio_pads,
 813                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 814                 .dio_cfg = {
 815                         {
 816                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 817                                 IMX_GPIO_NR(1, 16),
 818                                 { 0, 0 },
 819                                 0
 820                         },
 821                         {
 822                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 823                                 IMX_GPIO_NR(1, 19),
 824                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 825                                 2
 826                         },
 827                         {
 828                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 829                                 IMX_GPIO_NR(1, 17),
 830                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 831                                 3
 832                         },
 833                         {
 834                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 835                                 IMX_GPIO_NR(1, 20),
 836                                 { 0, 0 },
 837                                 0
 838                         },
 839                 },
 840                 .leds = {
 841                         IMX_GPIO_NR(4, 6),
 842                         IMX_GPIO_NR(4, 7),
 843                         IMX_GPIO_NR(4, 15),
 844                 },
 845                 .pcie_rst = IMX_GPIO_NR(1, 29),
 846                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 847                 .mezz_irq = IMX_GPIO_NR(2, 18),
 848                 .gps_shdn = IMX_GPIO_NR(1, 27),
 849                 .vidin_en = IMX_GPIO_NR(3, 31),
 850         },
 851
 852         /* GW54xx */
 853         {
 854                 .gpio_pads = gw54xx_gpio_pads,
 855                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 856                 .dio_cfg = {
 857                         {
 858                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 859                                 IMX_GPIO_NR(1, 9),
 860                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 861                                 1
 862                         },
 863                         {
 864                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 865                                 IMX_GPIO_NR(1, 19),
 866                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 867                                 2
 868                         },
 869                         {
 870                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 871                                 IMX_GPIO_NR(2, 9),
 872                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 873                                 3
 874                         },
 875                         {
 876                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 877                                 IMX_GPIO_NR(2, 10),
 878                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 879                                 4
 880                         },
 881                 },
 882                 .leds = {
 883                         IMX_GPIO_NR(4, 6),
 884                         IMX_GPIO_NR(4, 7),
 885                         IMX_GPIO_NR(4, 15),
 886                 },
 887                 .pcie_rst = IMX_GPIO_NR(1, 29),
 888                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 889                 .mezz_irq = IMX_GPIO_NR(2, 18),
 890                 .rs485en = IMX_GPIO_NR(7, 1),
 891                 .vidin_en = IMX_GPIO_NR(3, 31),
 892                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 893                 .pcie_sson = IMX_GPIO_NR(1, 20),
 894         },
 895 };
 896
 897 /* setup board specific PMIC */
 898 int power_init_board(void)
 899 {
 900         struct pmic *p;
 901         u32 reg;
 902
 903         /* configure PFUZE100 PMIC */
 904         if (board_type == GW54xx || board_type == GW54proto) {
 905                 power_pfuze100_init(I2C_PMIC);
 906                 p = pmic_get("PFUZE100_PMIC");
 907                 if (p && !pmic_probe(p)) {
 908                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 909                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 910
 911                         /* Set VGEN1 to 1.5V and enable */
 912                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
 913                         reg &= ~(LDO_VOL_MASK);
 914                         reg |= (LDOA_1_50V | LDO_EN);
 915                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
 916
 917                         /* Set SWBST to 5.0V and enable */
 918                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
 919                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
 920                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
 921                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
 922                 }
 923         }
 924
 925         /* configure LTC3676 PMIC */
 926         else {
 927                 power_ltc3676_init(I2C_PMIC);
 928                 p = pmic_get("LTC3676_PMIC");
 929                 if (p && !pmic_probe(p)) {
 930                         puts("PMIC:  LTC3676\n");
 931                         /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
 932                         if (is_cpu_type(MXC_CPU_MX6Q)) {
 933                                 /* mask PGOOD during SW1 transition */
 934                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 935                                 pmic_reg_write(p, LTC3676_DVB1B, reg);
 936                                 /* set SW1 (VDD_SOC) to 1259mV */
 937                                 reg = 0x1d;
 938                                 pmic_reg_write(p, LTC3676_DVB1A, reg);
 939
 940                                 /* mask PGOOD during SW3 transition */
 941                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 942                                 pmic_reg_write(p, LTC3676_DVB3B, reg);
 943                                 /*set SW3 (VDD_ARM) to 1259mV */
 944                                 reg = 0x1d;
 945                                 pmic_reg_write(p, LTC3676_DVB3A, reg);
 946                         }
 947                 }
 948         }
 949
 950         return 0;
 951 }
 952
 953 /* setup GPIO pinmux and default configuration per baseboard */
 954 static void setup_board_gpio(int board)
 955 {
 956         struct ventana_board_info *info = &ventana_info;
 957         const char *s;
 958         char arg[10];
 959         size_t len;
 960         int i;
 961         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
 962
 963         if (board >= GW_UNKNOWN)
 964                 return;
 965
 966         /* RS232_EN# */
 967         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
 968
 969         /* MSATA Enable */
 970         if (is_cpu_type(MXC_CPU_MX6Q) &&
 971             test_bit(EECONFIG_SATA, info->config)) {
 972                 gpio_direction_output(GP_MSATA_SEL,
 973                                       (hwconfig("msata")) ?  1 : 0);
 974         } else {
 975                 gpio_direction_output(GP_MSATA_SEL, 0);
 976         }
 977
 978         /*
 979          * assert PCI_RST# (released by OS when clock is valid)
 980          * TODO: figure out why leaving this de-asserted from PCI scan on boot
 981          *       causes linux pcie driver to hang during enumeration
 982          */
 983         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
 984
 985         /* turn off (active-high) user LED's */
 986         for (i = 0; i < 4; i++) {
 987                 if (gpio_cfg[board].leds[i])
 988                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
 989         }
 990
 991         /* Expansion Mezzanine IO */
 992         gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
 993         gpio_direction_input(gpio_cfg[board].mezz_irq);
 994
 995         /* RS485 Transmit Enable */
 996         if (gpio_cfg[board].rs485en)
 997                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
 998
 999         /* GPS_SHDN */
1000         if (gpio_cfg[board].gps_shdn)
1001                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1002
1003         /* Analog video codec power enable */
1004         if (gpio_cfg[board].vidin_en)
1005                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1006
1007         /* DIOI2C_DIS# */
1008         if (gpio_cfg[board].dioi2c_en)
1009                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1010
1011         /* PCICK_SSON: disable spread-spectrum clock */
1012         if (gpio_cfg[board].pcie_sson)
1013                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1014
1015         /* USBOTG Select (PCISKT or FrontPanel) */
1016         if (gpio_cfg[board].usb_sel)
1017                 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1018
1019         /*
1020          * Configure DIO pinmux/padctl registers
1021          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1022          */
1023         for (i = 0; i < 4; i++) {
1024                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1025                 unsigned ctrl = DIO_PAD_CTRL;
1026                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1027
1028                 sprintf(arg, "dio%d", i);
1029                 if (!hwconfig(arg))
1030                         continue;
1031                 s = hwconfig_subarg(arg, "padctrl", &len);
1032                 if (s)
1033                         ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
1034                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1035                         if (!quiet) {
1036                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1037                                        (cfg->gpio_param/32)+1,
1038                                        cfg->gpio_param%32,
1039                                        cfg->gpio_param);
1040                         }
1041                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1042                                                MUX_PAD_CTRL(ctrl));
1043                         gpio_direction_input(cfg->gpio_param);
1044                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1045                            cfg->pwm_padmux) {
1046                         if (!quiet)
1047                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1048                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1049                                                MUX_PAD_CTRL(ctrl));
1050                 }
1051         }
1052
1053         if (!quiet) {
1054                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1055                     (test_bit(EECONFIG_SATA, info->config))) {
1056                         printf("MSATA: %s\n", (hwconfig("msata") ?
1057                                "enabled" : "disabled"));
1058                 }
1059                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1060                        "enabled" : "disabled");
1061         }
1062 }
1063
1064 #if defined(CONFIG_CMD_PCI)
1065 int imx6_pcie_toggle_reset(void)
1066 {
1067         if (board_type < GW_UNKNOWN) {
1068                 uint pin = gpio_cfg[board_type].pcie_rst;
1069                 gpio_direction_output(pin, 0);
1070                 mdelay(50);
1071                 gpio_direction_output(pin, 1);
1072         }
1073         return 0;
1074 }
1075 #endif /* CONFIG_CMD_PCI */
1076
1077 #ifdef CONFIG_SERIAL_TAG
1078 /*
1079  * called when setting up ATAGS before booting kernel
1080  * populate serialnum from the following (in order of priority):
1081  *   serial# env var
1082  *   eeprom
1083  */
1084 void get_board_serial(struct tag_serialnr *serialnr)
1085 {
1086         char *serial = getenv("serial#");
1087
1088         if (serial) {
1089                 serialnr->high = 0;
1090                 serialnr->low = simple_strtoul(serial, NULL, 10);
1091         } else if (ventana_info.model[0]) {
1092                 serialnr->high = 0;
1093                 serialnr->low = ventana_info.serial;
1094         } else {
1095                 serialnr->high = 0;
1096                 serialnr->low = 0;
1097         }
1098 }
1099 #endif
1100
1101 /*
1102  * Board Support
1103  */
1104
1105 /* called from SPL board_init_f() */
1106 int board_early_init_f(void)
1107 {
1108         setup_iomux_uart();
1109         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1110
1111 #if defined(CONFIG_VIDEO_IPUV3)
1112         setup_display();
1113 #endif
1114         return 0;
1115 }
1116
1117 int dram_init(void)
1118 {
1119         gd->ram_size = imx_ddr_size();
1120         return 0;
1121 }
1122
1123 int board_init(void)
1124 {
1125         struct iomuxc_base_regs *const iomuxc_regs
1126                 = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
1127
1128         clrsetbits_le32(&iomuxc_regs->gpr[1],
1129                         IOMUXC_GPR1_OTG_ID_MASK,
1130                         IOMUXC_GPR1_OTG_ID_GPIO1);
1131
1132         /* address of linux boot parameters */
1133         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1134
1135 #ifdef CONFIG_CMD_NAND
1136         setup_gpmi_nand();
1137 #endif
1138 #ifdef CONFIG_MXC_SPI
1139         setup_spi();
1140 #endif
1141         if (is_cpu_type(MXC_CPU_MX6Q)) {
1142                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1143                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1144                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1145         } else {
1146                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1147                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1148                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1149         }
1150
1151 #ifdef CONFIG_CMD_SATA
1152         setup_sata();
1153 #endif
1154         /* read Gateworks EEPROM into global struct (used later) */
1155         board_type = read_eeprom(I2C_GSC, &ventana_info);
1156
1157         /* board-specifc GPIO iomux */
1158         SETUP_IOMUX_PADS(gw_gpio_pads);
1159         if (board_type < GW_UNKNOWN) {
1160                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1161                 int count = gpio_cfg[board_type].num_pads;
1162
1163                 imx_iomux_v3_setup_multiple_pads(p, count);
1164         }
1165
1166         return 0;
1167 }
1168
1169 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1170 /*
1171  * called during late init (after relocation and after board_init())
1172  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1173  * EEPROM read.
1174  */
1175 int checkboard(void)
1176 {
1177         struct ventana_board_info *info = &ventana_info;
1178         unsigned char buf[4];
1179         const char *p;
1180         int quiet; /* Quiet or minimal output mode */
1181
1182         quiet = 0;
1183         p = getenv("quiet");
1184         if (p)
1185                 quiet = simple_strtol(p, NULL, 10);
1186         else
1187                 setenv("quiet", "0");
1188
1189         puts("\nGateworks Corporation Copyright 2014\n");
1190         if (info->model[0]) {
1191                 printf("Model: %s\n", info->model);
1192                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1193                        info->mfgdate[0], info->mfgdate[1],
1194                        info->mfgdate[2], info->mfgdate[3]);
1195                 printf("Serial:%d\n", info->serial);
1196         } else {
1197                 puts("Invalid EEPROM - board will not function fully\n");
1198         }
1199         if (quiet)
1200                 return 0;
1201
1202         /* Display GSC firmware revision/CRC/status */
1203         i2c_set_bus_num(I2C_GSC);
1204         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1205                 printf("GSC:   v%d", buf[0]);
1206                 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1207                         printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1208                         printf(" 0x%02x", buf[0]); /* irq status */
1209                 }
1210                 puts("\n");
1211         }
1212         /* Display RTC */
1213         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1214                 printf("RTC:   %d\n",
1215                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1216         }
1217
1218         return 0;
1219 }
1220 #endif
1221
1222 #ifdef CONFIG_CMD_BMODE
1223 /*
1224  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1225  * see Table 8-11 and Table 5-9
1226  *  BOOT_CFG1[7] = 1 (boot from NAND)
1227  *  BOOT_CFG1[5] = 0 - raw NAND
1228  *  BOOT_CFG1[4] = 0 - default pad settings
1229  *  BOOT_CFG1[3:2] = 00 - devices = 1
1230  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1231  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1232  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1233  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1234  */
1235 static const struct boot_mode board_boot_modes[] = {
1236         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1237         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1238         { NULL, 0 },
1239 };
1240 #endif
1241
1242 /* late init */
1243 int misc_init_r(void)
1244 {
1245         struct ventana_board_info *info = &ventana_info;
1246         unsigned char reg;
1247
1248         /* set env vars based on EEPROM data */
1249         if (ventana_info.model[0]) {
1250                 char str[16], fdt[36];
1251                 char *p;
1252                 const char *cputype = "";
1253                 int i;
1254
1255                 /*
1256                  * FDT name will be prefixed with CPU type.  Three versions
1257                  * will be created each increasingly generic and bootloader
1258                  * env scripts will try loading each from most specific to
1259                  * least.
1260                  */
1261                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1262                     is_cpu_type(MXC_CPU_MX6D))
1263                         cputype = "imx6q";
1264                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1265                          is_cpu_type(MXC_CPU_MX6SOLO))
1266                         cputype = "imx6dl";
1267                 memset(str, 0, sizeof(str));
1268                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1269                         str[i] = tolower(info->model[i]);
1270                 if (!getenv("model"))
1271                         setenv("model", str);
1272                 if (!getenv("fdt_file")) {
1273                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1274                         setenv("fdt_file", fdt);
1275                 }
1276                 p = strchr(str, '-');
1277                 if (p) {
1278                         *p++ = 0;
1279
1280                         setenv("model_base", str);
1281                         if (!getenv("fdt_file1")) {
1282                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1283                                 setenv("fdt_file1", fdt);
1284                         }
1285                         str[4] = 'x';
1286                         str[5] = 'x';
1287                         str[6] = 0;
1288                         if (!getenv("fdt_file2")) {
1289                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1290                                 setenv("fdt_file2", fdt);
1291                         }
1292                 }
1293
1294                 /* initialize env from EEPROM */
1295                 if (test_bit(EECONFIG_ETH0, info->config) &&
1296                     !getenv("ethaddr")) {
1297                         eth_setenv_enetaddr("ethaddr", info->mac0);
1298                 }
1299                 if (test_bit(EECONFIG_ETH1, info->config) &&
1300                     !getenv("eth1addr")) {
1301                         eth_setenv_enetaddr("eth1addr", info->mac1);
1302                 }
1303
1304                 /* board serial-number */
1305                 sprintf(str, "%6d", info->serial);
1306                 setenv("serial#", str);
1307         }
1308
1309
1310         /* setup baseboard specific GPIO pinmux and config */
1311         setup_board_gpio(board_type);
1312
1313 #ifdef CONFIG_CMD_BMODE
1314         add_board_boot_modes(board_boot_modes);
1315 #endif
1316
1317         /*
1318          *  The Gateworks System Controller implements a boot
1319          *  watchdog (always enabled) as a workaround for IMX6 boot related
1320          *  errata such as:
1321          *    ERR005768 - no fix
1322          *    ERR006282 - fixed in silicon r1.3
1323          *    ERR007117 - fixed in silicon r1.3
1324          *    ERR007220 - fixed in silicon r1.3
1325          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1326          *
1327          * Disable the boot watchdog and display/clear the timeout flag if set
1328          */
1329         i2c_set_bus_num(I2C_GSC);
1330         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1331                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1332                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1333                         puts("Error: could not disable GSC Watchdog\n");
1334         } else {
1335                 puts("Error: could not disable GSC Watchdog\n");
1336         }
1337         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1338                 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1339                         puts("GSC boot watchdog timeout detected");
1340                         reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1341                         gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1342                 }
1343         }
1344
1345         return 0;
1346 }
1347
1348 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1349
1350 /* FDT aliases associated with EEPROM config bits */
1351 const char *fdt_aliases[] = {
1352         "ethernet0",
1353         "ethernet1",
1354         "hdmi_out",
1355         "ahci0",
1356         "pcie",
1357         "ssi0",
1358         "ssi1",
1359         "lcd0",
1360         "lvds0",
1361         "lvds1",
1362         "usb0",
1363         "usb1",
1364         "mmc0",
1365         "mmc1",
1366         "mmc2",
1367         "mmc3",
1368         "uart0",
1369         "uart1",
1370         "uart2",
1371         "uart3",
1372         "uart4",
1373         "ipu0",
1374         "ipu1",
1375         "can0",
1376         "mipi_dsi",
1377         "mipi_csi",
1378         "tzasc0",
1379         "tzasc1",
1380         "i2c0",
1381         "i2c1",
1382         "i2c2",
1383         "vpu",
1384         "csi0",
1385         "csi1",
1386         "caam",
1387         NULL,
1388         NULL,
1389         NULL,
1390         NULL,
1391         NULL,
1392         "spi0",
1393         "spi1",
1394         "spi2",
1395         "spi3",
1396         "spi4",
1397         "spi5",
1398         NULL,
1399         NULL,
1400         "pps",
1401         NULL,
1402         NULL,
1403         NULL,
1404         "hdmi_in",
1405         "cvbs_out",
1406         "cvbs_in",
1407         "nand",
1408         NULL,
1409         NULL,
1410         NULL,
1411         NULL,
1412         NULL,
1413         NULL,
1414         NULL,
1415         NULL,
1416 };
1417
1418 /*
1419  * called prior to booting kernel or by 'fdt boardsetup' command
1420  *
1421  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1422  *  - mtd partitions based on mtdparts/mtdids env
1423  *  - system-serial (board serial num from EEPROM)
1424  *  - board (full model from EEPROM)
1425  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1426  */
1427 void ft_board_setup(void *blob, bd_t *bd)
1428 {
1429         int bit;
1430         struct ventana_board_info *info = &ventana_info;
1431         struct node_info nodes[] = {
1432                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1433                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1434         };
1435         const char *model = getenv("model");
1436
1437         if (getenv("fdt_noauto")) {
1438                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1439                 return;
1440         }
1441
1442         /* Update partition nodes using info from mtdparts env var */
1443         puts("   Updating MTD partitions...\n");
1444         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1445
1446         if (!model) {
1447                 puts("invalid board info: Leaving FDT fully enabled\n");
1448                 return;
1449         }
1450         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1451
1452         /* board serial number */
1453         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1454                     strlen(getenv("serial#")) + 1);
1455
1456         /* board (model contains model from device-tree) */
1457         fdt_setprop(blob, 0, "board", info->model,
1458                     strlen((const char *)info->model) + 1);
1459
1460         /*
1461          * Peripheral Config:
1462          *  remove nodes by alias path if EEPROM config tells us the
1463          *  peripheral is not loaded on the board.
1464          */
1465         for (bit = 0; bit < 64; bit++) {
1466                 if (!test_bit(bit, info->config))
1467                         fdt_del_node_and_alias(blob, fdt_aliases[bit]);
1468         }
1469 }
1470 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1471