2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/sys_proto.h>
18 #include <asm/imx-common/iomux-v3.h>
19 #include <asm/imx-common/mxc_i2c.h>
20 #include <asm/imx-common/boot_mode.h>
21 #include <asm/imx-common/sata.h>
22 #include <jffs2/load_kernel.h>
25 #include <linux/ctype.h>
26 #include <fdt_support.h>
27 #include <fsl_esdhc.h>
32 #include <power/pmic.h>
33 #include <power/ltc3676_pmic.h>
34 #include <power/pfuze100_pmic.h>
35 #include <fdt_support.h>
36 #include <jffs2/load_kernel.h>
37 #include <spi_flash.h>
40 #include "ventana_eeprom.h"
42 DECLARE_GLOBAL_DATA_PTR;
44 /* GPIO's common to all baseboards */
45 #define GP_PHY_RST IMX_GPIO_NR(1, 30)
46 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
47 #define GP_SD3_CD IMX_GPIO_NR(7, 0)
48 #define GP_RS232_EN IMX_GPIO_NR(2, 11)
49 #define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
55 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
56 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
57 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
59 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
60 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
61 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
63 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
64 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
65 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
67 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
68 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
69 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
71 #define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
72 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
73 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
75 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
76 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
77 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
80 * EEPROM board info struct populated by read_eeprom so that we only have to
83 static struct ventana_board_info ventana_info;
86 GW54proto, /* original GW5400-A prototype */
96 /* UART1: Function varies per baseboard */
97 iomux_v3_cfg_t const uart1_pads[] = {
98 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
99 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
102 /* UART2: Serial Console */
103 iomux_v3_cfg_t const uart2_pads[] = {
104 MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
105 MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
108 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
111 struct i2c_pads_info i2c_pad_info0 = {
113 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
114 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
115 .gp = IMX_GPIO_NR(3, 21)
118 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
119 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
120 .gp = IMX_GPIO_NR(3, 28)
124 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
125 struct i2c_pads_info i2c_pad_info1 = {
127 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
128 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
129 .gp = IMX_GPIO_NR(4, 12)
132 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
133 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
134 .gp = IMX_GPIO_NR(4, 13)
138 /* I2C3: Misc/Expansion */
139 struct i2c_pads_info i2c_pad_info2 = {
141 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
142 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
143 .gp = IMX_GPIO_NR(1, 3)
146 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
147 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
148 .gp = IMX_GPIO_NR(1, 6)
153 iomux_v3_cfg_t const usdhc3_pads[] = {
154 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
164 iomux_v3_cfg_t const enet_pads[] = {
165 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
166 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
167 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
168 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
169 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
170 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
171 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
172 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
173 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
174 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
175 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
176 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
177 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
178 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
179 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
181 MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
185 iomux_v3_cfg_t const nfc_pads[] = {
186 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
187 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
188 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
189 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
190 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
191 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
192 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
193 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
194 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
195 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
196 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
197 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
198 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
199 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
200 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
203 #ifdef CONFIG_CMD_NAND
204 static void setup_gpmi_nand(void)
206 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
208 /* config gpmi nand iomux */
209 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
211 /* config gpmi and bch clock to 100 MHz */
212 clrsetbits_le32(&mxc_ccm->cs2cdr,
213 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
214 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
215 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
216 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
217 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
218 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
220 /* enable gpmi and bch clock gating */
221 setbits_le32(&mxc_ccm->CCGR4,
222 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
223 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
224 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
225 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
226 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
228 /* enable apbh clock gating */
229 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
233 static void setup_iomux_enet(void)
235 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
237 /* toggle PHY_RST# */
238 gpio_direction_output(GP_PHY_RST, 0);
240 gpio_set_value(GP_PHY_RST, 1);
243 static void setup_iomux_uart(void)
245 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
246 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
249 #ifdef CONFIG_USB_EHCI_MX6
250 iomux_v3_cfg_t const usb_pads[] = {
251 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL),
252 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL),
253 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */
256 int board_ehci_hcd_init(int port)
258 struct ventana_board_info *info = &ventana_info;
260 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
262 /* Reset USB HUB (present on GW54xx/GW53xx) */
263 switch (info->model[3]) {
264 case '3': /* GW53xx */
265 imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09|
266 MUX_PAD_CTRL(NO_PAD_CTRL));
267 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
269 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
271 case '4': /* GW54xx */
272 imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 |
273 MUX_PAD_CTRL(NO_PAD_CTRL));
274 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
276 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
283 int board_ehci_power(int port, int on)
287 gpio_set_value(GP_USB_OTG_PWR, on);
290 #endif /* CONFIG_USB_EHCI_MX6 */
292 #ifdef CONFIG_FSL_ESDHC
293 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
295 int board_mmc_getcd(struct mmc *mmc)
298 gpio_direction_input(GP_SD3_CD);
299 return !gpio_get_value(GP_SD3_CD);
302 int board_mmc_init(bd_t *bis)
304 /* Only one USDHC controller on Ventana */
305 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
306 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
307 usdhc_cfg.max_bus_width = 4;
309 return fsl_esdhc_initialize(bis, &usdhc_cfg);
311 #endif /* CONFIG_FSL_ESDHC */
313 #ifdef CONFIG_MXC_SPI
314 iomux_v3_cfg_t const ecspi1_pads[] = {
316 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
317 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
318 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
319 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
322 static void setup_spi(void)
324 gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
325 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
326 ARRAY_SIZE(ecspi1_pads));
330 /* configure eth0 PHY board-specific LED behavior */
331 int board_phy_config(struct phy_device *phydev)
336 if (phydev->phy_id == 0x1410dd1) {
338 * Page 3, Register 16: LED[2:0] Function Control Register
339 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
340 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
342 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
343 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
346 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
347 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
350 if (phydev->drv->config)
351 phydev->drv->config(phydev);
356 int board_eth_init(bd_t *bis)
360 #ifdef CONFIG_FEC_MXC
365 /* For otg ethernet*/
366 usb_eth_initialize(bis);
372 /* read ventana EEPROM, check for validity, and return baseboard type */
380 struct ventana_board_info *info = &ventana_info;
381 unsigned char *buf = (unsigned char *)&ventana_info;
383 memset(info, 0, sizeof(ventana_info));
386 * On a board with a missing/depleted backup battery for GSC, the
387 * board may be ready to probe the GSC before its firmware is
388 * running. We will wait here indefinately for the GSC/EEPROM.
391 if (0 == i2c_set_bus_num(I2C_GSC) &&
392 0 == i2c_probe(GSC_EEPROM_ADDR))
397 /* read eeprom config section */
398 if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) {
399 puts("EEPROM: Failed to read EEPROM\n");
405 if (info->model[0] != 'G' || info->model[1] != 'W') {
406 puts("EEPROM: Invalid Model in EEPROM\n");
411 /* validate checksum */
412 for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
414 if ((info->chksum[0] != chksum>>8) ||
415 (info->chksum[1] != (chksum&0xff))) {
416 puts("EEPROM: Failed EEPROM checksum\n");
421 /* original GW5400-A prototype */
422 baseboard = info->model[3];
423 if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
427 case '0': /* original GW5400-A prototype */
443 printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
451 * Baseboard specific GPIO
454 /* common to add baseboards */
455 static iomux_v3_cfg_t const gw_gpio_pads[] = {
457 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
459 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
463 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
465 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
467 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
469 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
471 MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
473 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
475 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
477 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
479 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
481 MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
483 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
486 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
488 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
490 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
492 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
494 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
497 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
499 MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
501 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
504 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
506 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
508 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
510 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
512 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
515 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
517 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
519 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
521 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
523 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
526 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
528 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
530 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
532 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
534 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
537 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
539 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
541 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
543 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
546 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
548 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
550 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
552 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
554 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
556 MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
558 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
560 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
562 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
564 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
566 MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
568 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
572 * each baseboard has 4 user configurable Digital IO lines which can
573 * be pinmuxed as a GPIO or in some cases a PWM
576 iomux_v3_cfg_t gpio_padmux;
578 iomux_v3_cfg_t pwm_padmux;
584 iomux_v3_cfg_t const *gpio_pads;
587 struct dio_cfg dio_cfg[4];
588 /* various gpios (0 if non-existent) */
601 struct ventana gpio_cfg[] = {
604 .gpio_pads = gw54xx_gpio_pads,
605 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
607 { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
608 MX6_PAD_GPIO_9__PWM1_OUT, 1 },
609 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
610 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
611 { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
612 MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
613 { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
614 MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
621 .pcie_rst = IMX_GPIO_NR(1, 29),
622 .mezz_pwren = IMX_GPIO_NR(4, 7),
623 .mezz_irq = IMX_GPIO_NR(4, 9),
624 .rs485en = IMX_GPIO_NR(3, 24),
625 .dioi2c_en = IMX_GPIO_NR(4, 5),
626 .pcie_sson = IMX_GPIO_NR(1, 20),
631 .gpio_pads = gw51xx_gpio_pads,
632 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads),
634 { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
636 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
637 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
638 { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
639 MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
640 { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18),
641 MX6_PAD_SD1_CMD__PWM4_OUT, 4 },
647 .pcie_rst = IMX_GPIO_NR(1, 0),
648 .mezz_pwren = IMX_GPIO_NR(2, 19),
649 .mezz_irq = IMX_GPIO_NR(2, 18),
650 .gps_shdn = IMX_GPIO_NR(1, 2),
651 .vidin_en = IMX_GPIO_NR(5, 20),
656 .gpio_pads = gw52xx_gpio_pads,
657 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads),
659 { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
661 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
662 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
663 { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
664 MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
665 { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
673 .pcie_rst = IMX_GPIO_NR(1, 29),
674 .mezz_pwren = IMX_GPIO_NR(2, 19),
675 .mezz_irq = IMX_GPIO_NR(2, 18),
676 .gps_shdn = IMX_GPIO_NR(1, 27),
677 .vidin_en = IMX_GPIO_NR(3, 31),
678 .usb_sel = IMX_GPIO_NR(1, 2),
683 .gpio_pads = gw53xx_gpio_pads,
684 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads),
686 { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
688 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
689 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
690 { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
691 MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
692 { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
700 .pcie_rst = IMX_GPIO_NR(1, 29),
701 .mezz_pwren = IMX_GPIO_NR(2, 19),
702 .mezz_irq = IMX_GPIO_NR(2, 18),
703 .gps_shdn = IMX_GPIO_NR(1, 27),
704 .vidin_en = IMX_GPIO_NR(3, 31),
709 .gpio_pads = gw54xx_gpio_pads,
710 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
712 { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
713 MX6_PAD_GPIO_9__PWM1_OUT, 1 },
714 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
715 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
716 { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
717 MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
718 { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
719 MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
726 .pcie_rst = IMX_GPIO_NR(1, 29),
727 .mezz_pwren = IMX_GPIO_NR(2, 19),
728 .mezz_irq = IMX_GPIO_NR(2, 18),
729 .rs485en = IMX_GPIO_NR(7, 1),
730 .vidin_en = IMX_GPIO_NR(3, 31),
731 .dioi2c_en = IMX_GPIO_NR(4, 5),
732 .pcie_sson = IMX_GPIO_NR(1, 20),
736 /* setup board specific PMIC */
737 int power_init_board(void)
742 /* configure PFUZE100 PMIC */
743 if (board_type == GW54xx || board_type == GW54proto) {
744 power_pfuze100_init(I2C_PMIC);
745 p = pmic_get("PFUZE100_PMIC");
746 if (p && !pmic_probe(p)) {
747 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
748 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
750 /* Set VGEN1 to 1.5V and enable */
751 pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
752 reg &= ~(LDO_VOL_MASK);
753 reg |= (LDOA_1_50V | LDO_EN);
754 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
756 /* Set SWBST to 5.0V and enable */
757 pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
758 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
759 reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
760 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
764 /* configure LTC3676 PMIC */
766 power_ltc3676_init(I2C_PMIC);
767 p = pmic_get("LTC3676_PMIC");
768 if (p && !pmic_probe(p)) {
769 puts("PMIC: LTC3676\n");
770 /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
771 if (is_cpu_type(MXC_CPU_MX6Q)) {
772 /* mask PGOOD during SW1 transition */
773 reg = 0x1d | LTC3676_PGOOD_MASK;
774 pmic_reg_write(p, LTC3676_DVB1B, reg);
775 /* set SW1 (VDD_SOC) to 1259mV */
777 pmic_reg_write(p, LTC3676_DVB1A, reg);
779 /* mask PGOOD during SW3 transition */
780 reg = 0x1d | LTC3676_PGOOD_MASK;
781 pmic_reg_write(p, LTC3676_DVB3B, reg);
782 /*set SW3 (VDD_ARM) to 1259mV */
784 pmic_reg_write(p, LTC3676_DVB3A, reg);
792 /* setup GPIO pinmux and default configuration per baseboard */
793 static void setup_board_gpio(int board)
795 struct ventana_board_info *info = &ventana_info;
800 int quiet = simple_strtol(getenv("quiet"), NULL, 10);
802 if (board >= GW_UNKNOWN)
806 gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
809 if (is_cpu_type(MXC_CPU_MX6Q) &&
810 test_bit(EECONFIG_SATA, info->config)) {
811 gpio_direction_output(GP_MSATA_SEL,
812 (hwconfig("msata")) ? 1 : 0);
814 gpio_direction_output(GP_MSATA_SEL, 0);
818 * assert PCI_RST# (released by OS when clock is valid)
819 * TODO: figure out why leaving this de-asserted from PCI scan on boot
820 * causes linux pcie driver to hang during enumeration
822 gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
824 /* turn off (active-high) user LED's */
825 for (i = 0; i < 4; i++) {
826 if (gpio_cfg[board].leds[i])
827 gpio_direction_output(gpio_cfg[board].leds[i], 1);
830 /* Expansion Mezzanine IO */
831 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
832 gpio_direction_input(gpio_cfg[board].mezz_irq);
834 /* RS485 Transmit Enable */
835 if (gpio_cfg[board].rs485en)
836 gpio_direction_output(gpio_cfg[board].rs485en, 0);
839 if (gpio_cfg[board].gps_shdn)
840 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
842 /* Analog video codec power enable */
843 if (gpio_cfg[board].vidin_en)
844 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
847 if (gpio_cfg[board].dioi2c_en)
848 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
850 /* PCICK_SSON: disable spread-spectrum clock */
851 if (gpio_cfg[board].pcie_sson)
852 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
854 /* USBOTG Select (PCISKT or FrontPanel) */
855 if (gpio_cfg[board].usb_sel)
856 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
859 * Configure DIO pinmux/padctl registers
860 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
862 for (i = 0; i < 4; i++) {
863 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
864 unsigned ctrl = DIO_PAD_CTRL;
866 sprintf(arg, "dio%d", i);
869 s = hwconfig_subarg(arg, "padctrl", &len);
871 ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
872 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
874 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
875 (cfg->gpio_param/32)+1,
879 imx_iomux_v3_setup_pad(cfg->gpio_padmux |
881 gpio_direction_input(cfg->gpio_param);
882 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
885 printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
886 imx_iomux_v3_setup_pad(cfg->pwm_padmux |
892 if (is_cpu_type(MXC_CPU_MX6Q) &&
893 (test_bit(EECONFIG_SATA, info->config))) {
894 printf("MSATA: %s\n", (hwconfig("msata") ?
895 "enabled" : "disabled"));
897 printf("RS232: %s\n", (hwconfig("rs232")) ?
898 "enabled" : "disabled");
902 #if defined(CONFIG_CMD_PCI)
903 int imx6_pcie_toggle_reset(void)
905 if (board_type < GW_UNKNOWN) {
906 gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0);
908 gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1);
912 #endif /* CONFIG_CMD_PCI */
914 #ifdef CONFIG_SERIAL_TAG
916 * called when setting up ATAGS before booting kernel
917 * populate serialnum from the following (in order of priority):
921 void get_board_serial(struct tag_serialnr *serialnr)
923 char *serial = getenv("serial#");
927 serialnr->low = simple_strtoul(serial, NULL, 10);
928 } else if (ventana_info.model[0]) {
930 serialnr->low = ventana_info.serial;
942 int board_early_init_f(void)
945 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
952 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
953 CONFIG_DDR_MB*1024*1024);
960 struct iomuxc_base_regs *const iomuxc_regs
961 = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
963 clrsetbits_le32(&iomuxc_regs->gpr[1],
964 IOMUXC_GPR1_OTG_ID_MASK,
965 IOMUXC_GPR1_OTG_ID_GPIO1);
967 /* address of linux boot parameters */
968 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
970 #ifdef CONFIG_CMD_NAND
973 #ifdef CONFIG_MXC_SPI
976 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
977 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
978 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
980 #ifdef CONFIG_CMD_SATA
983 /* read Gateworks EEPROM into global struct (used later) */
984 board_type = read_eeprom();
986 /* board-specifc GPIO iomux */
987 if (board_type < GW_UNKNOWN) {
988 imx_iomux_v3_setup_multiple_pads(gw_gpio_pads,
989 ARRAY_SIZE(gw_gpio_pads));
990 imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads,
991 gpio_cfg[board_type].num_pads);
997 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
999 * called during late init (after relocation and after board_init())
1000 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1003 int checkboard(void)
1005 struct ventana_board_info *info = &ventana_info;
1006 unsigned char buf[4];
1008 int quiet; /* Quiet or minimal output mode */
1011 p = getenv("quiet");
1013 quiet = simple_strtol(p, NULL, 10);
1015 setenv("quiet", "0");
1017 puts("\nGateworks Corporation Copyright 2014\n");
1018 if (info->model[0]) {
1019 printf("Model: %s\n", info->model);
1020 printf("MFGDate: %02x-%02x-%02x%02x\n",
1021 info->mfgdate[0], info->mfgdate[1],
1022 info->mfgdate[2], info->mfgdate[3]);
1023 printf("Serial:%d\n", info->serial);
1025 puts("Invalid EEPROM - board will not function fully\n");
1030 /* Display GSC firmware revision/CRC/status */
1031 i2c_set_bus_num(I2C_GSC);
1032 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1033 printf("GSC: v%d", buf[0]);
1034 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1035 printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1036 printf(" 0x%02x", buf[0]); /* irq status */
1041 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1043 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1050 #ifdef CONFIG_CMD_BMODE
1052 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1053 * see Table 8-11 and Table 5-9
1054 * BOOT_CFG1[7] = 1 (boot from NAND)
1055 * BOOT_CFG1[5] = 0 - raw NAND
1056 * BOOT_CFG1[4] = 0 - default pad settings
1057 * BOOT_CFG1[3:2] = 00 - devices = 1
1058 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1059 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1060 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1061 * BOOT_CFG2[0] = 0 - Reset time 12ms
1063 static const struct boot_mode board_boot_modes[] = {
1064 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1065 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1071 int misc_init_r(void)
1073 struct ventana_board_info *info = &ventana_info;
1076 /* set env vars based on EEPROM data */
1077 if (ventana_info.model[0]) {
1078 char str[16], fdt[36];
1080 const char *cputype = "";
1084 * FDT name will be prefixed with CPU type. Three versions
1085 * will be created each increasingly generic and bootloader
1086 * env scripts will try loading each from most specific to
1089 if (is_cpu_type(MXC_CPU_MX6Q))
1091 else if (is_cpu_type(MXC_CPU_MX6DL))
1093 memset(str, 0, sizeof(str));
1094 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1095 str[i] = tolower(info->model[i]);
1096 if (!getenv("model"))
1097 setenv("model", str);
1098 if (!getenv("fdt_file")) {
1099 sprintf(fdt, "%s-%s.dtb", cputype, str);
1100 setenv("fdt_file", fdt);
1102 p = strchr(str, '-');
1106 setenv("model_base", str);
1107 if (!getenv("fdt_file1")) {
1108 sprintf(fdt, "%s-%s.dtb", cputype, str);
1109 setenv("fdt_file1", fdt);
1114 if (!getenv("fdt_file2")) {
1115 sprintf(fdt, "%s-%s.dtb", cputype, str);
1116 setenv("fdt_file2", fdt);
1120 /* initialize env from EEPROM */
1121 if (test_bit(EECONFIG_ETH0, info->config) &&
1122 !getenv("ethaddr")) {
1123 eth_setenv_enetaddr("ethaddr", info->mac0);
1125 if (test_bit(EECONFIG_ETH1, info->config) &&
1126 !getenv("eth1addr")) {
1127 eth_setenv_enetaddr("eth1addr", info->mac1);
1130 /* board serial-number */
1131 sprintf(str, "%6d", info->serial);
1132 setenv("serial#", str);
1136 /* setup baseboard specific GPIO pinmux and config */
1137 setup_board_gpio(board_type);
1139 #ifdef CONFIG_CMD_BMODE
1140 add_board_boot_modes(board_boot_modes);
1144 * The Gateworks System Controller implements a boot
1145 * watchdog (always enabled) as a workaround for IMX6 boot related
1147 * ERR005768 - no fix
1148 * ERR006282 - fixed in silicon r1.3
1149 * ERR007117 - fixed in silicon r1.3
1150 * ERR007220 - fixed in silicon r1.3
1151 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1153 * Disable the boot watchdog and display/clear the timeout flag if set
1155 i2c_set_bus_num(I2C_GSC);
1156 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
1157 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1158 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
1159 puts("Error: could not disable GSC Watchdog\n");
1161 puts("Error: could not disable GSC Watchdog\n");
1163 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) {
1164 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1165 puts("GSC boot watchdog timeout detected");
1166 reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1167 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1);
1174 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1176 /* FDT aliases associated with EEPROM config bits */
1177 const char *fdt_aliases[] = {
1245 * called prior to booting kernel or by 'fdt boardsetup' command
1247 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1248 * - mtd partitions based on mtdparts/mtdids env
1249 * - system-serial (board serial num from EEPROM)
1250 * - board (full model from EEPROM)
1251 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1253 void ft_board_setup(void *blob, bd_t *bd)
1256 struct ventana_board_info *info = &ventana_info;
1257 struct node_info nodes[] = {
1258 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1259 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1261 const char *model = getenv("model");
1263 if (getenv("fdt_noauto")) {
1264 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1268 /* Update partition nodes using info from mtdparts env var */
1269 puts(" Updating MTD partitions...\n");
1270 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1273 puts("invalid board info: Leaving FDT fully enabled\n");
1276 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1278 /* board serial number */
1279 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1280 strlen(getenv("serial#")) + 1);
1282 /* board (model contains model from device-tree) */
1283 fdt_setprop(blob, 0, "board", info->model,
1284 strlen((const char *)info->model) + 1);
1287 * Peripheral Config:
1288 * remove nodes by alias path if EEPROM config tells us the
1289 * peripheral is not loaded on the board.
1291 for (bit = 0; bit < 64; bit++) {
1292 if (!test_bit(bit, info->config))
1293 fdt_del_node_and_alias(blob, fdt_aliases[bit]);
1296 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */