3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
16 #include <gdsys_fpga.h>
18 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
19 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
20 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
41 char *s = getenv("serial#");
43 puts("Board: CATCenter Neo");
55 static void print_fpga_info(void)
57 struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
58 u16 versions = in_le16(&fpga->versions);
59 u16 fpga_version = in_le16(&fpga->fpga_version);
60 u16 fpga_features = in_le16(&fpga->fpga_features);
61 int fpga_state = get_fpga_state(0);
63 unsigned hardware_version;
64 unsigned feature_channels;
67 if (fpga_state & FPGA_STATE_DONE_FAILED) {
68 printf(" done timed out\n");
72 if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
73 printf(" refelectione test failed\n");
77 unit_type = (versions & 0xf000) >> 12;
78 hardware_version = versions & 0x000f;
79 feature_channels = fpga_features & 0x007f;
87 printf("UnitType %d(not supported)", unit_type);
91 switch (hardware_version) {
93 printf(" HW-Ver 3.00-3.12\n");
97 printf(" HW-Ver %d(not supported)\n",
102 printf(" FPGA V %d.%02d, features:",
103 fpga_version / 100, fpga_version % 100);
105 printf(" %d channel(s)\n", feature_channels);
108 int last_stage_init(void)
115 void gd405ep_init(void)
119 void gd405ep_set_fpga_reset(unsigned state)
122 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
123 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
125 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
126 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
130 void gd405ep_setup_hw(void)
133 * set "startup-finished"-gpios
135 gpio_write_bit(21, 0);
136 gpio_write_bit(22, 1);
139 int gd405ep_get_fpga_done(unsigned fpga)
142 * Neo hardware has no FPGA-DONE GPIO