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1 /*
2  * ICP DAS LP-8x4x Support
3  *
4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5  * adapted from Voipac PXA270 Support by
6  * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #include <common.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/regs-mmc.h>
14 #include <asm/arch/pxa.h>
15 #include <netdev.h>
16 #include <serial.h>
17 #include <asm/io.h>
18 #include <usb.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 /*
23  * Miscelaneous platform dependent initialisations
24  */
25 int board_init(void)
26 {
27         /* We have RAM, disable cache */
28         dcache_disable();
29         icache_disable();
30
31         /* memory and cpu-speed are setup before relocation */
32         /* so we do _nothing_ here */
33
34         /* adress of boot parameters */
35         gd->bd->bi_boot_params = 0xa0000100;
36
37         return 0;
38 }
39
40 int dram_init(void)
41 {
42         pxa2xx_dram_init();
43         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
44         return 0;
45 }
46
47 void dram_init_banksize(void)
48 {
49         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
50         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
51 }
52
53 #ifdef  CONFIG_CMD_MMC
54 int board_mmc_init(bd_t *bis)
55 {
56         pxa_mmc_register(0);
57         return 0;
58 }
59 #endif
60
61 #ifdef  CONFIG_CMD_USB
62 int board_usb_init(int index, enum usb_init_type init)
63 {
64         if (index !=0 || init != USB_INIT_HOST)
65                 return -1;
66
67         writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
68
69         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
70         udelay(11);
71         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
72
73         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
74
75         while (readl(UHCHR) & UHCHR_FSBIR)
76                 continue; /* required by checkpath.pl */
77
78         writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
79         writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA);
80         writel(readl(UHCRHDA) | 0x800, UHCRHDA);
81
82         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
83         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
84
85         /* Clear any OTG Pin Hold */
86         if (readl(PSSR) & PSSR_OTGPH)
87                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
88
89         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
90         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
91
92         /* Set port power control mask bits, only 3 ports. */
93         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
94
95         return 0;
96 }
97
98 int usb_board_stop(void)
99 {
100         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
101         udelay(11);
102         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
103
104         writel(readl(UHCCOMS) | 1, UHCCOMS);
105         udelay(10);
106
107         writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR);
108
109         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
110
111         return 0;
112 }
113
114 int board_usb_cleanup(int index, enum usb_init_type init)
115 {
116         if (index !=0 || init != USB_INIT_HOST)
117                 return -1;
118
119         return usb_board_stop();
120 }
121 #endif
122
123 #ifdef CONFIG_DRIVER_DM9000
124 void lp8x4x_eth1_mac_init(void)
125 {
126         u8 eth1addr[8];
127         int i;
128         u8 reg;
129
130         eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
131         if (!is_valid_ether_addr(eth1addr))
132                 return;
133
134         for (i = 0, reg = 0x10; i < 6; i++, reg++) {
135                 writeb(reg, (u8 *)(DM9000_IO_2));
136                 writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
137         }
138 }
139
140 int board_eth_init(bd_t *bis)
141 {
142         lp8x4x_eth1_mac_init();
143         return dm9000_initialize(bis);
144 }
145 #endif