board/karo/tx48/flash.h

   1 /*
   2  * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 /* timing parameters for Samsung K9F1G08U0D */
  15 #define tCS_NAND                20
  16 #define tCH_NAND                5
  17 #define tCEA_NAND               25
  18 #define tREA_NAND               20
  19 #define tWP_NAND                15
  20 #define tRP_NAND                15
  21 #define tWC_NAND                30
  22 #define tRC_NAND                30
  23 #define tALS_NAND               15
  24 #define tADL_NAND               100
  25 #define tRHW_NAND               100
  26
  27 /* Values for GPMC_CONFIG1 - signal control parameters */
  28 #define WRAPBURST                       (1 << 31)
  29 #define READMULTIPLE                    (1 << 30)
  30 #define READTYPE                        (1 << 29)
  31 #define WRITEMULTIPLE                   (1 << 28)
  32 #define WRITETYPE                       (1 << 27)
  33 #define CLKACTIVATIONTIME(x)            (((x) & 3) << 25)
  34 #define ATTACHEDDEVICEPAGELENGTH(x)     (((x) & 3) << 23)
  35 #define WAITREADMONITORING              (1 << 22)
  36 #define WAITWRITEMONITORING             (1 << 21)
  37 #define WAITMONITORINGTIME(x)           (((x) & 3) << 18)
  38 #define WAITPINSELECT(x)                (((x) & 3) << 16)
  39 #define DEVICESIZE(x)                   (((x) & 3) << 12)
  40 #define DEVICESIZE_8BIT                 DEVICESIZE(0)
  41 #define DEVICESIZE_16BIT                DEVICESIZE(1)
  42 #define DEVICETYPE(x)                   (((x) & 3) << 10)
  43 #define DEVICETYPE_NOR                  DEVICETYPE(0)
  44 #define DEVICETYPE_NAND                 DEVICETYPE(2)
  45 #define MUXADDDATA(n)                   ((n) << 8)
  46 #define TIMEPARAGRANULARITY             (1 << 4)
  47 #define GPMCFCLKDIVIDER(x)              (((x) & 3) << 0)
  48
  49 /* Values for GPMC_CONFIG2 - CS timing */
  50 #define CSWROFFTIME(x)                  (((x) & 0x1f) << 16)
  51 #define CSRDOFFTIME(x)                  (((x) & 0x1f) <<  8)
  52 #define CSEXTRADELAY                    (1 << 7)
  53 #define CSONTIME(x)                     (((x) &  0xf) <<  0)
  54
  55 /* Values for GPMC_CONFIG3 - nADV timing */
  56 #define ADVWROFFTIME(x)                 (((x) & 0x1f) << 16)
  57 #define ADVRDOFFTIME(x)                 (((x) & 0x1f) <<  8)
  58 #define ADVEXTRADELAY                   (1 << 7)
  59 #define ADVONTIME(x)                    (((x) &  0xf) <<  0)
  60
  61 /* Values for GPMC_CONFIG4 - nWE and nOE timing */
  62 #define WEOFFTIME(x)                    (((x) & 0x1f) << 24)
  63 #define WEEXTRADELAY                    (1 << 23)
  64 #define WEONTIME(x)                     (((x) &  0xf) << 16)
  65 #define OEOFFTIME(x)                    (((x) & 0x1f) <<  8)
  66 #define OEEXTRADELAY                    (1 << 7)
  67 #define OEONTIME(x)                     (((x) &  0xf) <<  0)
  68
  69 /* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */
  70 #define PAGEBURSTACCESSTIME(x)          (((x) &  0xf) << 24)
  71 #define RDACCESSTIME(x)                 (((x) & 0x1f) << 16)
  72 #define WRCYCLETIME(x)                  (((x) & 0x1f) <<  8)
  73 #define RDCYCLETIME(x)                  (((x) & 0x1f) <<  0)
  74
  75 /* Values for GPMC_CONFIG6 - misc timings */
  76 #define WRACCESSTIME(x)                 (((x) & 0x1f) << 24)
  77 #define WRDATAONADMUXBUS(x)             (((x) & 0xf) << 16)
  78 #define CYCLE2CYCLEDELAY(x)             (((x) & 0xf) << 8)
  79 #define CYCLE2CYCLESAMECSEN             (1 << 7)
  80 #define CYCLE2CYCLEDIFFCSEN             (1 << 6)
  81 #define BUSTURNAROUND(x)                (((x) & 0xf) << 0)
  82
  83 /* Values for GPMC_CONFIG7 - CS address mapping configuration */
  84 #define MASKADDRESS(x)                  (((x) & 0xf) << 8)
  85 #define CSVALID                         (1 << 6)
  86 #define BASEADDRESS(x)                  (((x) & 0x3f) << 0)
  87
  88 #define GPMC_CLK                100
  89 #define NS_TO_CK(ns)            DIV_ROUND_UP((ns) * GPMC_CLK, 1000)
  90
  91 #define _CSWOFF                 NS_TO_CK(tCS_NAND + tCH_NAND)
  92 #define _CSROFF                 NS_TO_CK(tCEA_NAND + tRP_NAND - tREA_NAND)
  93
  94 #define _ADWOFF                 NS_TO_CK(0)     /* ? */
  95 #define _ADROFF                 NS_TO_CK(0)     /* ? */
  96 #define _ADON                   NS_TO_CK(0)     /* ? */
  97
  98 #define _WEOFF                  NS_TO_CK(tCS_NAND)
  99 #define _WEON                   NS_TO_CK(tCS_NAND - tWP_NAND)
 100
 101 #define _OEOFF                  NS_TO_CK(tCS_NAND + tCH_NAND)
 102 #define _OEON                   NS_TO_CK(tCEA_NAND - tREA_NAND)
 103
 104 #define _RDACC                  NS_TO_CK(tCEA_NAND)
 105 #define _WRCYC                  NS_TO_CK(tWC_NAND)
 106 #define _RDCYC                  NS_TO_CK(tRC_NAND)
 107
 108 #define _WRACC                  NS_TO_CK(tALS_NAND)
 109 #define _WBURST                 NS_TO_CK(0)
 110 #define _CSHIGH                 NS_TO_CK(tADL_NAND)
 111 #define _BTURN                  NS_TO_CK(tRHW_NAND)
 112
 113 #define TX48_NAND_GPMC_CONFIG1  (GPMCFCLKDIVIDER(0) |           \
 114                                 (0 << 4) /* TIMEPARAGRANULARITY */ | \
 115                                 MUXADDDATA(0) |                 \
 116                                 DEVICETYPE_NAND |               \
 117                                 DEVICESIZE_8BIT |               \
 118                                 WAITPINSELECT(0) |              \
 119                                 WAITMONITORINGTIME(0) |         \
 120                                 (0 << 21) /* WAITWRITEMONITORING */ | \
 121                                 (0 << 22) /* WAITREADMONITORING */ | \
 122                                 ATTACHEDDEVICEPAGELENGTH(0) |   \
 123                                 CLKACTIVATIONTIME(0) |          \
 124                                 (0 << 27) /* WRITETYPE */ |     \
 125                                 (0 << 28) /* WRITEMULTIPLE */ | \
 126                                 (0 << 29) /* READTYPE */ |      \
 127                                 (0 << 30) /* READMULTIPLE */ |  \
 128                                 (0 << 31) /* WRAPBURST */)
 129 /* CONFIG2: Chip Select */
 130 #define TX48_NAND_GPMC_CONFIG2  (CSWROFFTIME(_CSWOFF) |         \
 131                                 CSRDOFFTIME(_CSROFF) |          \
 132                                 CSONTIME(0) |                   \
 133                                 (0 << 7) /* CSEXTRADELAY */)
 134 /* CONFIG3: ADV/ALE */
 135 #define TX48_NAND_GPMC_CONFIG3  (ADVWROFFTIME(_ADWOFF) |        \
 136                                 ADVRDOFFTIME(_ADROFF) |         \
 137                                 (0 << 7) /* ADVEXTRADELAY */ |  \
 138                                 ADVONTIME(_ADON))
 139 /* CONFIG4: WE/OE */
 140 #define TX48_NAND_GPMC_CONFIG4  (WEOFFTIME(_WEOFF) |            \
 141                                 (0 << 23) /* WEEXTRADELAY */ |  \
 142                                 WEONTIME(_WEON) |               \
 143                                 OEOFFTIME(_OEOFF) |             \
 144                                 (0 << 7) /* OEEXTRADELAY */ |   \
 145                                 OEONTIME(_OEON))
 146 /* CONFIG5: Cycle Timing */
 147 #define TX48_NAND_GPMC_CONFIG5  (PAGEBURSTACCESSTIME(0) |       \
 148                                 RDACCESSTIME(_RDACC) |          \
 149                                 WRCYCLETIME(_WRCYC) |           \
 150                                 RDCYCLETIME(_RDCYC))
 151 /* CONFIG6: Rest of the Pack */
 152 #define TX48_NAND_GPMC_CONFIG6  (WRACCESSTIME(_WRACC) |         \
 153                                 WRDATAONADMUXBUS(_WBURST) |     \
 154                                 CYCLE2CYCLEDELAY(_CSHIGH) |     \
 155                                 CYCLE2CYCLESAMECSEN |           \
 156                                 (0 << 6) /* CYCLE2CYCLEDIFFCSEN */ | \
 157                                 BUSTURNAROUND(_BTURN))