board/karo/tx51/tx51.c

   1 /*
   2  * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <common.h>
  21 #include <errno.h>
  22 #include <libfdt.h>
  23 #include <fdt_support.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <video_fb.h>
  29 #include <ipu.h>
  30 #include <mxcfb.h>
  31 #include <linux/fb.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/iomux-mx51.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/arch/imx-regs.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <asm/arch/sys_proto.h>
  39
  40 #include "../common/karo.h"
  41
  42 #define TX51_FEC_RST_GPIO       IMX_GPIO_NR(2, 14)
  43 #define TX51_FEC_PWR_GPIO       IMX_GPIO_NR(1, 3)
  44 #define TX51_FEC_INT_GPIO       IMX_GPIO_NR(3, 18)
  45 #define TX51_LED_GPIO           IMX_GPIO_NR(4, 10)
  46
  47 #define TX51_LCD_PWR_GPIO       IMX_GPIO_NR(4, 14)
  48 #define TX51_LCD_RST_GPIO       IMX_GPIO_NR(4, 13)
  49 #define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
  50
  51 #define TX51_RESET_OUT_GPIO     IMX_GPIO_NR(2, 15)
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define IOMUX_SION              IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  56
  57 #define FEC_PAD_CTRL            MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
  58                                         PAD_CTL_SRE_FAST)
  59 #define FEC_PAD_CTRL2           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_SRE_FAST)
  60 #define GPIO_PAD_CTRL           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP)
  61
  62 static iomux_v3_cfg_t tx51_pads[] = {
  63         /* NAND flash pads are set up in lowlevel_init.S */
  64
  65         /* RESET_OUT */
  66         MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
  67
  68         /* UART pads */
  69 #if CONFIG_MXC_UART_BASE == UART1_BASE
  70         MX51_PAD_UART1_RXD__UART1_RXD,
  71         MX51_PAD_UART1_TXD__UART1_TXD,
  72         MX51_PAD_UART1_RTS__UART1_RTS,
  73         MX51_PAD_UART1_CTS__UART1_CTS,
  74 #endif
  75 #if CONFIG_MXC_UART_BASE == UART2_BASE
  76         MX51_PAD_UART2_RXD__UART2_RXD,
  77         MX51_PAD_UART2_TXD__UART2_TXD,
  78         MX51_PAD_EIM_D26__UART2_RTS,
  79         MX51_PAD_EIM_D25__UART2_CTS,
  80 #endif
  81 #if CONFIG_MXC_UART_BASE == UART3_BASE
  82         MX51_PAD_UART3_RXD__UART3_RXD,
  83         MX51_PAD_UART3_TXD__UART3_TXD,
  84         MX51_PAD_EIM_D18__UART3_RTS,
  85         MX51_PAD_EIM_D17__UART3_CTS,
  86 #endif
  87         /* internal I2C */
  88         MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
  89         MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
  90
  91         /* FEC PHY GPIO functions */
  92         MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL,    /* PHY POWER */
  93         MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL,   /* PHY RESET */
  94         MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
  95
  96         /* FEC functions */
  97         MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
  98         MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
  99         MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
 100         MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
 101         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
 102         MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
 103         MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
 104         MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
 105         MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
 106         MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
 107
 108         /* strap pins for PHY configuration */
 109         MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
 110         MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL,  /* RXD0/Mode0 */
 111         MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL,   /* RXD1/Mode1 */
 112         MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL,   /* RXD2/Mode2 */
 113         MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL,   /* RXD3/nINTSEL */
 114         MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
 115         MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL,   /* CRS/PHYAD4 */
 116
 117         /* unusable pins on TX51 */
 118         MX51_PAD_GPIO1_0__GPIO1_0,
 119         MX51_PAD_GPIO1_1__GPIO1_1,
 120 };
 121
 122 static const struct gpio tx51_gpios[] = {
 123         /* RESET_OUT */
 124         { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
 125
 126         /* FEC PHY control GPIOs */
 127         { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
 128         { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
 129         { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },         /* PHY INT (TX_ER) */
 130
 131         /* FEC PHY strap pins */
 132         { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", },  /* RX_CLK/REGOFF */
 133         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", },   /* RXD0/Mode0 */
 134         { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", },   /* RXD1/Mode1 */
 135         { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", },   /* RXD2/Mode2 */
 136         { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
 137         { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", },    /* COL/RMII/CRSDV */
 138         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", },  /* CRS/PHYAD4 */
 139
 140         /* module internal I2C bus */
 141         { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
 142         { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
 143
 144         /* Unconnected pins */
 145         { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
 146         { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
 147 };
 148
 149 /*
 150  * Functions
 151  */
 152 /* placed in section '.data' to prevent overwriting relocation info
 153  * overlayed with bss
 154  */
 155 static u32 wrsr __attribute__((section(".data")));
 156
 157 #define WRSR_POR        (1 << 4)
 158 #define WRSR_TOUT       (1 << 1)
 159 #define WRSR_SFTW       (1 << 0)
 160
 161 static void print_reset_cause(void)
 162 {
 163         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 164         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 165         u32 srsr;
 166         char *dlm = "";
 167
 168         printf("Reset cause: ");
 169
 170         srsr = readl(&src_regs->srsr);
 171         wrsr = readw(wdt_base + 4);
 172
 173         if (wrsr & WRSR_POR) {
 174                 printf("%sPOR", dlm);
 175                 dlm = " | ";
 176         }
 177         if (srsr & 0x00004) {
 178                 printf("%sCSU", dlm);
 179                 dlm = " | ";
 180         }
 181         if (srsr & 0x00008) {
 182                 printf("%sIPP USER", dlm);
 183                 dlm = " | ";
 184         }
 185         if (srsr & 0x00010) {
 186                 if (wrsr & WRSR_SFTW) {
 187                         printf("%sSOFT", dlm);
 188                         dlm = " | ";
 189                 }
 190                 if (wrsr & WRSR_TOUT) {
 191                         printf("%sWDOG", dlm);
 192                         dlm = " | ";
 193                 }
 194         }
 195         if (srsr & 0x00020) {
 196                 printf("%sJTAG HIGH-Z", dlm);
 197                 dlm = " | ";
 198         }
 199         if (srsr & 0x00040) {
 200                 printf("%sJTAG SW", dlm);
 201                 dlm = " | ";
 202         }
 203         if (srsr & 0x10000) {
 204                 printf("%sWARM BOOT", dlm);
 205                 dlm = " | ";
 206         }
 207         if (dlm[0] == '\0')
 208                 printf("unknown");
 209
 210         printf("\n");
 211 }
 212
 213 static void tx51_print_cpuinfo(void)
 214 {
 215         u32 cpurev;
 216
 217         cpurev = get_cpu_rev();
 218
 219         printf("CPU:   Freescale i.MX51 rev%d.%d at %d MHz\n",
 220                 (cpurev & 0x000F0) >> 4,
 221                 (cpurev & 0x0000F) >> 0,
 222                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 223
 224         print_reset_cause();
 225 }
 226
 227 int board_early_init_f(void)
 228 {
 229         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 230
 231         gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
 232         imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
 233
 234         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 235         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 236
 237         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 238         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 239         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 240         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 241         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 242
 243         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 244         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 245
 246         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 247         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 248         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 249         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 250         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 251
 252         writel(0xffcffffc, &ccm_regs->CCGR0);
 253         writel(0x003fffff, &ccm_regs->CCGR1);
 254         writel(0x030c003c, &ccm_regs->CCGR2);
 255         writel(0x000000ff, &ccm_regs->CCGR3);
 256         writel(0x00000000, &ccm_regs->CCGR4);
 257         writel(0x003fc003, &ccm_regs->CCGR5);
 258         writel(0x00000000, &ccm_regs->CCGR6);
 259         writel(0x00000000, &ccm_regs->cmeor);
 260 #ifdef CONFIG_CMD_BOOTCE
 261         /* WinCE fails to enable these clocks */
 262         writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
 263         writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
 264         writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
 265 #endif
 266         return 0;
 267 }
 268
 269 int board_init(void)
 270 {
 271         /* Address of boot parameters */
 272         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 273         return 0;
 274 }
 275
 276 int dram_init(void)
 277 {
 278         int ret;
 279
 280         /* dram_init must store complete ramsize in gd->ram_size */
 281         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 282                                 PHYS_SDRAM_1_SIZE);
 283
 284         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 285                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 286         if (ret)
 287                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 288                         CONFIG_SYS_SDRAM_CLK, ret);
 289         else
 290                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 291                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 292                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 293                         CONFIG_SYS_SDRAM_CLK);
 294         return ret;
 295 }
 296
 297 void dram_init_banksize(void)
 298 {
 299         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 300         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 301                         PHYS_SDRAM_1_SIZE);
 302 #if CONFIG_NR_DRAM_BANKS > 1
 303         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 304         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 305                         PHYS_SDRAM_2_SIZE);
 306 #endif
 307 }
 308
 309 #ifdef  CONFIG_CMD_MMC
 310 static const iomux_v3_cfg_t mmc0_pads[] = {
 311         MX51_PAD_SD1_CMD__SD1_CMD,
 312         MX51_PAD_SD1_CLK__SD1_CLK,
 313         MX51_PAD_SD1_DATA0__SD1_DATA0,
 314         MX51_PAD_SD1_DATA1__SD1_DATA1,
 315         MX51_PAD_SD1_DATA2__SD1_DATA2,
 316         MX51_PAD_SD1_DATA3__SD1_DATA3,
 317         /* SD1 CD */
 318         MX51_PAD_DISPB2_SER_RS__GPIO3_8 | GPIO_PAD_CTRL,
 319 };
 320
 321 static const iomux_v3_cfg_t mmc1_pads[] = {
 322         MX51_PAD_SD2_CMD__SD2_CMD,
 323         MX51_PAD_SD2_CLK__SD2_CLK,
 324         MX51_PAD_SD2_DATA0__SD2_DATA0,
 325         MX51_PAD_SD2_DATA1__SD2_DATA1,
 326         MX51_PAD_SD2_DATA2__SD2_DATA2,
 327         MX51_PAD_SD2_DATA3__SD2_DATA3,
 328         /* SD2 CD */
 329         MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | GPIO_PAD_CTRL,
 330 };
 331
 332 static struct tx51_esdhc_cfg {
 333         const iomux_v3_cfg_t *pads;
 334         int num_pads;
 335         struct fsl_esdhc_cfg cfg;
 336         int cd_gpio;
 337 } tx51_esdhc_cfg[] = {
 338         {
 339                 .pads = mmc0_pads,
 340                 .num_pads = ARRAY_SIZE(mmc0_pads),
 341                 .cfg = {
 342                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 343                         .max_bus_width = 4,
 344                 },
 345                 .cd_gpio = IMX_GPIO_NR(3, 8),
 346         },
 347         {
 348                 .pads = mmc1_pads,
 349                 .num_pads = ARRAY_SIZE(mmc1_pads),
 350                 .cfg = {
 351                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 352                         .max_bus_width = 4,
 353                 },
 354                 .cd_gpio = IMX_GPIO_NR(3, 6),
 355         },
 356 };
 357
 358 #define to_tx51_esdhc_cfg(p) container_of(p, struct tx51_esdhc_cfg, cfg)
 359
 360 int board_mmc_getcd(struct mmc *mmc)
 361 {
 362         struct tx51_esdhc_cfg *cfg = to_tx51_esdhc_cfg(mmc->priv);
 363
 364         if (cfg->cd_gpio < 0)
 365                 return cfg->cd_gpio;
 366
 367         debug("SD card %d is %spresent\n",
 368                 cfg - tx51_esdhc_cfg,
 369                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 370         return !gpio_get_value(cfg->cd_gpio);
 371 }
 372
 373 int board_mmc_init(bd_t *bis)
 374 {
 375         int i;
 376
 377         for (i = 0; i < ARRAY_SIZE(tx51_esdhc_cfg); i++) {
 378                 struct mmc *mmc;
 379                 struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i];
 380                 int ret;
 381
 382                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 383                         break;
 384
 385                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
 386                                                 cfg->num_pads);
 387                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 388
 389                 fsl_esdhc_initialize(bis, &cfg->cfg);
 390
 391                 ret = gpio_request_one(cfg->cd_gpio,
 392                                 GPIOF_INPUT, "MMC CD");
 393                 if (ret) {
 394                         printf("Error %d requesting GPIO%d_%d\n",
 395                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 396                         continue;
 397                 }
 398
 399                 mmc = find_mmc_device(i);
 400                 if (mmc == NULL)
 401                         continue;
 402                 if (board_mmc_getcd(mmc) > 0)
 403                         mmc_init(mmc);
 404         }
 405         return 0;
 406 }
 407 #endif /* CONFIG_CMD_MMC */
 408
 409 #ifdef CONFIG_FEC_MXC
 410
 411 #ifndef ETH_ALEN
 412 #define ETH_ALEN 6
 413 #endif
 414
 415 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 416 {
 417         int i;
 418         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 419         struct fuse_bank *bank = &iim->bank[1];
 420         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 421
 422         if (dev_id > 0)
 423                 return;
 424
 425         for (i = 0; i < ETH_ALEN; i++)
 426                 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
 427 }
 428
 429 static iomux_v3_cfg_t tx51_fec_pads[] = {
 430         /* reconfigure strap pins for FEC function */
 431         MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
 432         MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
 433         MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
 434         MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
 435         MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
 436         MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
 437         MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
 438 };
 439
 440 /* take bit 4 of PHY address from configured PHY address or
 441  * set it to 0 if PHYADDR is -1 (probe for PHY)
 442  */
 443 #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
 444
 445 static struct gpio tx51_fec_gpios[] = {
 446         { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
 447         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", },       /* RXD0/Mode0 */
 448         { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", },       /* RXD1/Mode1 */
 449         { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", },       /* RXD2/Mode2 */
 450         { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", },     /* RXD3/nINTSEL */
 451 #if PHYAD4
 452         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
 453 #else
 454         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
 455 #endif
 456 };
 457
 458 int board_eth_init(bd_t *bis)
 459 {
 460         int ret;
 461         unsigned char mac[ETH_ALEN];
 462
 463         /* Power up the external phy and assert strap options */
 464         gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
 465
 466         /* delay at least 21ms for the PHY internal POR signal to deassert */
 467         udelay(22000);
 468
 469         /* Deassert RESET to the external phy */
 470         gpio_set_value(TX51_FEC_RST_GPIO, 1);
 471
 472         /* Without this delay the PHY won't work, though nothing in
 473          * the datasheets suggests that it should be necessary!
 474          */
 475         udelay(400);
 476         imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
 477                                         ARRAY_SIZE(tx51_fec_pads));
 478
 479         ret = cpu_eth_init(bis);
 480         if (ret) {
 481                 printf("cpu_eth_init() failed: %d\n", ret);
 482                 return ret;
 483         }
 484
 485         imx_get_mac_from_fuse(0, mac);
 486         eth_setenv_enetaddr("ethaddr", mac);
 487         printf("MAC addr from fuse: %pM\n", mac);
 488
 489         return ret;
 490 }
 491 #endif /* CONFIG_FEC_MXC */
 492
 493 enum {
 494         LED_STATE_INIT = -1,
 495         LED_STATE_OFF,
 496         LED_STATE_ON,
 497 };
 498
 499 void show_activity(int arg)
 500 {
 501         static int led_state = LED_STATE_INIT;
 502         static ulong last;
 503
 504         if (led_state == LED_STATE_INIT) {
 505                 last = get_timer(0);
 506                 gpio_set_value(TX51_LED_GPIO, 1);
 507                 led_state = LED_STATE_ON;
 508         } else {
 509                 if (get_timer(last) > CONFIG_SYS_HZ) {
 510                         last = get_timer(0);
 511                         if (led_state == LED_STATE_ON) {
 512                                 gpio_set_value(TX51_LED_GPIO, 0);
 513                         } else {
 514                                 gpio_set_value(TX51_LED_GPIO, 1);
 515                         }
 516                         led_state = 1 - led_state;
 517                 }
 518         }
 519 }
 520
 521 static const iomux_v3_cfg_t stk5_pads[] = {
 522         /* SW controlled LED on STK5 baseboard */
 523         MX51_PAD_CSI2_D13__GPIO4_10 | GPIO_PAD_CTRL,
 524
 525         /* USB PHY reset */
 526         MX51_PAD_GPIO1_4__GPIO1_4 | GPIO_PAD_CTRL,
 527         /* USBOTG OC */
 528         MX51_PAD_GPIO1_6__GPIO1_6 | GPIO_PAD_CTRL,
 529         /* USB PHY clock enable */
 530         MX51_PAD_GPIO1_7__GPIO1_7 | GPIO_PAD_CTRL,
 531         /* USBH1 VBUS enable */
 532         MX51_PAD_GPIO1_8__GPIO1_8 | GPIO_PAD_CTRL,
 533         /* USBH1 OC */
 534         MX51_PAD_GPIO1_9__GPIO1_9 | GPIO_PAD_CTRL,
 535 };
 536
 537 static const struct gpio stk5_gpios[] = {
 538         { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 539
 540         { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
 541         { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
 542         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
 543         { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 544         { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
 545 };
 546
 547 #ifdef CONFIG_LCD
 548 static ushort tx51_cmap[256];
 549 vidinfo_t panel_info = {
 550         /* set to max. size supported by SoC */
 551         .vl_col = 1600,
 552         .vl_row = 1200,
 553
 554         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 555         .cmap = tx51_cmap,
 556 };
 557
 558 static struct fb_videomode tx51_fb_modes[] = {
 559         {
 560                 /* Standard VGA timing */
 561                 .name           = "VGA",
 562                 .refresh        = 60,
 563                 .xres           = 640,
 564                 .yres           = 480,
 565                 .pixclock       = KHZ2PICOS(25175),
 566                 .left_margin    = 48,
 567                 .hsync_len      = 96,
 568                 .right_margin   = 16,
 569                 .upper_margin   = 31,
 570                 .vsync_len      = 2,
 571                 .lower_margin   = 12,
 572                 .sync           = FB_SYNC_CLK_LAT_FALL,
 573         },
 574         {
 575                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 576                  * DE high active, 115.2 mm x 86.4 mm display area
 577                  * VGA compatible timing
 578                  */
 579                 .name           = "ETV570",
 580                 .refresh        = 60,
 581                 .xres           = 640,
 582                 .yres           = 480,
 583                 .pixclock       = KHZ2PICOS(25175),
 584                 .left_margin    = 114,
 585                 .hsync_len      = 30,
 586                 .right_margin   = 16,
 587                 .upper_margin   = 32,
 588                 .vsync_len      = 3,
 589                 .lower_margin   = 10,
 590                 .sync           = FB_SYNC_CLK_LAT_FALL,
 591         },
 592         {
 593                 /* Emerging ET0350G0DH6 320 x 240 display.
 594                  * 70.08 mm x 52.56 mm display area.
 595                  */
 596                 .name           = "ET0350",
 597                 .refresh        = 60,
 598                 .xres           = 320,
 599                 .yres           = 240,
 600                 .pixclock       = KHZ2PICOS(6500),
 601                 .left_margin    = 68 - 34,
 602                 .hsync_len      = 34,
 603                 .right_margin   = 20,
 604                 .upper_margin   = 18 - 3,
 605                 .vsync_len      = 3,
 606                 .lower_margin   = 4,
 607                 .sync           = FB_SYNC_CLK_LAT_FALL,
 608         },
 609         {
 610                 /* Emerging ET0430G0DH6 480 x 272 display.
 611                  * 95.04 mm x 53.856 mm display area.
 612                  */
 613                 .name           = "ET0430",
 614                 .refresh        = 60,
 615                 .xres           = 480,
 616                 .yres           = 272,
 617                 .pixclock       = KHZ2PICOS(9000),
 618                 .left_margin    = 2,
 619                 .hsync_len      = 41,
 620                 .right_margin   = 2,
 621                 .upper_margin   = 2,
 622                 .vsync_len      = 10,
 623                 .lower_margin   = 2,
 624                 .sync           = FB_SYNC_CLK_LAT_FALL,
 625         },
 626         {
 627                 /* Emerging ET0500G0DH6 800 x 480 display.
 628                  * 109.6 mm x 66.4 mm display area.
 629                  */
 630                 .name           = "ET0500",
 631                 .refresh        = 60,
 632                 .xres           = 800,
 633                 .yres           = 480,
 634                 .pixclock       = KHZ2PICOS(33260),
 635                 .left_margin    = 216 - 128,
 636                 .hsync_len      = 128,
 637                 .right_margin   = 1056 - 800 - 216,
 638                 .upper_margin   = 35 - 2,
 639                 .vsync_len      = 2,
 640                 .lower_margin   = 525 - 480 - 35,
 641                 .sync           = FB_SYNC_CLK_LAT_FALL,
 642         },
 643         {
 644                 /* Emerging ETQ570G0DH6 320 x 240 display.
 645                  * 115.2 mm x 86.4 mm display area.
 646                  */
 647                 .name           = "ETQ570",
 648                 .refresh        = 60,
 649                 .xres           = 320,
 650                 .yres           = 240,
 651                 .pixclock       = KHZ2PICOS(6400),
 652                 .left_margin    = 38,
 653                 .hsync_len      = 30,
 654                 .right_margin   = 30,
 655                 .upper_margin   = 16, /* 15 according to datasheet */
 656                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 657                 .lower_margin   = 4, /* 4.5 according to datasheet */
 658                 .sync           = FB_SYNC_CLK_LAT_FALL,
 659         },
 660         {
 661                 /* Emerging ET0700G0DH6 800 x 480 display.
 662                  * 152.4 mm x 91.44 mm display area.
 663                  */
 664                 .name           = "ET0700",
 665                 .refresh        = 60,
 666                 .xres           = 800,
 667                 .yres           = 480,
 668                 .pixclock       = KHZ2PICOS(33260),
 669                 .left_margin    = 216 - 128,
 670                 .hsync_len      = 128,
 671                 .right_margin   = 1056 - 800 - 216,
 672                 .upper_margin   = 35 - 2,
 673                 .vsync_len      = 2,
 674                 .lower_margin   = 525 - 480 - 35,
 675                 .sync           = FB_SYNC_CLK_LAT_FALL,
 676         },
 677         {
 678                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 679                 .refresh        = 60,
 680                 .left_margin    = 48,
 681                 .hsync_len      = 96,
 682                 .right_margin   = 16,
 683                 .upper_margin   = 31,
 684                 .vsync_len      = 2,
 685                 .lower_margin   = 12,
 686                 .sync           = FB_SYNC_CLK_LAT_FALL,
 687         },
 688 };
 689
 690 static int lcd_enabled = 1;
 691
 692 void lcd_enable(void)
 693 {
 694         /* HACK ALERT:
 695          * global variable from common/lcd.c
 696          * Set to 0 here to prevent messages from going to LCD
 697          * rather than serial console
 698          */
 699         lcd_is_enabled = 0;
 700
 701         karo_load_splashimage(1);
 702         if (lcd_enabled) {
 703                 debug("Switching LCD on\n");
 704                 gpio_set_value(TX51_LCD_PWR_GPIO, 1);
 705                 udelay(100);
 706                 gpio_set_value(TX51_LCD_RST_GPIO, 1);
 707                 udelay(300000);
 708                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 0);
 709         }
 710 }
 711
 712 void lcd_disable(void)
 713 {
 714         printf("Disabling LCD\n");
 715 }
 716
 717 void lcd_panel_disable(void)
 718 {
 719         if (lcd_enabled) {
 720                 debug("Switching LCD off\n");
 721                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 1);
 722                 gpio_set_value(TX51_LCD_RST_GPIO, 0);
 723                 gpio_set_value(TX51_LCD_PWR_GPIO, 0);
 724         }
 725 }
 726
 727 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 728         /* LCD RESET */
 729         MX51_PAD_CSI2_VSYNC__GPIO4_13,
 730         /* LCD POWER_ENABLE */
 731         MX51_PAD_CSI2_HSYNC__GPIO4_14,
 732         /* LCD Backlight (PWM) */
 733         MX51_PAD_GPIO1_2__GPIO1_2,
 734
 735         /* Display */
 736         MX51_PAD_DISP1_DAT0__DISP1_DAT0,
 737         MX51_PAD_DISP1_DAT1__DISP1_DAT1,
 738         MX51_PAD_DISP1_DAT2__DISP1_DAT2,
 739         MX51_PAD_DISP1_DAT3__DISP1_DAT3,
 740         MX51_PAD_DISP1_DAT4__DISP1_DAT4,
 741         MX51_PAD_DISP1_DAT5__DISP1_DAT5,
 742         MX51_PAD_DISP1_DAT6__DISP1_DAT6,
 743         MX51_PAD_DISP1_DAT7__DISP1_DAT7,
 744         MX51_PAD_DISP1_DAT8__DISP1_DAT8,
 745         MX51_PAD_DISP1_DAT9__DISP1_DAT9,
 746         MX51_PAD_DISP1_DAT10__DISP1_DAT10,
 747         MX51_PAD_DISP1_DAT11__DISP1_DAT11,
 748         MX51_PAD_DISP1_DAT12__DISP1_DAT12,
 749         MX51_PAD_DISP1_DAT13__DISP1_DAT13,
 750         MX51_PAD_DISP1_DAT14__DISP1_DAT14,
 751         MX51_PAD_DISP1_DAT15__DISP1_DAT15,
 752         MX51_PAD_DISP1_DAT16__DISP1_DAT16,
 753         MX51_PAD_DISP1_DAT17__DISP1_DAT17,
 754         MX51_PAD_DISP1_DAT18__DISP1_DAT18,
 755         MX51_PAD_DISP1_DAT19__DISP1_DAT19,
 756         MX51_PAD_DISP1_DAT20__DISP1_DAT20,
 757         MX51_PAD_DISP1_DAT21__DISP1_DAT21,
 758         MX51_PAD_DISP1_DAT22__DISP1_DAT22,
 759         MX51_PAD_DISP1_DAT23__DISP1_DAT23,
 760         MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
 761         MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
 762 };
 763
 764 static const struct gpio stk5_lcd_gpios[] = {
 765         { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 766         { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 767         { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 768 };
 769
 770 void lcd_ctrl_init(void *lcdbase)
 771 {
 772         int color_depth = 24;
 773         char *vm;
 774         unsigned long val;
 775         int refresh = 60;
 776         struct fb_videomode *p = &tx51_fb_modes[0];
 777         struct fb_videomode fb_mode;
 778         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 779         int pix_fmt = 0;
 780         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 781         unsigned long di_clk_rate = 65000000;
 782
 783         if (!lcd_enabled) {
 784                 debug("LCD disabled\n");
 785                 return;
 786         }
 787
 788         if (tstc() || (wrsr & WRSR_TOUT)) {
 789                 debug("Disabling LCD\n");
 790                 lcd_enabled = 0;
 791                 return;
 792         }
 793
 794         karo_fdt_move_fdt();
 795
 796         vm = getenv("video_mode");
 797         if (vm == NULL) {
 798                 debug("Disabling LCD\n");
 799                 lcd_enabled = 0;
 800                 return;
 801         }
 802         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 803                 p = &fb_mode;
 804                 debug("Using video mode from FDT\n");
 805                 vm += strlen(vm);
 806                 if (fb_mode.xres < panel_info.vl_col)
 807                         panel_info.vl_col = fb_mode.xres;
 808                 if (fb_mode.yres < panel_info.vl_row)
 809                         panel_info.vl_row = fb_mode.yres;
 810         }
 811         if (p->name != NULL)
 812                 debug("Trying compiled-in video modes\n");
 813         while (p->name != NULL) {
 814                 if (strcmp(p->name, vm) == 0) {
 815                         debug("Using video mode: '%s'\n", p->name);
 816                         vm += strlen(vm);
 817                         break;
 818                 }
 819                 p++;
 820         }
 821         if (*vm != '\0')
 822                 debug("Trying to decode video_mode: '%s'\n", vm);
 823         while (*vm != '\0') {
 824                 if (*vm >= '0' && *vm <= '9') {
 825                         char *end;
 826
 827                         val = simple_strtoul(vm, &end, 0);
 828                         if (end > vm) {
 829                                 if (!xres_set) {
 830                                         if (val > panel_info.vl_col)
 831                                                 val = panel_info.vl_col;
 832                                         p->xres = val;
 833                                         panel_info.vl_col = val;
 834                                         xres_set = 1;
 835                                 } else if (!yres_set) {
 836                                         if (val > panel_info.vl_row)
 837                                                 val = panel_info.vl_row;
 838                                         p->yres = val;
 839                                         panel_info.vl_row = val;
 840                                         yres_set = 1;
 841                                 } else if (!bpp_set) {
 842                                         switch (val) {
 843                                         case 8:
 844                                         case 16:
 845                                         case 24:
 846                                                 color_depth = val;
 847                                                 break;
 848
 849                                         default:
 850                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 851                                                         end - vm, vm, color_depth);
 852                                         }
 853                                         bpp_set = 1;
 854                                 } else if (!refresh_set) {
 855                                         refresh = val;
 856                                         refresh_set = 1;
 857                                 }
 858                         }
 859                         vm = end;
 860                 }
 861                 switch (*vm) {
 862                 case '@':
 863                         bpp_set = 1;
 864                         /* fallthru */
 865                 case '-':
 866                         yres_set = 1;
 867                         /* fallthru */
 868                 case 'x':
 869                         xres_set = 1;
 870                         /* fallthru */
 871                 case 'M':
 872                 case 'R':
 873                         vm++;
 874                         break;
 875
 876                 default:
 877                         if (!pix_fmt) {
 878                                 char *tmp;
 879
 880                                 pix_fmt = IPU_PIX_FMT_RGB24;
 881                                 tmp = strchr(vm, ':');
 882                                 if (tmp)
 883                                         vm = tmp;
 884                         }
 885                         if (*vm != '\0')
 886                                 vm++;
 887                 }
 888         }
 889         if (p->xres == 0 || p->yres == 0) {
 890                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 891                 lcd_enabled = 0;
 892                 printf("Supported video modes are:");
 893                 for (p = &tx51_fb_modes[0]; p->name != NULL; p++) {
 894                         printf(" %s", p->name);
 895                 }
 896                 printf("\n");
 897                 return;
 898         }
 899
 900         p->pixclock = KHZ2PICOS(refresh *
 901                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 902                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 903                 / 1000);
 904         debug("Pixel clock set to %lu.%03lu MHz\n",
 905                 PICOS2KHZ(p->pixclock) / 1000,
 906                 PICOS2KHZ(p->pixclock) % 1000);
 907
 908         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 909         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 910                                         ARRAY_SIZE(stk5_lcd_pads));
 911
 912         debug("Initializing FB driver\n");
 913         if (!pix_fmt)
 914                 pix_fmt = IPU_PIX_FMT_RGB24;
 915
 916         if (karo_load_splashimage(0) == 0) {
 917                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 918                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
 919
 920                 /* MIPI HSC clock is required for initialization */
 921                 writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
 922
 923                 debug("Initializing LCD controller\n");
 924                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 925
 926                 writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
 927         } else {
 928                 debug("Skipping initialization of LCD controller\n");
 929         }
 930 }
 931 #else
 932 #define lcd_enabled 0
 933 #endif /* CONFIG_LCD */
 934
 935 static void stk5_board_init(void)
 936 {
 937         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 938         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 939 }
 940
 941 static void stk5v3_board_init(void)
 942 {
 943         stk5_board_init();
 944 }
 945
 946 static void tx51_set_cpu_clock(void)
 947 {
 948         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 949         int ret;
 950
 951         if (tstc() || (wrsr & WRSR_TOUT))
 952                 return;
 953
 954         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 955                 return;
 956
 957         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
 958         if (ret != 0) {
 959                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 960                 return;
 961         }
 962         printf("CPU clock set to %u.%03u MHz\n",
 963                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
 964                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
 965 }
 966
 967 int board_late_init(void)
 968 {
 969         int ret = 0;
 970         const char *baseboard;
 971
 972         tx51_set_cpu_clock();
 973         karo_fdt_move_fdt();
 974
 975         baseboard = getenv("baseboard");
 976         if (!baseboard)
 977                 goto exit;
 978
 979         if (strncmp(baseboard, "stk5", 4) == 0) {
 980                 printf("Baseboard: %s\n", baseboard);
 981                 if ((strlen(baseboard) == 4) ||
 982                         strcmp(baseboard, "stk5-v3") == 0) {
 983                         stk5v3_board_init();
 984                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 985                         printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
 986                                 baseboard);
 987                         stk5v3_board_init();
 988                 } else {
 989                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 990                                 baseboard + 4);
 991                 }
 992         } else {
 993                 printf("WARNING: Unsupported baseboard: '%s'\n",
 994                         baseboard);
 995                 ret = -EINVAL;
 996         }
 997
 998 exit:
 999         gpio_set_value(TX51_RESET_OUT_GPIO, 1);
1000         return ret;
1001 }
1002
1003 int checkboard(void)
1004 {
1005         tx51_print_cpuinfo();
1006
1007         printf("Board: Ka-Ro TX51-%sxx%s\n",
1008                 TX51_MOD_PREFIX, TX51_MOD_SUFFIX);
1009
1010         return 0;
1011 }
1012
1013 #if defined(CONFIG_OF_BOARD_SETUP)
1014 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1015 #include <jffs2/jffs2.h>
1016 #include <mtd_node.h>
1017 struct node_info nodes[] = {
1018         { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
1019 };
1020
1021 #else
1022 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1023 #endif
1024
1025 void ft_board_setup(void *blob, bd_t *bd)
1026 {
1027         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1028         fdt_fixup_ethernet(blob);
1029
1030         karo_fdt_fixup_touchpanel(blob);
1031         karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1032 }
1033 #endif