board/karo/tx51/tx51.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <lcd.h>
  24 #include <netdev.h>
  25 #include <mmc.h>
  26 #include <fsl_esdhc.h>
  27 #include <video_fb.h>
  28 #include <ipu.h>
  29 #include <mxcfb.h>
  30 #include <linux/fb.h>
  31 #include <asm/io.h>
  32 #include <asm/gpio.h>
  33 #include <asm/arch/iomux-mx51.h>
  34 #include <asm/arch/clock.h>
  35 #include <asm/arch/imx-regs.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 #include "../common/karo.h"
  40
  41 #define TX51_FEC_RST_GPIO       IMX_GPIO_NR(2, 14)
  42 #define TX51_FEC_PWR_GPIO       IMX_GPIO_NR(1, 3)
  43 #define TX51_FEC_INT_GPIO       IMX_GPIO_NR(3, 18)
  44 #define TX51_LED_GPIO           IMX_GPIO_NR(4, 10)
  45
  46 #define TX51_LCD_PWR_GPIO       IMX_GPIO_NR(4, 14)
  47 #define TX51_LCD_RST_GPIO       IMX_GPIO_NR(4, 13)
  48 #define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
  49
  50 #define TX51_RESET_OUT_GPIO     IMX_GPIO_NR(2, 15)
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 #define IOMUX_SION              IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  55
  56 #define FEC_PAD_CTRL            MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
  57                                         PAD_CTL_SRE_FAST)
  58 #define FEC_PAD_CTRL2           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_SRE_FAST)
  59 #define GPIO_PAD_CTRL           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP)
  60
  61 static iomux_v3_cfg_t tx51_pads[] = {
  62         /* NAND flash pads are set up in lowlevel_init.S */
  63
  64         /* RESET_OUT */
  65         MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
  66
  67         /* UART pads */
  68 #if CONFIG_MXC_UART_BASE == UART1_BASE
  69         MX51_PAD_UART1_RXD__UART1_RXD,
  70         MX51_PAD_UART1_TXD__UART1_TXD,
  71         MX51_PAD_UART1_RTS__UART1_RTS,
  72         MX51_PAD_UART1_CTS__UART1_CTS,
  73 #endif
  74 #if CONFIG_MXC_UART_BASE == UART2_BASE
  75         MX51_PAD_UART2_RXD__UART2_RXD,
  76         MX51_PAD_UART2_TXD__UART2_TXD,
  77         MX51_PAD_EIM_D26__UART2_RTS,
  78         MX51_PAD_EIM_D25__UART2_CTS,
  79 #endif
  80 #if CONFIG_MXC_UART_BASE == UART3_BASE
  81         MX51_PAD_UART3_RXD__UART3_RXD,
  82         MX51_PAD_UART3_TXD__UART3_TXD,
  83         MX51_PAD_EIM_D18__UART3_RTS,
  84         MX51_PAD_EIM_D17__UART3_CTS,
  85 #endif
  86         /* internal I2C */
  87         MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
  88         MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
  89
  90         /* FEC PHY GPIO functions */
  91         MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL,    /* PHY POWER */
  92         MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL,   /* PHY RESET */
  93         MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
  94
  95         /* FEC functions */
  96         MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
  97         MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
  98         MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
  99         MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
 100         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
 101         MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
 102         MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
 103         MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
 104         MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
 105         MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
 106
 107         /* strap pins for PHY configuration */
 108         MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
 109         MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL,  /* RXD0/Mode0 */
 110         MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL,   /* RXD1/Mode1 */
 111         MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL,   /* RXD2/Mode2 */
 112         MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL,   /* RXD3/nINTSEL */
 113         MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
 114         MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL,   /* CRS/PHYAD4 */
 115
 116         /* unusable pins on TX51 */
 117         MX51_PAD_GPIO1_0__GPIO1_0,
 118         MX51_PAD_GPIO1_1__GPIO1_1,
 119 };
 120
 121 static const struct gpio tx51_gpios[] = {
 122         /* RESET_OUT */
 123         { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
 124
 125         /* FEC PHY control GPIOs */
 126         { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
 127         { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
 128         { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },         /* PHY INT (TX_ER) */
 129
 130         /* FEC PHY strap pins */
 131         { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", },  /* RX_CLK/REGOFF */
 132         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", },   /* RXD0/Mode0 */
 133         { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", },   /* RXD1/Mode1 */
 134         { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", },   /* RXD2/Mode2 */
 135         { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
 136         { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", },    /* COL/RMII/CRSDV */
 137         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", },  /* CRS/PHYAD4 */
 138
 139         /* module internal I2C bus */
 140         { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
 141         { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
 142
 143         /* Unconnected pins */
 144         { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
 145         { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
 146 };
 147
 148 /*
 149  * Functions
 150  */
 151 /* placed in section '.data' to prevent overwriting relocation info
 152  * overlayed with bss
 153  */
 154 static u32 wrsr __attribute__((section(".data")));
 155
 156 #define WRSR_POR        (1 << 4)
 157 #define WRSR_TOUT       (1 << 1)
 158 #define WRSR_SFTW       (1 << 0)
 159
 160 static void print_reset_cause(void)
 161 {
 162         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 163         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 164         u32 srsr;
 165         char *dlm = "";
 166
 167         printf("Reset cause: ");
 168
 169         srsr = readl(&src_regs->srsr);
 170         wrsr = readw(wdt_base + 4);
 171
 172         if (wrsr & WRSR_POR) {
 173                 printf("%sPOR", dlm);
 174                 dlm = " | ";
 175         }
 176         if (srsr & 0x00004) {
 177                 printf("%sCSU", dlm);
 178                 dlm = " | ";
 179         }
 180         if (srsr & 0x00008) {
 181                 printf("%sIPP USER", dlm);
 182                 dlm = " | ";
 183         }
 184         if (srsr & 0x00010) {
 185                 if (wrsr & WRSR_SFTW) {
 186                         printf("%sSOFT", dlm);
 187                         dlm = " | ";
 188                 }
 189                 if (wrsr & WRSR_TOUT) {
 190                         printf("%sWDOG", dlm);
 191                         dlm = " | ";
 192                 }
 193         }
 194         if (srsr & 0x00020) {
 195                 printf("%sJTAG HIGH-Z", dlm);
 196                 dlm = " | ";
 197         }
 198         if (srsr & 0x00040) {
 199                 printf("%sJTAG SW", dlm);
 200                 dlm = " | ";
 201         }
 202         if (srsr & 0x10000) {
 203                 printf("%sWARM BOOT", dlm);
 204                 dlm = " | ";
 205         }
 206         if (dlm[0] == '\0')
 207                 printf("unknown");
 208
 209         printf("\n");
 210 }
 211
 212 static void tx51_print_cpuinfo(void)
 213 {
 214         u32 cpurev;
 215
 216         cpurev = get_cpu_rev();
 217
 218         printf("CPU:   Freescale i.MX51 rev%d.%d at %d MHz\n",
 219                 (cpurev & 0x000F0) >> 4,
 220                 (cpurev & 0x0000F) >> 0,
 221                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 222
 223         print_reset_cause();
 224 }
 225
 226 int board_early_init_f(void)
 227 {
 228         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 229
 230         gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
 231         imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
 232
 233         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 234         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 235
 236         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 237         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 238         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 239         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 240         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 241
 242         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 243         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 244
 245         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 246         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 247         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 248         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 249         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 250
 251         writel(0xffcffffc, &ccm_regs->CCGR0);
 252         writel(0x003fffff, &ccm_regs->CCGR1);
 253         writel(0x030c003c, &ccm_regs->CCGR2);
 254         writel(0x000000ff, &ccm_regs->CCGR3);
 255         writel(0x00000000, &ccm_regs->CCGR4);
 256         writel(0x003fc003, &ccm_regs->CCGR5);
 257         writel(0x00000000, &ccm_regs->CCGR6);
 258         writel(0x00000000, &ccm_regs->cmeor);
 259 #ifdef CONFIG_CMD_BOOTCE
 260         /* WinCE fails to enable these clocks */
 261         writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
 262         writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
 263         writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
 264 #endif
 265         return 0;
 266 }
 267
 268 int board_init(void)
 269 {
 270         /* Address of boot parameters */
 271         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 272         return 0;
 273 }
 274
 275 int dram_init(void)
 276 {
 277         int ret;
 278
 279         /* dram_init must store complete ramsize in gd->ram_size */
 280         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 281                                 PHYS_SDRAM_1_SIZE);
 282
 283         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 284                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 285         if (ret)
 286                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 287                         CONFIG_SYS_SDRAM_CLK, ret);
 288         else
 289                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 290                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 291                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 292                         CONFIG_SYS_SDRAM_CLK);
 293         return ret;
 294 }
 295
 296 void dram_init_banksize(void)
 297 {
 298         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 299         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 300                         PHYS_SDRAM_1_SIZE);
 301 #if CONFIG_NR_DRAM_BANKS > 1
 302         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 303         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 304                         PHYS_SDRAM_2_SIZE);
 305 #endif
 306 }
 307
 308 #ifdef  CONFIG_CMD_MMC
 309 static const iomux_v3_cfg_t mmc0_pads[] = {
 310         MX51_PAD_SD1_CMD__SD1_CMD,
 311         MX51_PAD_SD1_CLK__SD1_CLK,
 312         MX51_PAD_SD1_DATA0__SD1_DATA0,
 313         MX51_PAD_SD1_DATA1__SD1_DATA1,
 314         MX51_PAD_SD1_DATA2__SD1_DATA2,
 315         MX51_PAD_SD1_DATA3__SD1_DATA3,
 316         /* SD1 CD */
 317         MX51_PAD_DISPB2_SER_RS__GPIO3_8 | GPIO_PAD_CTRL,
 318 };
 319
 320 static const iomux_v3_cfg_t mmc1_pads[] = {
 321         MX51_PAD_SD2_CMD__SD2_CMD,
 322         MX51_PAD_SD2_CLK__SD2_CLK,
 323         MX51_PAD_SD2_DATA0__SD2_DATA0,
 324         MX51_PAD_SD2_DATA1__SD2_DATA1,
 325         MX51_PAD_SD2_DATA2__SD2_DATA2,
 326         MX51_PAD_SD2_DATA3__SD2_DATA3,
 327         /* SD2 CD */
 328         MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | GPIO_PAD_CTRL,
 329 };
 330
 331 static struct tx51_esdhc_cfg {
 332         const iomux_v3_cfg_t *pads;
 333         int num_pads;
 334         struct fsl_esdhc_cfg cfg;
 335         int cd_gpio;
 336 } tx51_esdhc_cfg[] = {
 337         {
 338                 .pads = mmc0_pads,
 339                 .num_pads = ARRAY_SIZE(mmc0_pads),
 340                 .cfg = {
 341                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 342                         .max_bus_width = 4,
 343                 },
 344                 .cd_gpio = IMX_GPIO_NR(3, 8),
 345         },
 346         {
 347                 .pads = mmc1_pads,
 348                 .num_pads = ARRAY_SIZE(mmc1_pads),
 349                 .cfg = {
 350                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 351                         .max_bus_width = 4,
 352                 },
 353                 .cd_gpio = IMX_GPIO_NR(3, 6),
 354         },
 355 };
 356
 357 #define to_tx51_esdhc_cfg(p) container_of(p, struct tx51_esdhc_cfg, cfg)
 358
 359 int board_mmc_getcd(struct mmc *mmc)
 360 {
 361         struct tx51_esdhc_cfg *cfg = to_tx51_esdhc_cfg(mmc->priv);
 362
 363         if (cfg->cd_gpio < 0)
 364                 return cfg->cd_gpio;
 365
 366         debug("SD card %d is %spresent\n",
 367                 cfg - tx51_esdhc_cfg,
 368                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 369         return !gpio_get_value(cfg->cd_gpio);
 370 }
 371
 372 int board_mmc_init(bd_t *bis)
 373 {
 374         int i;
 375
 376         for (i = 0; i < ARRAY_SIZE(tx51_esdhc_cfg); i++) {
 377                 struct mmc *mmc;
 378                 struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i];
 379                 int ret;
 380
 381                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
 382                                                 cfg->num_pads);
 383                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 384
 385                 fsl_esdhc_initialize(bis, &cfg->cfg);
 386
 387                 ret = gpio_request_one(cfg->cd_gpio,
 388                                 GPIOF_INPUT, "MMC CD");
 389                 if (ret) {
 390                         printf("Error %d requesting GPIO%d_%d\n",
 391                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 392                         continue;
 393                 }
 394
 395                 mmc = find_mmc_device(i);
 396                 if (mmc == NULL)
 397                         continue;
 398                 if (board_mmc_getcd(mmc) > 0)
 399                         mmc_init(mmc);
 400         }
 401         return 0;
 402 }
 403 #endif /* CONFIG_CMD_MMC */
 404
 405 #ifdef CONFIG_FEC_MXC
 406
 407 #ifndef ETH_ALEN
 408 #define ETH_ALEN 6
 409 #endif
 410
 411 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 412 {
 413         int i;
 414         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 415         struct fuse_bank *bank = &iim->bank[1];
 416         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 417
 418         if (dev_id > 0)
 419                 return;
 420
 421         for (i = 0; i < ETH_ALEN; i++)
 422                 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
 423 }
 424
 425 static iomux_v3_cfg_t tx51_fec_pads[] = {
 426         /* reconfigure strap pins for FEC function */
 427         MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
 428         MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
 429         MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
 430         MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
 431         MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
 432         MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
 433         MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
 434 };
 435
 436 /* take bit 4 of PHY address from configured PHY address or
 437  * set it to 0 if PHYADDR is -1 (probe for PHY)
 438  */
 439 #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
 440
 441 static struct gpio tx51_fec_gpios[] = {
 442         { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
 443         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", },       /* RXD0/Mode0 */
 444         { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", },       /* RXD1/Mode1 */
 445         { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", },       /* RXD2/Mode2 */
 446         { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", },     /* RXD3/nINTSEL */
 447 #if PHYAD4
 448         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
 449 #else
 450         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
 451 #endif
 452 };
 453
 454 int board_eth_init(bd_t *bis)
 455 {
 456         int ret;
 457
 458         /* Power up the external phy and assert strap options */
 459         gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
 460
 461         /* delay at least 21ms for the PHY internal POR signal to deassert */
 462         udelay(22000);
 463
 464         /* Deassert RESET to the external phy */
 465         gpio_set_value(TX51_FEC_RST_GPIO, 1);
 466
 467         /* Without this delay the PHY won't work, though nothing in
 468          * the datasheets suggests that it should be necessary!
 469          */
 470         udelay(400);
 471         imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
 472                                         ARRAY_SIZE(tx51_fec_pads));
 473
 474         ret = cpu_eth_init(bis);
 475         if (ret)
 476                 printf("cpu_eth_init() failed: %d\n", ret);
 477         return ret;
 478 }
 479 #endif /* CONFIG_FEC_MXC */
 480
 481 enum {
 482         LED_STATE_INIT = -1,
 483         LED_STATE_OFF,
 484         LED_STATE_ON,
 485 };
 486
 487 void show_activity(int arg)
 488 {
 489         static int led_state = LED_STATE_INIT;
 490         static ulong last;
 491
 492         if (led_state == LED_STATE_INIT) {
 493                 last = get_timer(0);
 494                 gpio_set_value(TX51_LED_GPIO, 1);
 495                 led_state = LED_STATE_ON;
 496         } else {
 497                 if (get_timer(last) > CONFIG_SYS_HZ) {
 498                         last = get_timer(0);
 499                         if (led_state == LED_STATE_ON) {
 500                                 gpio_set_value(TX51_LED_GPIO, 0);
 501                         } else {
 502                                 gpio_set_value(TX51_LED_GPIO, 1);
 503                         }
 504                         led_state = 1 - led_state;
 505                 }
 506         }
 507 }
 508
 509 static const iomux_v3_cfg_t stk5_pads[] = {
 510         /* SW controlled LED on STK5 baseboard */
 511         MX51_PAD_CSI2_D13__GPIO4_10 | GPIO_PAD_CTRL,
 512
 513         /* USB PHY reset */
 514         MX51_PAD_GPIO1_4__GPIO1_4 | GPIO_PAD_CTRL,
 515         /* USBOTG OC */
 516         MX51_PAD_GPIO1_6__GPIO1_6 | GPIO_PAD_CTRL,
 517         /* USB PHY clock enable */
 518         MX51_PAD_GPIO1_7__GPIO1_7 | GPIO_PAD_CTRL,
 519         /* USBH1 VBUS enable */
 520         MX51_PAD_GPIO1_8__GPIO1_8 | GPIO_PAD_CTRL,
 521         /* USBH1 OC */
 522         MX51_PAD_GPIO1_9__GPIO1_9 | GPIO_PAD_CTRL,
 523 };
 524
 525 static const struct gpio stk5_gpios[] = {
 526         { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 527
 528         { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
 529         { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
 530         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
 531         { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 532         { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
 533 };
 534
 535 #ifdef CONFIG_LCD
 536 vidinfo_t panel_info = {
 537         /* set to max. size supported by SoC */
 538         .vl_col = 1600,
 539         .vl_row = 1200,
 540
 541         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 542 };
 543
 544 static struct fb_videomode tx51_fb_modes[] = {
 545         {
 546                 /* Standard VGA timing */
 547                 .name           = "VGA",
 548                 .refresh        = 60,
 549                 .xres           = 640,
 550                 .yres           = 480,
 551                 .pixclock       = KHZ2PICOS(25175),
 552                 .left_margin    = 48,
 553                 .hsync_len      = 96,
 554                 .right_margin   = 16,
 555                 .upper_margin   = 31,
 556                 .vsync_len      = 2,
 557                 .lower_margin   = 12,
 558                 .sync           = FB_SYNC_CLK_LAT_FALL,
 559         },
 560         {
 561                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 562                  * DE high active, 115.2 mm x 86.4 mm display area
 563                  * VGA compatible timing
 564                  */
 565                 .name           = "ETV570",
 566                 .refresh        = 60,
 567                 .xres           = 640,
 568                 .yres           = 480,
 569                 .pixclock       = KHZ2PICOS(25175),
 570                 .left_margin    = 114,
 571                 .hsync_len      = 30,
 572                 .right_margin   = 16,
 573                 .upper_margin   = 32,
 574                 .vsync_len      = 3,
 575                 .lower_margin   = 10,
 576                 .sync           = FB_SYNC_CLK_LAT_FALL,
 577         },
 578         {
 579                 /* Emerging ET0350G0DH6 320 x 240 display.
 580                  * 70.08 mm x 52.56 mm display area.
 581                  */
 582                 .name           = "ET0350",
 583                 .refresh        = 60,
 584                 .xres           = 320,
 585                 .yres           = 240,
 586                 .pixclock       = KHZ2PICOS(6500),
 587                 .left_margin    = 68 - 34,
 588                 .hsync_len      = 34,
 589                 .right_margin   = 20,
 590                 .upper_margin   = 18 - 3,
 591                 .vsync_len      = 3,
 592                 .lower_margin   = 4,
 593                 .sync           = FB_SYNC_CLK_LAT_FALL,
 594         },
 595         {
 596                 /* Emerging ET0430G0DH6 480 x 272 display.
 597                  * 95.04 mm x 53.856 mm display area.
 598                  */
 599                 .name           = "ET0430",
 600                 .refresh        = 60,
 601                 .xres           = 480,
 602                 .yres           = 272,
 603                 .pixclock       = KHZ2PICOS(9000),
 604                 .left_margin    = 2,
 605                 .hsync_len      = 41,
 606                 .right_margin   = 2,
 607                 .upper_margin   = 2,
 608                 .vsync_len      = 10,
 609                 .lower_margin   = 2,
 610                 .sync           = FB_SYNC_CLK_LAT_FALL,
 611         },
 612         {
 613                 /* Emerging ET0500G0DH6 800 x 480 display.
 614                  * 109.6 mm x 66.4 mm display area.
 615                  */
 616                 .name           = "ET0500",
 617                 .refresh        = 60,
 618                 .xres           = 800,
 619                 .yres           = 480,
 620                 .pixclock       = KHZ2PICOS(33260),
 621                 .left_margin    = 216 - 128,
 622                 .hsync_len      = 128,
 623                 .right_margin   = 1056 - 800 - 216,
 624                 .upper_margin   = 35 - 2,
 625                 .vsync_len      = 2,
 626                 .lower_margin   = 525 - 480 - 35,
 627                 .sync           = FB_SYNC_CLK_LAT_FALL,
 628         },
 629         {
 630                 /* Emerging ETQ570G0DH6 320 x 240 display.
 631                  * 115.2 mm x 86.4 mm display area.
 632                  */
 633                 .name           = "ETQ570",
 634                 .refresh        = 60,
 635                 .xres           = 320,
 636                 .yres           = 240,
 637                 .pixclock       = KHZ2PICOS(6400),
 638                 .left_margin    = 38,
 639                 .hsync_len      = 30,
 640                 .right_margin   = 30,
 641                 .upper_margin   = 16, /* 15 according to datasheet */
 642                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 643                 .lower_margin   = 4, /* 4.5 according to datasheet */
 644                 .sync           = FB_SYNC_CLK_LAT_FALL,
 645         },
 646         {
 647                 /* Emerging ET0700G0DH6 800 x 480 display.
 648                  * 152.4 mm x 91.44 mm display area.
 649                  */
 650                 .name           = "ET0700",
 651                 .refresh        = 60,
 652                 .xres           = 800,
 653                 .yres           = 480,
 654                 .pixclock       = KHZ2PICOS(33260),
 655                 .left_margin    = 216 - 128,
 656                 .hsync_len      = 128,
 657                 .right_margin   = 1056 - 800 - 216,
 658                 .upper_margin   = 35 - 2,
 659                 .vsync_len      = 2,
 660                 .lower_margin   = 525 - 480 - 35,
 661                 .sync           = FB_SYNC_CLK_LAT_FALL,
 662         },
 663         {
 664                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 665                 .refresh        = 60,
 666                 .left_margin    = 48,
 667                 .hsync_len      = 96,
 668                 .right_margin   = 16,
 669                 .upper_margin   = 31,
 670                 .vsync_len      = 2,
 671                 .lower_margin   = 12,
 672                 .sync           = FB_SYNC_CLK_LAT_FALL,
 673         },
 674 };
 675
 676 static int lcd_enabled = 1;
 677 static int lcd_bl_polarity;
 678
 679 static int lcd_backlight_polarity(void)
 680 {
 681         return lcd_bl_polarity;
 682 }
 683
 684 void lcd_enable(void)
 685 {
 686         /* HACK ALERT:
 687          * global variable from common/lcd.c
 688          * Set to 0 here to prevent messages from going to LCD
 689          * rather than serial console
 690          */
 691         lcd_is_enabled = 0;
 692
 693         if (lcd_enabled) {
 694                 karo_load_splashimage(1);
 695
 696                 debug("Switching LCD on\n");
 697                 gpio_set_value(TX51_LCD_PWR_GPIO, 1);
 698                 udelay(100);
 699                 gpio_set_value(TX51_LCD_RST_GPIO, 1);
 700                 udelay(300000);
 701                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
 702                         lcd_backlight_polarity());
 703         }
 704 }
 705
 706 void lcd_disable(void)
 707 {
 708         if (lcd_enabled) {
 709                 printf("Disabling LCD\n");
 710                 ipuv3_fb_shutdown();
 711         }
 712 }
 713
 714 void lcd_panel_disable(void)
 715 {
 716         if (lcd_enabled) {
 717                 debug("Switching LCD off\n");
 718                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
 719                         !lcd_backlight_polarity());
 720                 gpio_set_value(TX51_LCD_RST_GPIO, 0);
 721                 gpio_set_value(TX51_LCD_PWR_GPIO, 0);
 722         }
 723 }
 724
 725 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 726         /* LCD RESET */
 727         MX51_PAD_CSI2_VSYNC__GPIO4_13,
 728         /* LCD POWER_ENABLE */
 729         MX51_PAD_CSI2_HSYNC__GPIO4_14,
 730         /* LCD Backlight (PWM) */
 731         MX51_PAD_GPIO1_2__GPIO1_2,
 732
 733         /* Display */
 734         MX51_PAD_DISP1_DAT0__DISP1_DAT0,
 735         MX51_PAD_DISP1_DAT1__DISP1_DAT1,
 736         MX51_PAD_DISP1_DAT2__DISP1_DAT2,
 737         MX51_PAD_DISP1_DAT3__DISP1_DAT3,
 738         MX51_PAD_DISP1_DAT4__DISP1_DAT4,
 739         MX51_PAD_DISP1_DAT5__DISP1_DAT5,
 740         MX51_PAD_DISP1_DAT6__DISP1_DAT6,
 741         MX51_PAD_DISP1_DAT7__DISP1_DAT7,
 742         MX51_PAD_DISP1_DAT8__DISP1_DAT8,
 743         MX51_PAD_DISP1_DAT9__DISP1_DAT9,
 744         MX51_PAD_DISP1_DAT10__DISP1_DAT10,
 745         MX51_PAD_DISP1_DAT11__DISP1_DAT11,
 746         MX51_PAD_DISP1_DAT12__DISP1_DAT12,
 747         MX51_PAD_DISP1_DAT13__DISP1_DAT13,
 748         MX51_PAD_DISP1_DAT14__DISP1_DAT14,
 749         MX51_PAD_DISP1_DAT15__DISP1_DAT15,
 750         MX51_PAD_DISP1_DAT16__DISP1_DAT16,
 751         MX51_PAD_DISP1_DAT17__DISP1_DAT17,
 752         MX51_PAD_DISP1_DAT18__DISP1_DAT18,
 753         MX51_PAD_DISP1_DAT19__DISP1_DAT19,
 754         MX51_PAD_DISP1_DAT20__DISP1_DAT20,
 755         MX51_PAD_DISP1_DAT21__DISP1_DAT21,
 756         MX51_PAD_DISP1_DAT22__DISP1_DAT22,
 757         MX51_PAD_DISP1_DAT23__DISP1_DAT23,
 758         MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
 759         MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
 760 };
 761
 762 static const struct gpio stk5_lcd_gpios[] = {
 763         { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 764         { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 765         { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 766 };
 767
 768 void lcd_ctrl_init(void *lcdbase)
 769 {
 770         int color_depth = 24;
 771         char *vm;
 772         unsigned long val;
 773         int refresh = 60;
 774         struct fb_videomode *p = &tx51_fb_modes[0];
 775         struct fb_videomode fb_mode;
 776         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 777         int pix_fmt = 0;
 778         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 779         unsigned long di_clk_rate = 65000000;
 780
 781         if (!lcd_enabled) {
 782                 debug("LCD disabled\n");
 783                 return;
 784         }
 785
 786         if (tstc() || (wrsr & WRSR_TOUT)) {
 787                 debug("Disabling LCD\n");
 788                 lcd_enabled = 0;
 789                 setenv("splashimage", NULL);
 790                 return;
 791         }
 792
 793         karo_fdt_move_fdt();
 794         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 795
 796         vm = getenv("video_mode");
 797         if (vm == NULL) {
 798                 debug("Disabling LCD\n");
 799                 lcd_enabled = 0;
 800                 return;
 801         }
 802         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 803                 p = &fb_mode;
 804                 debug("Using video mode from FDT\n");
 805                 vm += strlen(vm);
 806                 if (fb_mode.xres > panel_info.vl_col ||
 807                         fb_mode.yres > panel_info.vl_row) {
 808                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 809                                 fb_mode.xres, fb_mode.yres,
 810                                 panel_info.vl_col, panel_info.vl_row);
 811                         lcd_enabled = 0;
 812                         return;
 813                 }
 814         }
 815         if (p->name != NULL)
 816                 debug("Trying compiled-in video modes\n");
 817         while (p->name != NULL) {
 818                 if (strcmp(p->name, vm) == 0) {
 819                         debug("Using video mode: '%s'\n", p->name);
 820                         vm += strlen(vm);
 821                         break;
 822                 }
 823                 p++;
 824         }
 825         if (*vm != '\0')
 826                 debug("Trying to decode video_mode: '%s'\n", vm);
 827         while (*vm != '\0') {
 828                 if (*vm >= '0' && *vm <= '9') {
 829                         char *end;
 830
 831                         val = simple_strtoul(vm, &end, 0);
 832                         if (end > vm) {
 833                                 if (!xres_set) {
 834                                         if (val > panel_info.vl_col)
 835                                                 val = panel_info.vl_col;
 836                                         p->xres = val;
 837                                         panel_info.vl_col = val;
 838                                         xres_set = 1;
 839                                 } else if (!yres_set) {
 840                                         if (val > panel_info.vl_row)
 841                                                 val = panel_info.vl_row;
 842                                         p->yres = val;
 843                                         panel_info.vl_row = val;
 844                                         yres_set = 1;
 845                                 } else if (!bpp_set) {
 846                                         switch (val) {
 847                                         case 8:
 848                                         case 16:
 849                                         case 24:
 850                                         case 32:
 851                                                 color_depth = val;
 852                                                 break;
 853
 854                                         default:
 855                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 856                                                         end - vm, vm, color_depth);
 857                                         }
 858                                         bpp_set = 1;
 859                                 } else if (!refresh_set) {
 860                                         refresh = val;
 861                                         refresh_set = 1;
 862                                 }
 863                         }
 864                         vm = end;
 865                 }
 866                 switch (*vm) {
 867                 case '@':
 868                         bpp_set = 1;
 869                         /* fallthru */
 870                 case '-':
 871                         yres_set = 1;
 872                         /* fallthru */
 873                 case 'x':
 874                         xres_set = 1;
 875                         /* fallthru */
 876                 case 'M':
 877                 case 'R':
 878                         vm++;
 879                         break;
 880
 881                 default:
 882                         if (!pix_fmt) {
 883                                 char *tmp;
 884
 885                                 pix_fmt = IPU_PIX_FMT_RGB24;
 886                                 tmp = strchr(vm, ':');
 887                                 if (tmp)
 888                                         vm = tmp;
 889                         }
 890                         if (*vm != '\0')
 891                                 vm++;
 892                 }
 893         }
 894         if (p->xres == 0 || p->yres == 0) {
 895                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 896                 lcd_enabled = 0;
 897                 printf("Supported video modes are:");
 898                 for (p = &tx51_fb_modes[0]; p->name != NULL; p++) {
 899                         printf(" %s", p->name);
 900                 }
 901                 printf("\n");
 902                 return;
 903         }
 904         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 905                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 906                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 907                 lcd_enabled = 0;
 908                 return;
 909         }
 910         panel_info.vl_col = p->xres;
 911         panel_info.vl_row = p->yres;
 912
 913         switch (color_depth) {
 914         case 8:
 915                 panel_info.vl_bpix = LCD_COLOR8;
 916                 break;
 917         case 16:
 918                 panel_info.vl_bpix = LCD_COLOR16;
 919                 break;
 920         default:
 921                 panel_info.vl_bpix = LCD_COLOR24;
 922         }
 923
 924         p->pixclock = KHZ2PICOS(refresh *
 925                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 926                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 927                 / 1000);
 928         debug("Pixel clock set to %lu.%03lu MHz\n",
 929                 PICOS2KHZ(p->pixclock) / 1000,
 930                 PICOS2KHZ(p->pixclock) % 1000);
 931
 932         if (p != &fb_mode) {
 933                 int ret;
 934                 char *modename = getenv("video_mode");
 935
 936                 printf("Creating new display-timing node from '%s'\n",
 937                         modename);
 938                 ret = karo_fdt_create_fb_mode(working_fdt, modename, p);
 939                 if (ret)
 940                         printf("Failed to create new display-timing node from '%s': %d\n",
 941                                 modename, ret);
 942         }
 943
 944         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 945         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 946                                         ARRAY_SIZE(stk5_lcd_pads));
 947
 948         debug("Initializing FB driver\n");
 949         if (!pix_fmt)
 950                 pix_fmt = IPU_PIX_FMT_RGB24;
 951
 952         if (karo_load_splashimage(0) == 0) {
 953                 int ret;
 954                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 955                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
 956
 957                 /* MIPI HSC clock is required for initialization */
 958                 writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
 959
 960                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3DEX;
 961
 962                 debug("Initializing LCD controller\n");
 963                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 964                 writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
 965                 if (ret) {
 966                         printf("Failed to initialize FB driver: %d\n", ret);
 967                         lcd_enabled = 0;
 968                 }
 969         } else {
 970                 debug("Skipping initialization of LCD controller\n");
 971         }
 972 }
 973 #else
 974 #define lcd_enabled 0
 975 #endif /* CONFIG_LCD */
 976
 977 static void stk5_board_init(void)
 978 {
 979         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 980         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 981 }
 982
 983 static void stk5v3_board_init(void)
 984 {
 985         stk5_board_init();
 986 }
 987
 988 static void tx51_set_cpu_clock(void)
 989 {
 990         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 991         int ret;
 992
 993         if (tstc() || (wrsr & WRSR_TOUT))
 994                 return;
 995
 996         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 997                 return;
 998
 999         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
1000         if (ret != 0) {
1001                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1002                 return;
1003         }
1004         printf("CPU clock set to %u.%03u MHz\n",
1005                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
1006                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
1007 }
1008
1009 static void tx51_init_mac(void)
1010 {
1011         u8 mac[ETH_ALEN];
1012
1013         imx_get_mac_from_fuse(0, mac);
1014         if (!is_valid_ether_addr(mac)) {
1015                 printf("No valid MAC address programmed\n");
1016                 return;
1017         }
1018
1019         eth_setenv_enetaddr("ethaddr", mac);
1020         printf("MAC addr from fuse: %pM\n", mac);
1021 }
1022
1023 int board_late_init(void)
1024 {
1025         int ret = 0;
1026         const char *baseboard;
1027
1028         tx51_set_cpu_clock();
1029         karo_fdt_move_fdt();
1030
1031         baseboard = getenv("baseboard");
1032         if (!baseboard)
1033                 goto exit;
1034
1035         if (strncmp(baseboard, "stk5", 4) == 0) {
1036                 printf("Baseboard: %s\n", baseboard);
1037                 if ((strlen(baseboard) == 4) ||
1038                         strcmp(baseboard, "stk5-v3") == 0) {
1039                         stk5v3_board_init();
1040                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1041                         printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
1042                                 baseboard);
1043                         stk5v3_board_init();
1044                 } else {
1045                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1046                                 baseboard + 4);
1047                 }
1048         } else {
1049                 printf("WARNING: Unsupported baseboard: '%s'\n",
1050                         baseboard);
1051                 ret = -EINVAL;
1052         }
1053
1054 exit:
1055         tx51_init_mac();
1056         gpio_set_value(TX51_RESET_OUT_GPIO, 1);
1057         return ret;
1058 }
1059
1060 int checkboard(void)
1061 {
1062         tx51_print_cpuinfo();
1063 #if CONFIG_NR_DRAM_BANKS > 1
1064         printf("Board: Ka-Ro TX51-8xx1 | TX51-8xx2\n");
1065 #else
1066         printf("Board: Ka-Ro TX51-8xx0\n");
1067 #endif
1068         return 0;
1069 }
1070
1071 #if defined(CONFIG_OF_BOARD_SETUP)
1072 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1073 #include <jffs2/jffs2.h>
1074 #include <mtd_node.h>
1075 struct node_info nodes[] = {
1076         { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
1077 };
1078
1079 #else
1080 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1081 #endif
1082
1083 static const char *tx51_touchpanels[] = {
1084         "ti,tsc2007",
1085         "edt,edt-ft5x06",
1086 };
1087
1088 void ft_board_setup(void *blob, bd_t *bd)
1089 {
1090         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1091         fdt_fixup_ethernet(blob);
1092
1093         karo_fdt_fixup_touchpanel(blob, tx51_touchpanels,
1094                                 ARRAY_SIZE(tx51_touchpanels));
1095         karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1096         karo_fdt_update_fb_mode(blob, getenv("video_mode"));
1097 }
1098 #endif