board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <i2c.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <video_fb.h>
  29 #include <ipu.h>
  30 #include <mxcfb.h>
  31 #include <linux/fb.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/iomux-mx53.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/arch/hab.h>
  37 #include <asm/arch/imx-regs.h>
  38 #include <asm/arch/crm_regs.h>
  39 #include <asm/arch/sys_proto.h>
  40
  41 #include "../common/karo.h"
  42
  43 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  44 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  45 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  46 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  47
  48 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  49 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  50 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  51
  52 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  53
  54 DECLARE_GLOBAL_DATA_PTR;
  55
  56 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
  57                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  58
  59 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
  60                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
  61
  62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  63 char __csf_data[0] __attribute__((section(".__csf_data")));
  64
  65 static iomux_v3_cfg_t tx53_pads[] = {
  66         /* NAND flash pads are set up in lowlevel_init.S */
  67
  68         /* UART pads */
  69 #if CONFIG_MXC_UART_BASE == UART1_BASE
  70         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  71         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  72         MX53_PAD_PATA_IORDY__UART1_RTS,
  73         MX53_PAD_PATA_RESET_B__UART1_CTS,
  74 #endif
  75 #if CONFIG_MXC_UART_BASE == UART2_BASE
  76         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  77         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  78         MX53_PAD_PATA_DIOR__UART2_RTS,
  79         MX53_PAD_PATA_INTRQ__UART2_CTS,
  80 #endif
  81 #if CONFIG_MXC_UART_BASE == UART3_BASE
  82         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  83         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  84         MX53_PAD_PATA_DA_2__UART3_RTS,
  85         MX53_PAD_PATA_DA_1__UART3_CTS,
  86 #endif
  87         /* internal I2C */
  88         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
  89         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
  90
  91         /* FEC PHY GPIO functions */
  92         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  93         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  94         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  95
  96         /* FEC functions */
  97         MX53_PAD_FEC_MDC__FEC_MDC,
  98         MX53_PAD_FEC_MDIO__FEC_MDIO,
  99         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 100         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 101         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 102         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 103         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 104         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 105         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 106         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 107 };
 108
 109 static const struct gpio tx53_gpios[] = {
 110         { TX53_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 111         { TX53_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 112         { TX53_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 113         { TX53_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 114 };
 115
 116 /*
 117  * Functions
 118  */
 119 /* placed in section '.data' to prevent overwriting relocation info
 120  * overlayed with bss
 121  */
 122 static u32 wrsr __attribute__((section(".data")));
 123
 124 #define WRSR_POR        (1 << 4)
 125 #define WRSR_TOUT       (1 << 1)
 126 #define WRSR_SFTW       (1 << 0)
 127
 128 static void print_reset_cause(void)
 129 {
 130         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 131         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 132         u32 srsr;
 133         char *dlm = "";
 134
 135         printf("Reset cause: ");
 136
 137         srsr = readl(&src_regs->srsr);
 138         wrsr = readw(wdt_base + 4);
 139
 140         if (wrsr & WRSR_POR) {
 141                 printf("%sPOR", dlm);
 142                 dlm = " | ";
 143         }
 144         if (srsr & 0x00004) {
 145                 printf("%sCSU", dlm);
 146                 dlm = " | ";
 147         }
 148         if (srsr & 0x00008) {
 149                 printf("%sIPP USER", dlm);
 150                 dlm = " | ";
 151         }
 152         if (srsr & 0x00010) {
 153                 if (wrsr & WRSR_SFTW) {
 154                         printf("%sSOFT", dlm);
 155                         dlm = " | ";
 156                 }
 157                 if (wrsr & WRSR_TOUT) {
 158                         printf("%sWDOG", dlm);
 159                         dlm = " | ";
 160                 }
 161         }
 162         if (srsr & 0x00020) {
 163                 printf("%sJTAG HIGH-Z", dlm);
 164                 dlm = " | ";
 165         }
 166         if (srsr & 0x00040) {
 167                 printf("%sJTAG SW", dlm);
 168                 dlm = " | ";
 169         }
 170         if (srsr & 0x10000) {
 171                 printf("%sWARM BOOT", dlm);
 172                 dlm = " | ";
 173         }
 174         if (dlm[0] == '\0')
 175                 printf("unknown");
 176
 177         printf("\n");
 178 }
 179
 180 #define pr_lpgr_val(v, n, b, c) do {                                    \
 181         u32 __v = ((v) >> (b)) & ((1 << (c)) - 1);                      \
 182         if (__v)                                                        \
 183                 printf(" %s=%0*x", #n, DIV_ROUND_UP(c, 4), __v);        \
 184 } while (0)
 185
 186 static inline void print_lpgr(u32 lpgr)
 187 {
 188         if (!lpgr)
 189                 return;
 190
 191         printf("LPGR=%08x:", lpgr);
 192         pr_lpgr_val(lpgr, SW_ISO, 31, 1);
 193         pr_lpgr_val(lpgr, SECONDARY_BOOT, 30, 1);
 194         pr_lpgr_val(lpgr, BLOCK_REWRITE, 29, 1);
 195         pr_lpgr_val(lpgr, WDOG_BOOT, 28, 1);
 196         pr_lpgr_val(lpgr, SBMR_SHADOW, 0, 26);
 197         printf("\n");
 198 }
 199
 200 static void tx53_print_cpuinfo(void)
 201 {
 202         u32 cpurev;
 203         struct srtc_regs *srtc_regs = (void *)SRTC_BASE_ADDR;
 204         u32 lpgr = readl(&srtc_regs->lpgr);
 205
 206         cpurev = get_cpu_rev();
 207
 208         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 209                 (cpurev & 0x000F0) >> 4,
 210                 (cpurev & 0x0000F) >> 0,
 211                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 212
 213         print_reset_cause();
 214
 215         print_lpgr(lpgr);
 216
 217         if (lpgr & (1 << 30))
 218                 printf("WARNING: U-Boot started from secondary bootstrap image\n");
 219
 220         if (lpgr) {
 221                 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 222                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
 223
 224                 writel(ccgr4 | MXC_CCM_CCGR4_SRTC(3), &ccm_regs->CCGR4);
 225                 writel(0, &srtc_regs->lpgr);
 226                 writel(ccgr4, &ccm_regs->CCGR4);
 227         }
 228 }
 229
 230 enum LTC3589_REGS {
 231         LTC3589_SCR1 = 0x07,
 232         LTC3589_SCR2 = 0x12,
 233         LTC3589_VCCR = 0x20,
 234         LTC3589_CLIRQ = 0x21,
 235         LTC3589_B1DTV1 = 0x23,
 236         LTC3589_B1DTV2 = 0x24,
 237         LTC3589_VRRCR = 0x25,
 238         LTC3589_B2DTV1 = 0x26,
 239         LTC3589_B2DTV2 = 0x27,
 240         LTC3589_B3DTV1 = 0x29,
 241         LTC3589_B3DTV2 = 0x2a,
 242         LTC3589_L2DTV1 = 0x32,
 243         LTC3589_L2DTV2 = 0x33,
 244 };
 245
 246 #define LTC3589_BnDTV1_PGOOD_MASK       (1 << 5)
 247 #define LTC3589_BnDTV1_SLEW(n)          (((n) & 3) << 6)
 248
 249 #define LTC3589_CLK_RATE_LOW            (1 << 5)
 250
 251 #define LTC3589_SCR2_PGOOD_SHUTDWN      (1 << 7)
 252
 253 #define VDD_LDO2_VAL            mV_to_regval(vout_to_vref(1325 * 10, 2))
 254 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1100 * 10, 3))
 255 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1325 * 10, 4))
 256 #define VDD_BUCK3_VAL           mV_to_regval(vout_to_vref(2500 * 10, 5))
 257
 258 #ifndef CONFIG_SYS_TX53_HWREV_2
 259 /* LDO2 vref divider */
 260 #define R1_2    180
 261 #define R2_2    191
 262 /* BUCK1 vref divider */
 263 #define R1_3    150
 264 #define R2_3    180
 265 /* BUCK2 vref divider */
 266 #define R1_4    180
 267 #define R2_4    191
 268 /* BUCK3 vref divider */
 269 #define R1_5    270
 270 #define R2_5    100
 271 #else
 272 /* no dividers on vref */
 273 #define R1_2    0
 274 #define R2_2    1
 275 #define R1_3    0
 276 #define R2_3    1
 277 #define R1_4    0
 278 #define R2_4    1
 279 #define R1_5    0
 280 #define R2_5    1
 281 #endif
 282
 283 /* calculate voltages in 10mV */
 284 #define R1(idx)                 R1_##idx
 285 #define R2(idx)                 R2_##idx
 286
 287 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
 288 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
 289
 290 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 3625) ? 3625 : (mV)) - 3625), 125)
 291 #define regval_to_mV(v)         (((v) * 125 + 3625))
 292
 293 static struct pmic_regs {
 294         enum LTC3589_REGS addr;
 295         u8 val;
 296 } ltc3589_regs[] = {
 297         { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
 298         { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */
 299
 300         { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 301         { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
 302
 303         { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 304         { LTC3589_B1DTV2, VDD_CORE_VAL, },
 305
 306         { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 307         { LTC3589_B2DTV2, VDD_SOC_VAL, },
 308
 309         { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 310         { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
 311
 312         /* Select ref 0 for all regulators and enable slew */
 313         { LTC3589_VCCR, 0x55, },
 314
 315         { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
 316 };
 317
 318 static int setup_pmic_voltages(void)
 319 {
 320         int ret;
 321         unsigned char value;
 322         int i;
 323
 324         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 325         if (ret != 0) {
 326                 printf("Failed to initialize I2C\n");
 327                 return ret;
 328         }
 329
 330         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 331         if (ret) {
 332                 printf("%s: i2c_read error: %d\n", __func__, ret);
 333                 return ret;
 334         }
 335
 336         for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
 337                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 338                                 &value, 1);
 339                 debug("Writing %02x to reg %02x (%02x)\n",
 340                         ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
 341                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 342                                 &ltc3589_regs[i].val, 1);
 343                 if (ret) {
 344                         printf("%s: failed to write PMIC register %02x: %d\n",
 345                                 __func__, ltc3589_regs[i].addr, ret);
 346                         return ret;
 347                 }
 348         }
 349         printf("VDDCORE set to %umV\n",
 350                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
 351
 352         printf("VDDSOC  set to %umV\n",
 353                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
 354         return 0;
 355 }
 356
 357 static struct {
 358         u32 max_freq;
 359         u32 mV;
 360 } tx53_core_voltages[] = {
 361         { 800000000, 1100, },
 362         { 1000000000, 1240, },
 363         { 1200000000, 1350, },
 364 };
 365
 366 int adjust_core_voltage(u32 freq)
 367 {
 368         int ret;
 369         int i;
 370
 371         printf("%s@%d\n", __func__, __LINE__);
 372
 373         for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) {
 374                 if (freq <= tx53_core_voltages[i].max_freq) {
 375                         int retries = 0;
 376                         const int max_tries = 10;
 377                         const int delay_us = 1;
 378                         u32 mV = tx53_core_voltages[i].mV;
 379                         u8 val = mV_to_regval(vout_to_vref(mV * 10, 3));
 380                         u8 v;
 381
 382                         debug("regval[%umV]=%02x\n", mV, val);
 383
 384                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
 385                                 &v, 1);
 386                         if (ret) {
 387                                 printf("%s: failed to read PMIC register %02x: %d\n",
 388                                         __func__, LTC3589_B1DTV1, ret);
 389                                 return ret;
 390                         }
 391                         debug("Changing reg %02x from %02x to %02x\n",
 392                                 LTC3589_B1DTV1, v, (v & ~0x1f) |
 393                                 mV_to_regval(vout_to_vref(mV * 10, 3)));
 394                         v &= ~0x1f;
 395                         v |= mV_to_regval(vout_to_vref(mV * 10, 3));
 396                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
 397                                         &v, 1);
 398                         if (ret) {
 399                                 printf("%s: failed to write PMIC register %02x: %d\n",
 400                                         __func__, LTC3589_B1DTV1, ret);
 401                                 return ret;
 402                         }
 403                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
 404                                         &v, 1);
 405                         if (ret) {
 406                                 printf("%s: failed to read PMIC register %02x: %d\n",
 407                                         __func__, LTC3589_VCCR, ret);
 408                                 return ret;
 409                         }
 410                         v |= 0x1;
 411                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
 412                                         &v, 1);
 413                         if (ret) {
 414                                 printf("%s: failed to write PMIC register %02x: %d\n",
 415                                         __func__, LTC3589_VCCR, ret);
 416                                 return ret;
 417                         }
 418                         for (retries = 0; retries < max_tries; retries++) {
 419                                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE,
 420                                         LTC3589_VCCR, 1, &v, 1);
 421                                 if (ret) {
 422                                         printf("%s: failed to read PMIC register %02x: %d\n",
 423                                                 __func__, LTC3589_VCCR, ret);
 424                                         return ret;
 425                                 }
 426                                 if (!(v & 1))
 427                                         break;
 428                                 udelay(delay_us);
 429                         }
 430                         if (v & 1) {
 431                                 printf("change of VDDCORE did not complete after %uµs\n",
 432                                         retries * delay_us);
 433                                 return -ETIMEDOUT;
 434                         }
 435
 436                         printf("VDDCORE set to %umV after %u loops\n",
 437                                 DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3),
 438                                         10), retries);
 439                         return 0;
 440                 }
 441         }
 442         return -EINVAL;
 443 }
 444
 445 int board_early_init_f(void)
 446 {
 447         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 448
 449         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 450         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 451
 452         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 453         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 454         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 455         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 456         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 457
 458         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 459         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 460
 461         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 462         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 463         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 464         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 465         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 466
 467         writel(0xffcf0fff, &ccm_regs->CCGR0);
 468         writel(0x000fffcf, &ccm_regs->CCGR1);
 469         writel(0x033c0000, &ccm_regs->CCGR2);
 470         writel(0x000000ff, &ccm_regs->CCGR3);
 471         writel(0x00000000, &ccm_regs->CCGR4);
 472         writel(0x00fff033, &ccm_regs->CCGR5);
 473         writel(0x0f00030f, &ccm_regs->CCGR6);
 474         writel(0xfff00000, &ccm_regs->CCGR7);
 475         writel(0x00000000, &ccm_regs->cmeor);
 476
 477         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 478
 479         return 0;
 480 }
 481
 482 int board_init(void)
 483 {
 484         int ret;
 485
 486         ret = gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 487         if (ret < 0) {
 488                 printf("Failed to request tx53_gpios: %d\n", ret);
 489         }
 490
 491         /* Address of boot parameters */
 492         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 493
 494         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 495                 if (wrsr & WRSR_TOUT)
 496                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 497                 else
 498                         printf("<CTRL-C> detected; safeboot enabled\n");
 499                 return 0;
 500         }
 501
 502         ret = setup_pmic_voltages();
 503         if (ret) {
 504                 printf("Failed to setup PMIC voltages\n");
 505                 hang();
 506         }
 507         return 0;
 508 }
 509
 510 int dram_init(void)
 511 {
 512         int ret;
 513
 514         /*
 515          * U-Boot doesn't support RAM banks with intervening holes,
 516          * so let U-Boot only know about the first bank for its
 517          * internal data structures. The size reported to Linux is
 518          * determined from the individual bank sizes.
 519          */
 520         gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, SZ_1G);
 521
 522         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 523                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 524         if (ret)
 525                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 526                         CONFIG_SYS_SDRAM_CLK, ret);
 527         else
 528                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 529                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 530                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 531                         CONFIG_SYS_SDRAM_CLK);
 532         return ret;
 533 }
 534
 535 void dram_init_banksize(void)
 536 {
 537         long total_size = gd->ram_size;
 538
 539         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 540         gd->bd->bi_dram[0].size = gd->ram_size;
 541
 542 #if CONFIG_NR_DRAM_BANKS > 1
 543         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, SZ_1G);
 544
 545         if (gd->bd->bi_dram[1].size) {
 546                 debug("Found %luMiB SDRAM in bank 2\n",
 547                         gd->bd->bi_dram[1].size / SZ_1M);
 548                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 549                 total_size += gd->bd->bi_dram[1].size;
 550         }
 551 #endif
 552         if (total_size != CONFIG_SYS_SDRAM_SIZE)
 553                 printf("WARNING: SDRAM size mismatch: %uMiB configured; %luMiB detected\n",
 554                         CONFIG_SYS_SDRAM_SIZE / SZ_1M, total_size / SZ_1M);
 555 }
 556
 557 #ifdef  CONFIG_CMD_MMC
 558 static const iomux_v3_cfg_t mmc0_pads[] = {
 559         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
 560         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
 561         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
 562         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
 563         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
 564         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
 565         /* SD1 CD */
 566         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
 567 };
 568
 569 static const iomux_v3_cfg_t mmc1_pads[] = {
 570         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
 571         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
 572         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
 573         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
 574         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
 575         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
 576         /* SD2 CD */
 577         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
 578 };
 579
 580 static struct tx53_esdhc_cfg {
 581         const iomux_v3_cfg_t *pads;
 582         int num_pads;
 583         struct fsl_esdhc_cfg cfg;
 584         int cd_gpio;
 585 } tx53_esdhc_cfg[] = {
 586         {
 587                 .pads = mmc0_pads,
 588                 .num_pads = ARRAY_SIZE(mmc0_pads),
 589                 .cfg = {
 590                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 591                         .max_bus_width = 4,
 592                 },
 593                 .cd_gpio = IMX_GPIO_NR(3, 24),
 594         },
 595         {
 596                 .pads = mmc1_pads,
 597                 .num_pads = ARRAY_SIZE(mmc1_pads),
 598                 .cfg = {
 599                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 600                         .max_bus_width = 4,
 601                 },
 602                 .cd_gpio = IMX_GPIO_NR(3, 25),
 603         },
 604 };
 605
 606 static inline struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 607 {
 608         return container_of(cfg, struct tx53_esdhc_cfg, cfg);
 609 }
 610
 611 int board_mmc_getcd(struct mmc *mmc)
 612 {
 613         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
 614
 615         if (cfg->cd_gpio < 0)
 616                 return cfg->cd_gpio;
 617
 618         debug("SD card %d is %spresent\n",
 619                 cfg - tx53_esdhc_cfg,
 620                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 621         return !gpio_get_value(cfg->cd_gpio);
 622 }
 623
 624 int board_mmc_init(bd_t *bis)
 625 {
 626         int i;
 627
 628         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
 629                 struct mmc *mmc;
 630                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
 631                 int ret;
 632
 633                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 634                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 635
 636                 ret = gpio_request_one(cfg->cd_gpio,
 637                                 GPIOFLAG_INPUT, "MMC CD");
 638                 if (ret) {
 639                         printf("Error %d requesting GPIO%d_%d\n",
 640                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 641                         continue;
 642                 }
 643
 644                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 645                 fsl_esdhc_initialize(bis, &cfg->cfg);
 646
 647                 mmc = find_mmc_device(i);
 648                 if (mmc == NULL)
 649                         continue;
 650                 if (board_mmc_getcd(mmc) > 0)
 651                         mmc_init(mmc);
 652         }
 653         return 0;
 654 }
 655 #endif /* CONFIG_CMD_MMC */
 656
 657 #ifdef CONFIG_FEC_MXC
 658
 659 #ifndef ETH_ALEN
 660 #define ETH_ALEN 6
 661 #endif
 662
 663 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 664 {
 665         int i;
 666         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 667         struct fuse_bank *bank = &iim->bank[1];
 668         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 669
 670         if (dev_id > 0)
 671                 return;
 672
 673         for (i = 0; i < ETH_ALEN; i++)
 674                 mac[i] = readl(&fuse->mac_addr[i]);
 675 }
 676
 677 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 678                         PAD_CTL_SRE_FAST)
 679 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 680 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 681
 682 int board_eth_init(bd_t *bis)
 683 {
 684         int ret;
 685
 686         /* delay at least 21ms for the PHY internal POR signal to deassert */
 687         udelay(22000);
 688
 689         /* Deassert RESET to the external phy */
 690         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 691
 692         ret = cpu_eth_init(bis);
 693         if (ret)
 694                 printf("cpu_eth_init() failed: %d\n", ret);
 695
 696         return ret;
 697 }
 698 #endif /* CONFIG_FEC_MXC */
 699
 700 enum {
 701         LED_STATE_INIT = -1,
 702         LED_STATE_OFF,
 703         LED_STATE_ON,
 704 };
 705
 706 void show_activity(int arg)
 707 {
 708         static int led_state = LED_STATE_INIT;
 709         static ulong last;
 710
 711         if (led_state == LED_STATE_INIT) {
 712                 last = get_timer(0);
 713                 gpio_set_value(TX53_LED_GPIO, 1);
 714                 led_state = LED_STATE_ON;
 715         } else {
 716                 if (get_timer(last) > CONFIG_SYS_HZ) {
 717                         last = get_timer(0);
 718                         if (led_state == LED_STATE_ON) {
 719                                 gpio_set_value(TX53_LED_GPIO, 0);
 720                         } else {
 721                                 gpio_set_value(TX53_LED_GPIO, 1);
 722                         }
 723                         led_state = 1 - led_state;
 724                 }
 725         }
 726 }
 727
 728 static const iomux_v3_cfg_t stk5_pads[] = {
 729         /* SW controlled LED on STK5 baseboard */
 730         MX53_PAD_EIM_A18__GPIO2_20,
 731
 732         /* I2C bus on DIMM pins 40/41 */
 733         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
 734         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
 735
 736         /* TSC200x PEN IRQ */
 737         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
 738
 739         /* EDT-FT5x06 Polytouch panel */
 740         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
 741         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
 742         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
 743
 744         /* USBH1 */
 745         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
 746         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
 747         /* USBOTG */
 748         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 749         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 750
 751         /* DS1339 Interrupt */
 752         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
 753 };
 754
 755 static const struct gpio stk5_gpios[] = {
 756         { TX53_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 757
 758         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 759         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 760         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 761         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 762 };
 763
 764 #ifdef CONFIG_LCD
 765 static u16 tx53_cmap[256];
 766 vidinfo_t panel_info = {
 767         /* set to max. size supported by SoC */
 768         .vl_col = 1600,
 769         .vl_row = 1200,
 770
 771         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 772         .cmap = tx53_cmap,
 773 };
 774
 775 static struct fb_videomode tx53_fb_modes[] = {
 776 #ifndef CONFIG_SYS_LVDS_IF
 777         {
 778                 /* Standard VGA timing */
 779                 .name           = "VGA",
 780                 .refresh        = 60,
 781                 .xres           = 640,
 782                 .yres           = 480,
 783                 .pixclock       = KHZ2PICOS(25175),
 784                 .left_margin    = 48,
 785                 .hsync_len      = 96,
 786                 .right_margin   = 16,
 787                 .upper_margin   = 31,
 788                 .vsync_len      = 2,
 789                 .lower_margin   = 12,
 790                 .sync           = FB_SYNC_CLK_LAT_FALL,
 791         },
 792         {
 793                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 794                  * DE high active, 115.2 mm x 86.4 mm display area
 795                  * VGA compatible timing
 796                  */
 797                 .name           = "ETV570",
 798                 .refresh        = 60,
 799                 .xres           = 640,
 800                 .yres           = 480,
 801                 .pixclock       = KHZ2PICOS(25175),
 802                 .left_margin    = 114,
 803                 .hsync_len      = 30,
 804                 .right_margin   = 16,
 805                 .upper_margin   = 32,
 806                 .vsync_len      = 3,
 807                 .lower_margin   = 10,
 808                 .sync           = FB_SYNC_CLK_LAT_FALL,
 809         },
 810         {
 811                 /* Emerging ET0350G0DH6 320 x 240 display.
 812                  * 70.08 mm x 52.56 mm display area.
 813                  */
 814                 .name           = "ET0350",
 815                 .refresh        = 60,
 816                 .xres           = 320,
 817                 .yres           = 240,
 818                 .pixclock       = KHZ2PICOS(6500),
 819                 .left_margin    = 68 - 34,
 820                 .hsync_len      = 34,
 821                 .right_margin   = 20,
 822                 .upper_margin   = 18 - 3,
 823                 .vsync_len      = 3,
 824                 .lower_margin   = 4,
 825                 .sync           = FB_SYNC_CLK_LAT_FALL,
 826         },
 827         {
 828                 /* Emerging ET0430G0DH6 480 x 272 display.
 829                  * 95.04 mm x 53.856 mm display area.
 830                  */
 831                 .name           = "ET0430",
 832                 .refresh        = 60,
 833                 .xres           = 480,
 834                 .yres           = 272,
 835                 .pixclock       = KHZ2PICOS(9000),
 836                 .left_margin    = 2,
 837                 .hsync_len      = 41,
 838                 .right_margin   = 2,
 839                 .upper_margin   = 2,
 840                 .vsync_len      = 10,
 841                 .lower_margin   = 2,
 842         },
 843         {
 844                 /* Emerging ET0500G0DH6 800 x 480 display.
 845                  * 109.6 mm x 66.4 mm display area.
 846                  */
 847                 .name           = "ET0500",
 848                 .refresh        = 60,
 849                 .xres           = 800,
 850                 .yres           = 480,
 851                 .pixclock       = KHZ2PICOS(33260),
 852                 .left_margin    = 216 - 128,
 853                 .hsync_len      = 128,
 854                 .right_margin   = 1056 - 800 - 216,
 855                 .upper_margin   = 35 - 2,
 856                 .vsync_len      = 2,
 857                 .lower_margin   = 525 - 480 - 35,
 858                 .sync           = FB_SYNC_CLK_LAT_FALL,
 859         },
 860         {
 861                 /* Emerging ETQ570G0DH6 320 x 240 display.
 862                  * 115.2 mm x 86.4 mm display area.
 863                  */
 864                 .name           = "ETQ570",
 865                 .refresh        = 60,
 866                 .xres           = 320,
 867                 .yres           = 240,
 868                 .pixclock       = KHZ2PICOS(6400),
 869                 .left_margin    = 38,
 870                 .hsync_len      = 30,
 871                 .right_margin   = 30,
 872                 .upper_margin   = 16, /* 15 according to datasheet */
 873                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 874                 .lower_margin   = 4, /* 4.5 according to datasheet */
 875                 .sync           = FB_SYNC_CLK_LAT_FALL,
 876         },
 877         {
 878                 /* Emerging ET0700G0DH6 800 x 480 display.
 879                  * 152.4 mm x 91.44 mm display area.
 880                  */
 881                 .name           = "ET0700",
 882                 .refresh        = 60,
 883                 .xres           = 800,
 884                 .yres           = 480,
 885                 .pixclock       = KHZ2PICOS(33260),
 886                 .left_margin    = 216 - 128,
 887                 .hsync_len      = 128,
 888                 .right_margin   = 1056 - 800 - 216,
 889                 .upper_margin   = 35 - 2,
 890                 .vsync_len      = 2,
 891                 .lower_margin   = 525 - 480 - 35,
 892                 .sync           = FB_SYNC_CLK_LAT_FALL,
 893         },
 894 #else
 895         {
 896                 /* HannStar HSD100PXN1
 897                  * 202.7m mm x 152.06 mm display area.
 898                  */
 899                 .name           = "HSD100PXN1",
 900                 .refresh        = 60,
 901                 .xres           = 1024,
 902                 .yres           = 768,
 903                 .pixclock       = KHZ2PICOS(65000),
 904                 .left_margin    = 0,
 905                 .hsync_len      = 0,
 906                 .right_margin   = 320,
 907                 .upper_margin   = 0,
 908                 .vsync_len      = 0,
 909                 .lower_margin   = 38,
 910                 .sync           = FB_SYNC_CLK_LAT_FALL,
 911         },
 912 #endif
 913         {
 914                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 915                 .refresh        = 60,
 916                 .left_margin    = 48,
 917                 .hsync_len      = 96,
 918                 .right_margin   = 16,
 919                 .upper_margin   = 31,
 920                 .vsync_len      = 2,
 921                 .lower_margin   = 12,
 922                 .sync           = FB_SYNC_CLK_LAT_FALL,
 923         },
 924 };
 925
 926 static int lcd_enabled = 1;
 927 static int lcd_bl_polarity;
 928
 929 static int lcd_backlight_polarity(void)
 930 {
 931         return lcd_bl_polarity;
 932 }
 933
 934 void lcd_enable(void)
 935 {
 936         /* HACK ALERT:
 937          * global variable from common/lcd.c
 938          * Set to 0 here to prevent messages from going to LCD
 939          * rather than serial console
 940          */
 941         lcd_is_enabled = 0;
 942
 943         if (lcd_enabled) {
 944                 karo_load_splashimage(1);
 945
 946                 debug("Switching LCD on\n");
 947                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 948                 udelay(100);
 949                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 950                 udelay(300000);
 951                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
 952                         lcd_backlight_polarity());
 953         }
 954 }
 955
 956 void lcd_disable(void)
 957 {
 958         if (lcd_enabled) {
 959                 printf("Disabling LCD\n");
 960                 ipuv3_fb_shutdown();
 961         }
 962 }
 963
 964 void lcd_panel_disable(void)
 965 {
 966         if (lcd_enabled) {
 967                 debug("Switching LCD off\n");
 968                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
 969                         !lcd_backlight_polarity());
 970                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
 971                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
 972         }
 973 }
 974
 975 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 976         /* LCD RESET */
 977         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
 978         /* LCD POWER_ENABLE */
 979         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
 980         /* LCD Backlight (PWM) */
 981         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
 982
 983         /* Display */
 984 #ifndef CONFIG_SYS_LVDS_IF
 985         /* LCD option */
 986         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 987         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 988         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 989         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 990         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 991         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 992         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 993         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 994         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 995         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 996         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 997         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 998         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 999         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
1000         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
1001         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
1002         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
1003         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
1004         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
1005         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
1006         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
1007         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
1008         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
1009         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
1010         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
1011         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
1012         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
1013         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
1014 #else
1015         /* LVDS option */
1016         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
1017         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
1018         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
1019         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
1020         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
1021         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
1022         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
1023         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
1024         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
1025         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
1026 #endif
1027 };
1028
1029 static const struct gpio stk5_lcd_gpios[] = {
1030         { TX53_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1031         { TX53_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1032         { TX53_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1033 };
1034
1035 void lcd_ctrl_init(void *lcdbase)
1036 {
1037         int color_depth = 24;
1038         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1039         const char *vm;
1040         unsigned long val;
1041         int refresh = 60;
1042         struct fb_videomode *p = &tx53_fb_modes[0];
1043         struct fb_videomode fb_mode;
1044         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1045         int pix_fmt;
1046         int lcd_bus_width;
1047         ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
1048         unsigned long di_clk_rate = 65000000;
1049
1050         if (!lcd_enabled) {
1051                 debug("LCD disabled\n");
1052                 return;
1053         }
1054
1055         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1056                 debug("Disabling LCD\n");
1057                 lcd_enabled = 0;
1058                 setenv("splashimage", NULL);
1059                 return;
1060         }
1061
1062         karo_fdt_move_fdt();
1063
1064         if (video_mode == NULL) {
1065                 debug("Disabling LCD\n");
1066                 lcd_enabled = 0;
1067                 return;
1068         }
1069
1070         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1071         vm = video_mode;
1072         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1073                 p = &fb_mode;
1074                 debug("Using video mode from FDT\n");
1075                 vm += strlen(vm);
1076                 if (fb_mode.xres > panel_info.vl_col ||
1077                         fb_mode.yres > panel_info.vl_row) {
1078                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1079                                 fb_mode.xres, fb_mode.yres,
1080                                 panel_info.vl_col, panel_info.vl_row);
1081                         lcd_enabled = 0;
1082                         return;
1083                 }
1084         }
1085         if (p->name != NULL)
1086                 debug("Trying compiled-in video modes\n");
1087         while (p->name != NULL) {
1088                 if (strcmp(p->name, vm) == 0) {
1089                         debug("Using video mode: '%s'\n", p->name);
1090                         vm += strlen(vm);
1091                         break;
1092                 }
1093                 p++;
1094         }
1095         if (*vm != '\0')
1096                 debug("Trying to decode video_mode: '%s'\n", vm);
1097         while (*vm != '\0') {
1098                 if (*vm >= '0' && *vm <= '9') {
1099                         char *end;
1100
1101                         val = simple_strtoul(vm, &end, 0);
1102                         if (end > vm) {
1103                                 if (!xres_set) {
1104                                         if (val > panel_info.vl_col)
1105                                                 val = panel_info.vl_col;
1106                                         p->xres = val;
1107                                         panel_info.vl_col = val;
1108                                         xres_set = 1;
1109                                 } else if (!yres_set) {
1110                                         if (val > panel_info.vl_row)
1111                                                 val = panel_info.vl_row;
1112                                         p->yres = val;
1113                                         panel_info.vl_row = val;
1114                                         yres_set = 1;
1115                                 } else if (!bpp_set) {
1116                                         switch (val) {
1117                                         case 32:
1118                                         case 24:
1119                                                 if (is_lvds())
1120                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1121                                                 /* fallthru */
1122                                         case 16:
1123                                         case 8:
1124                                                 color_depth = val;
1125                                                 break;
1126
1127                                         case 18:
1128                                                 if (is_lvds()) {
1129                                                         color_depth = val;
1130                                                         break;
1131                                                 }
1132                                                 /* fallthru */
1133                                         default:
1134                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1135                                                         end - vm, vm, color_depth);
1136                                         }
1137                                         bpp_set = 1;
1138                                 } else if (!refresh_set) {
1139                                         refresh = val;
1140                                         refresh_set = 1;
1141                                 }
1142                         }
1143                         vm = end;
1144                 }
1145                 switch (*vm) {
1146                 case '@':
1147                         bpp_set = 1;
1148                         /* fallthru */
1149                 case '-':
1150                         yres_set = 1;
1151                         /* fallthru */
1152                 case 'x':
1153                         xres_set = 1;
1154                         /* fallthru */
1155                 case 'M':
1156                 case 'R':
1157                         vm++;
1158                         break;
1159
1160                 default:
1161                         if (*vm != '\0')
1162                                 vm++;
1163                 }
1164         }
1165         if (p->xres == 0 || p->yres == 0) {
1166                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1167                 lcd_enabled = 0;
1168                 printf("Supported video modes are:");
1169                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
1170                         printf(" %s", p->name);
1171                 }
1172                 printf("\n");
1173                 return;
1174         }
1175         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1176                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1177                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1178                 lcd_enabled = 0;
1179                 return;
1180         }
1181         panel_info.vl_col = p->xres;
1182         panel_info.vl_row = p->yres;
1183
1184         switch (color_depth) {
1185         case 8:
1186                 panel_info.vl_bpix = LCD_COLOR8;
1187                 break;
1188         case 16:
1189                 panel_info.vl_bpix = LCD_COLOR16;
1190                 break;
1191         default:
1192                 panel_info.vl_bpix = LCD_COLOR32;
1193         }
1194
1195         p->pixclock = KHZ2PICOS(refresh *
1196                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1197                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1198                                 1000);
1199         debug("Pixel clock set to %lu.%03lu MHz\n",
1200                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1201
1202         if (p != &fb_mode) {
1203                 int ret;
1204
1205                 debug("Creating new display-timing node from '%s'\n",
1206                         video_mode);
1207                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1208                 if (ret)
1209                         printf("Failed to create new display-timing node from '%s': %d\n",
1210                                 video_mode, ret);
1211         }
1212
1213         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1214         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1215                                         ARRAY_SIZE(stk5_lcd_pads));
1216
1217         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1218         switch (lcd_bus_width) {
1219         case 24:
1220                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1221                 break;
1222
1223         case 18:
1224                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1225                 break;
1226
1227         case 16:
1228                 if (!is_lvds()) {
1229                         pix_fmt = IPU_PIX_FMT_RGB565;
1230                         break;
1231                 }
1232                 /* fallthru */
1233         default:
1234                 lcd_enabled = 0;
1235                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1236                         lcd_bus_width);
1237                 return;
1238         }
1239         if (is_lvds()) {
1240                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1241                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1242                 uint32_t gpr2;
1243
1244                 if (lvds_chan_mask == 0) {
1245                         printf("No LVDS channel active\n");
1246                         lcd_enabled = 0;
1247                         return;
1248                 }
1249
1250                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1251                 if (lcd_bus_width == 24)
1252                         gpr2 |= (1 << 5) | (1 << 7);
1253                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1254                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1255                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1256                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1257         }
1258         if (karo_load_splashimage(0) == 0) {
1259                 int ret;
1260
1261                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1262
1263                 debug("Initializing LCD controller\n");
1264                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1265                 if (ret) {
1266                         printf("Failed to initialize FB driver: %d\n", ret);
1267                         lcd_enabled = 0;
1268                 }
1269         } else {
1270                 debug("Skipping initialization of LCD controller\n");
1271         }
1272 }
1273 #else
1274 #define lcd_enabled 0
1275 #endif /* CONFIG_LCD */
1276
1277 static void stk5_board_init(void)
1278 {
1279         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1280         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1281 }
1282
1283 static void stk5v3_board_init(void)
1284 {
1285         stk5_board_init();
1286 }
1287
1288 static void stk5v5_board_init(void)
1289 {
1290         stk5_board_init();
1291
1292         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1293                         "Flexcan Transceiver");
1294         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1295 }
1296
1297 static void tx53_set_cpu_clock(void)
1298 {
1299         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1300
1301         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1302                 return;
1303
1304         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1305                 printf("%s detected; skipping cpu clock change\n",
1306                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1307                 return;
1308         }
1309
1310         if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1311                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1312                 printf("CPU clock set to %lu.%03lu MHz\n",
1313                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1314         } else {
1315                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1316         }
1317 }
1318
1319 static void tx53_init_mac(void)
1320 {
1321         u8 mac[ETH_ALEN];
1322
1323         imx_get_mac_from_fuse(0, mac);
1324         if (!is_valid_ethaddr(mac)) {
1325                 printf("No valid MAC address programmed\n");
1326                 return;
1327         }
1328
1329         printf("MAC addr from fuse: %pM\n", mac);
1330         eth_setenv_enetaddr("ethaddr", mac);
1331 }
1332
1333 int board_late_init(void)
1334 {
1335         const char *baseboard;
1336
1337         env_cleanup();
1338
1339         tx53_set_cpu_clock();
1340
1341         if (had_ctrlc())
1342                 setenv_ulong("safeboot", 1);
1343         else if (wrsr & WRSR_TOUT)
1344                 setenv_ulong("wdreset", 1);
1345         else
1346                 karo_fdt_move_fdt();
1347
1348         baseboard = getenv("baseboard");
1349         if (!baseboard)
1350                 goto exit;
1351
1352         printf("Baseboard: %s\n", baseboard);
1353
1354         if (strncmp(baseboard, "stk5", 4) == 0) {
1355                 if ((strlen(baseboard) == 4) ||
1356                         strcmp(baseboard, "stk5-v3") == 0) {
1357                         stk5v3_board_init();
1358                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1359                         const char *otg_mode = getenv("otg_mode");
1360
1361                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1362                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1363                                         otg_mode, baseboard);
1364                                 setenv("otg_mode", "none");
1365                         }
1366                         stk5v5_board_init();
1367                 } else {
1368                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1369                                 baseboard + 4);
1370                 }
1371         } else {
1372                 printf("WARNING: Unsupported baseboard: '%s'\n",
1373                         baseboard);
1374                 if (!had_ctrlc())
1375                         return -EINVAL;
1376         }
1377
1378 exit:
1379         tx53_init_mac();
1380
1381         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1382         clear_ctrlc();
1383
1384         get_hab_status();
1385
1386         return 0;
1387 }
1388
1389 int checkboard(void)
1390 {
1391         tx53_print_cpuinfo();
1392 #if CONFIG_SYS_SDRAM_SIZE < SZ_1G
1393         printf("Board: Ka-Ro TX53-8%d3%c\n",
1394                 is_lvds(), '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1395 #elif CONFIG_SYS_SDRAM_SIZE < SZ_2G
1396         printf("Board: Ka-Ro TX53-1%d3%c\n",
1397                 is_lvds() + 2, '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1398 #else
1399         printf("Board: Ka-Ro TX53-123%c\n",
1400                 '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1401 #endif
1402         return 0;
1403 }
1404
1405 #if defined(CONFIG_OF_BOARD_SETUP)
1406 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1407 #include <jffs2/jffs2.h>
1408 #include <mtd_node.h>
1409 static struct node_info nodes[] = {
1410         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1411 };
1412 #else
1413 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1414 #endif
1415
1416 #ifdef CONFIG_SYS_TX53_HWREV_2
1417 static void tx53_fixup_rtc(void *blob)
1418 {
1419         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1420         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1421 }
1422 #else
1423 static inline void tx53_fixup_rtc(void *blob)
1424 {
1425 }
1426 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1427
1428 static const char *tx53_touchpanels[] = {
1429         "ti,tsc2007",
1430         "edt,edt-ft5x06",
1431         "eeti,egalax_ts",
1432 };
1433
1434 int ft_board_setup(void *blob, bd_t *bd)
1435 {
1436         const char *baseboard = getenv("baseboard");
1437         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1438         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1439         int ret;
1440
1441         ret = fdt_increase_size(blob, 4096);
1442         if (ret) {
1443                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1444                 return ret;
1445         }
1446         if (stk5_v5)
1447                 karo_fdt_enable_node(blob, "stk5led", 0);
1448
1449         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1450
1451         karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
1452                                 ARRAY_SIZE(tx53_touchpanels));
1453         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1454         karo_fdt_fixup_flexcan(blob, stk5_v5);
1455         tx53_fixup_rtc(blob);
1456         karo_fdt_update_fb_mode(blob, video_mode);
1457
1458         return 0;
1459 }
1460 #endif /* CONFIG_OF_BOARD_SETUP */