board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <i2c.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <video_fb.h>
  29 #include <ipu.h>
  30 #include <mxcfb.h>
  31 #include <linux/fb.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/iomux-mx53.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/arch/imx-regs.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <asm/arch/sys_proto.h>
  39
  40 #include "../common/karo.h"
  41
  42 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  43 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  44 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  45 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  46
  47 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  48 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  50
  51 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
  56                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  57
  58 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
  59                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
  60
  61 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  62
  63 static iomux_v3_cfg_t tx53_pads[] = {
  64         /* NAND flash pads are set up in lowlevel_init.S */
  65
  66         /* UART pads */
  67 #if CONFIG_MXC_UART_BASE == UART1_BASE
  68         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  69         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  70         MX53_PAD_PATA_IORDY__UART1_RTS,
  71         MX53_PAD_PATA_RESET_B__UART1_CTS,
  72 #endif
  73 #if CONFIG_MXC_UART_BASE == UART2_BASE
  74         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  75         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  76         MX53_PAD_PATA_DIOR__UART2_RTS,
  77         MX53_PAD_PATA_INTRQ__UART2_CTS,
  78 #endif
  79 #if CONFIG_MXC_UART_BASE == UART3_BASE
  80         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  81         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  82         MX53_PAD_PATA_DA_2__UART3_RTS,
  83         MX53_PAD_PATA_DA_1__UART3_CTS,
  84 #endif
  85         /* internal I2C */
  86         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
  87         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
  88
  89         /* FEC PHY GPIO functions */
  90         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  91         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  92         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  93
  94         /* FEC functions */
  95         MX53_PAD_FEC_MDC__FEC_MDC,
  96         MX53_PAD_FEC_MDIO__FEC_MDIO,
  97         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  98         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  99         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 100         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 101         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 102         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 103         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 104         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 105 };
 106
 107 static const struct gpio tx53_gpios[] = {
 108         { TX53_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 109         { TX53_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 110         { TX53_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 111         { TX53_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 112 };
 113
 114 /*
 115  * Functions
 116  */
 117 /* placed in section '.data' to prevent overwriting relocation info
 118  * overlayed with bss
 119  */
 120 static u32 wrsr __attribute__((section(".data")));
 121
 122 #define WRSR_POR        (1 << 4)
 123 #define WRSR_TOUT       (1 << 1)
 124 #define WRSR_SFTW       (1 << 0)
 125
 126 static void print_reset_cause(void)
 127 {
 128         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 129         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 130         u32 srsr;
 131         char *dlm = "";
 132
 133         printf("Reset cause: ");
 134
 135         srsr = readl(&src_regs->srsr);
 136         wrsr = readw(wdt_base + 4);
 137
 138         if (wrsr & WRSR_POR) {
 139                 printf("%sPOR", dlm);
 140                 dlm = " | ";
 141         }
 142         if (srsr & 0x00004) {
 143                 printf("%sCSU", dlm);
 144                 dlm = " | ";
 145         }
 146         if (srsr & 0x00008) {
 147                 printf("%sIPP USER", dlm);
 148                 dlm = " | ";
 149         }
 150         if (srsr & 0x00010) {
 151                 if (wrsr & WRSR_SFTW) {
 152                         printf("%sSOFT", dlm);
 153                         dlm = " | ";
 154                 }
 155                 if (wrsr & WRSR_TOUT) {
 156                         printf("%sWDOG", dlm);
 157                         dlm = " | ";
 158                 }
 159         }
 160         if (srsr & 0x00020) {
 161                 printf("%sJTAG HIGH-Z", dlm);
 162                 dlm = " | ";
 163         }
 164         if (srsr & 0x00040) {
 165                 printf("%sJTAG SW", dlm);
 166                 dlm = " | ";
 167         }
 168         if (srsr & 0x10000) {
 169                 printf("%sWARM BOOT", dlm);
 170                 dlm = " | ";
 171         }
 172         if (dlm[0] == '\0')
 173                 printf("unknown");
 174
 175         printf("\n");
 176 }
 177
 178 #define pr_lpgr_val(v, n, b, c) do {                                    \
 179         u32 __v = ((v) >> (b)) & ((1 << (c)) - 1);                      \
 180         if (__v)                                                        \
 181                 printf(" %s=%0*x", #n, DIV_ROUND_UP(c, 4), __v);        \
 182 } while (0)
 183
 184 static inline void print_lpgr(u32 lpgr)
 185 {
 186         if (!lpgr)
 187                 return;
 188
 189         printf("LPGR=%08x:", lpgr);
 190         pr_lpgr_val(lpgr, SW_ISO, 31, 1);
 191         pr_lpgr_val(lpgr, SECONDARY_BOOT, 30, 1);
 192         pr_lpgr_val(lpgr, BLOCK_REWRITE, 29, 1);
 193         pr_lpgr_val(lpgr, WDOG_BOOT, 28, 1);
 194         pr_lpgr_val(lpgr, SBMR_SHADOW, 0, 26);
 195         printf("\n");
 196 }
 197
 198 static void tx53_print_cpuinfo(void)
 199 {
 200         u32 cpurev;
 201         struct srtc_regs *srtc_regs = (void *)SRTC_BASE_ADDR;
 202         u32 lpgr = readl(&srtc_regs->lpgr);
 203
 204         cpurev = get_cpu_rev();
 205
 206         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 207                 (cpurev & 0x000F0) >> 4,
 208                 (cpurev & 0x0000F) >> 0,
 209                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 210
 211         print_reset_cause();
 212
 213         print_lpgr(lpgr);
 214
 215         if (lpgr & (1 << 30))
 216                 printf("WARNING: U-Boot started from secondary bootstrap image\n");
 217
 218         if (lpgr) {
 219                 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 220                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
 221
 222                 writel(ccgr4 | MXC_CCM_CCGR4_SRTC(3), &ccm_regs->CCGR4);
 223                 writel(0, &srtc_regs->lpgr);
 224                 writel(ccgr4, &ccm_regs->CCGR4);
 225         }
 226 }
 227
 228 enum LTC3589_REGS {
 229         LTC3589_SCR1 = 0x07,
 230         LTC3589_SCR2 = 0x12,
 231         LTC3589_VCCR = 0x20,
 232         LTC3589_CLIRQ = 0x21,
 233         LTC3589_B1DTV1 = 0x23,
 234         LTC3589_B1DTV2 = 0x24,
 235         LTC3589_VRRCR = 0x25,
 236         LTC3589_B2DTV1 = 0x26,
 237         LTC3589_B2DTV2 = 0x27,
 238         LTC3589_B3DTV1 = 0x29,
 239         LTC3589_B3DTV2 = 0x2a,
 240         LTC3589_L2DTV1 = 0x32,
 241         LTC3589_L2DTV2 = 0x33,
 242 };
 243
 244 #define LTC3589_BnDTV1_PGOOD_MASK       (1 << 5)
 245 #define LTC3589_BnDTV1_SLEW(n)          (((n) & 3) << 6)
 246
 247 #define LTC3589_CLK_RATE_LOW            (1 << 5)
 248
 249 #define LTC3589_SCR2_PGOOD_SHUTDWN      (1 << 7)
 250
 251 #define VDD_LDO2_VAL            mV_to_regval(vout_to_vref(1325 * 10, 2))
 252 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1100 * 10, 3))
 253 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1325 * 10, 4))
 254 #define VDD_BUCK3_VAL           mV_to_regval(vout_to_vref(2500 * 10, 5))
 255
 256 #ifndef CONFIG_SYS_TX53_HWREV_2
 257 /* LDO2 vref divider */
 258 #define R1_2    180
 259 #define R2_2    191
 260 /* BUCK1 vref divider */
 261 #define R1_3    150
 262 #define R2_3    180
 263 /* BUCK2 vref divider */
 264 #define R1_4    180
 265 #define R2_4    191
 266 /* BUCK3 vref divider */
 267 #define R1_5    270
 268 #define R2_5    100
 269 #else
 270 /* no dividers on vref */
 271 #define R1_2    0
 272 #define R2_2    1
 273 #define R1_3    0
 274 #define R2_3    1
 275 #define R1_4    0
 276 #define R2_4    1
 277 #define R1_5    0
 278 #define R2_5    1
 279 #endif
 280
 281 /* calculate voltages in 10mV */
 282 #define R1(idx)                 R1_##idx
 283 #define R2(idx)                 R2_##idx
 284
 285 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
 286 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
 287
 288 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 3625) ? 3625 : (mV)) - 3625), 125)
 289 #define regval_to_mV(v)         (((v) * 125 + 3625))
 290
 291 static struct pmic_regs {
 292         enum LTC3589_REGS addr;
 293         u8 val;
 294 } ltc3589_regs[] = {
 295         { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
 296         { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */
 297
 298         { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 299         { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
 300
 301         { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 302         { LTC3589_B1DTV2, VDD_CORE_VAL, },
 303
 304         { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 305         { LTC3589_B2DTV2, VDD_SOC_VAL, },
 306
 307         { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
 308         { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
 309
 310         /* Select ref 0 for all regulators and enable slew */
 311         { LTC3589_VCCR, 0x55, },
 312
 313         { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
 314 };
 315
 316 static int setup_pmic_voltages(void)
 317 {
 318         int ret;
 319         unsigned char value;
 320         int i;
 321
 322         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 323         if (ret != 0) {
 324                 printf("Failed to initialize I2C\n");
 325                 return ret;
 326         }
 327
 328         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 329         if (ret) {
 330                 printf("%s: i2c_read error: %d\n", __func__, ret);
 331                 return ret;
 332         }
 333
 334         for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
 335                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 336                                 &value, 1);
 337                 debug("Writing %02x to reg %02x (%02x)\n",
 338                         ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
 339                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 340                                 &ltc3589_regs[i].val, 1);
 341                 if (ret) {
 342                         printf("%s: failed to write PMIC register %02x: %d\n",
 343                                 __func__, ltc3589_regs[i].addr, ret);
 344                         return ret;
 345                 }
 346         }
 347         printf("VDDCORE set to %umV\n",
 348                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
 349
 350         printf("VDDSOC  set to %umV\n",
 351                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
 352         return 0;
 353 }
 354
 355 static struct {
 356         u32 max_freq;
 357         u32 mV;
 358 } tx53_core_voltages[] = {
 359         { 800000000, 1100, },
 360         { 1000000000, 1240, },
 361         { 1200000000, 1350, },
 362 };
 363
 364 int adjust_core_voltage(u32 freq)
 365 {
 366         int ret;
 367         int i;
 368
 369         printf("%s@%d\n", __func__, __LINE__);
 370
 371         for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) {
 372                 if (freq <= tx53_core_voltages[i].max_freq) {
 373                         int retries = 0;
 374                         const int max_tries = 10;
 375                         const int delay_us = 1;
 376                         u32 mV = tx53_core_voltages[i].mV;
 377                         u8 val = mV_to_regval(vout_to_vref(mV * 10, 3));
 378                         u8 v;
 379
 380                         debug("regval[%umV]=%02x\n", mV, val);
 381
 382                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
 383                                 &v, 1);
 384                         if (ret) {
 385                                 printf("%s: failed to read PMIC register %02x: %d\n",
 386                                         __func__, LTC3589_B1DTV1, ret);
 387                                 return ret;
 388                         }
 389                         debug("Changing reg %02x from %02x to %02x\n",
 390                                 LTC3589_B1DTV1, v, (v & ~0x1f) |
 391                                 mV_to_regval(vout_to_vref(mV * 10, 3)));
 392                         v &= ~0x1f;
 393                         v |= mV_to_regval(vout_to_vref(mV * 10, 3));
 394                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
 395                                         &v, 1);
 396                         if (ret) {
 397                                 printf("%s: failed to write PMIC register %02x: %d\n",
 398                                         __func__, LTC3589_B1DTV1, ret);
 399                                 return ret;
 400                         }
 401                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
 402                                         &v, 1);
 403                         if (ret) {
 404                                 printf("%s: failed to read PMIC register %02x: %d\n",
 405                                         __func__, LTC3589_VCCR, ret);
 406                                 return ret;
 407                         }
 408                         v |= 0x1;
 409                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
 410                                         &v, 1);
 411                         if (ret) {
 412                                 printf("%s: failed to write PMIC register %02x: %d\n",
 413                                         __func__, LTC3589_VCCR, ret);
 414                                 return ret;
 415                         }
 416                         for (retries = 0; retries < max_tries; retries++) {
 417                                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE,
 418                                         LTC3589_VCCR, 1, &v, 1);
 419                                 if (ret) {
 420                                         printf("%s: failed to read PMIC register %02x: %d\n",
 421                                                 __func__, LTC3589_VCCR, ret);
 422                                         return ret;
 423                                 }
 424                                 if (!(v & 1))
 425                                         break;
 426                                 udelay(delay_us);
 427                         }
 428                         if (v & 1) {
 429                                 printf("change of VDDCORE did not complete after %uµs\n",
 430                                         retries * delay_us);
 431                                 return -ETIMEDOUT;
 432                         }
 433
 434                         printf("VDDCORE set to %umV after %u loops\n",
 435                                 DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3),
 436                                         10), retries);
 437                         return 0;
 438                 }
 439         }
 440         return -EINVAL;
 441 }
 442
 443 int board_early_init_f(void)
 444 {
 445         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 446
 447         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 448         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 449
 450         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 451         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 452         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 453         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 454         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 455
 456         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 457         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 458
 459         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 460         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 461         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 462         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 463         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 464
 465         writel(0xffcf0fff, &ccm_regs->CCGR0);
 466         writel(0x000fffcf, &ccm_regs->CCGR1);
 467         writel(0x033c0000, &ccm_regs->CCGR2);
 468         writel(0x000000ff, &ccm_regs->CCGR3);
 469         writel(0x00000000, &ccm_regs->CCGR4);
 470         writel(0x00fff033, &ccm_regs->CCGR5);
 471         writel(0x0f00030f, &ccm_regs->CCGR6);
 472         writel(0xfff00000, &ccm_regs->CCGR7);
 473         writel(0x00000000, &ccm_regs->cmeor);
 474
 475         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 476
 477         return 0;
 478 }
 479
 480 int board_init(void)
 481 {
 482         int ret;
 483
 484         ret = gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 485         if (ret < 0) {
 486                 printf("Failed to request tx53_gpios: %d\n", ret);
 487         }
 488
 489         /* Address of boot parameters */
 490         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 491
 492         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 493                 if (wrsr & WRSR_TOUT)
 494                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 495                 else
 496                         printf("<CTRL-C> detected; safeboot enabled\n");
 497                 return 1;
 498         }
 499
 500         ret = setup_pmic_voltages();
 501         if (ret) {
 502                 printf("Failed to setup PMIC voltages\n");
 503                 hang();
 504         }
 505         return 0;
 506 }
 507
 508 int dram_init(void)
 509 {
 510         int ret;
 511
 512         /*
 513          * U-Boot doesn't support RAM banks with intervening holes,
 514          * so let U-Boot only know about the first bank for its
 515          * internal data structures. The size reported to Linux is
 516          * determined from the individual bank sizes.
 517          */
 518         gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, SZ_1G);
 519
 520         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 521                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 522         if (ret)
 523                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 524                         CONFIG_SYS_SDRAM_CLK, ret);
 525         else
 526                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 527                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 528                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 529                         CONFIG_SYS_SDRAM_CLK);
 530         return ret;
 531 }
 532
 533 void dram_init_banksize(void)
 534 {
 535         long total_size = gd->ram_size;
 536
 537         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 538         gd->bd->bi_dram[0].size = gd->ram_size;
 539
 540 #if CONFIG_NR_DRAM_BANKS > 1
 541         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, SZ_1G);
 542
 543         if (gd->bd->bi_dram[1].size) {
 544                 debug("Found %luMiB SDRAM in bank 2\n",
 545                         gd->bd->bi_dram[1].size / SZ_1M);
 546                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 547                 total_size += gd->bd->bi_dram[1].size;
 548         }
 549 #endif
 550         if (total_size != CONFIG_SYS_SDRAM_SIZE)
 551                 printf("WARNING: SDRAM size mismatch: %uMiB configured; %luMiB detected\n",
 552                         CONFIG_SYS_SDRAM_SIZE / SZ_1M, total_size / SZ_1M);
 553 }
 554
 555 #ifdef  CONFIG_CMD_MMC
 556 static const iomux_v3_cfg_t mmc0_pads[] = {
 557         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
 558         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
 559         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
 560         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
 561         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
 562         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
 563         /* SD1 CD */
 564         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
 565 };
 566
 567 static const iomux_v3_cfg_t mmc1_pads[] = {
 568         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
 569         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
 570         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
 571         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
 572         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
 573         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
 574         /* SD2 CD */
 575         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
 576 };
 577
 578 static struct tx53_esdhc_cfg {
 579         const iomux_v3_cfg_t *pads;
 580         int num_pads;
 581         struct fsl_esdhc_cfg cfg;
 582         int cd_gpio;
 583 } tx53_esdhc_cfg[] = {
 584         {
 585                 .pads = mmc0_pads,
 586                 .num_pads = ARRAY_SIZE(mmc0_pads),
 587                 .cfg = {
 588                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 589                         .max_bus_width = 4,
 590                 },
 591                 .cd_gpio = IMX_GPIO_NR(3, 24),
 592         },
 593         {
 594                 .pads = mmc1_pads,
 595                 .num_pads = ARRAY_SIZE(mmc1_pads),
 596                 .cfg = {
 597                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 598                         .max_bus_width = 4,
 599                 },
 600                 .cd_gpio = IMX_GPIO_NR(3, 25),
 601         },
 602 };
 603
 604 static inline struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 605 {
 606         return container_of(cfg, struct tx53_esdhc_cfg, cfg);
 607 }
 608
 609 int board_mmc_getcd(struct mmc *mmc)
 610 {
 611         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
 612
 613         if (cfg->cd_gpio < 0)
 614                 return cfg->cd_gpio;
 615
 616         debug("SD card %d is %spresent\n",
 617                 cfg - tx53_esdhc_cfg,
 618                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 619         return !gpio_get_value(cfg->cd_gpio);
 620 }
 621
 622 int board_mmc_init(bd_t *bis)
 623 {
 624         int i;
 625
 626         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
 627                 struct mmc *mmc;
 628                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
 629                 int ret;
 630
 631                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 632                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 633
 634                 ret = gpio_request_one(cfg->cd_gpio,
 635                                 GPIOFLAG_INPUT, "MMC CD");
 636                 if (ret) {
 637                         printf("Error %d requesting GPIO%d_%d\n",
 638                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 639                         continue;
 640                 }
 641
 642                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 643                 fsl_esdhc_initialize(bis, &cfg->cfg);
 644
 645                 mmc = find_mmc_device(i);
 646                 if (mmc == NULL)
 647                         continue;
 648                 if (board_mmc_getcd(mmc) > 0)
 649                         mmc_init(mmc);
 650         }
 651         return 0;
 652 }
 653 #endif /* CONFIG_CMD_MMC */
 654
 655 #ifdef CONFIG_FEC_MXC
 656
 657 #ifndef ETH_ALEN
 658 #define ETH_ALEN 6
 659 #endif
 660
 661 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 662 {
 663         int i;
 664         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 665         struct fuse_bank *bank = &iim->bank[1];
 666         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 667
 668         if (dev_id > 0)
 669                 return;
 670
 671         for (i = 0; i < ETH_ALEN; i++)
 672                 mac[i] = readl(&fuse->mac_addr[i]);
 673 }
 674
 675 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 676                         PAD_CTL_SRE_FAST)
 677 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 678 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 679
 680 int board_eth_init(bd_t *bis)
 681 {
 682         int ret;
 683
 684         /* delay at least 21ms for the PHY internal POR signal to deassert */
 685         udelay(22000);
 686
 687         /* Deassert RESET to the external phy */
 688         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 689
 690         ret = cpu_eth_init(bis);
 691         if (ret)
 692                 printf("cpu_eth_init() failed: %d\n", ret);
 693
 694         return ret;
 695 }
 696 #endif /* CONFIG_FEC_MXC */
 697
 698 enum {
 699         LED_STATE_INIT = -1,
 700         LED_STATE_OFF,
 701         LED_STATE_ON,
 702 };
 703
 704 void show_activity(int arg)
 705 {
 706         static int led_state = LED_STATE_INIT;
 707         static ulong last;
 708
 709         if (led_state == LED_STATE_INIT) {
 710                 last = get_timer(0);
 711                 gpio_set_value(TX53_LED_GPIO, 1);
 712                 led_state = LED_STATE_ON;
 713         } else {
 714                 if (get_timer(last) > CONFIG_SYS_HZ) {
 715                         last = get_timer(0);
 716                         if (led_state == LED_STATE_ON) {
 717                                 gpio_set_value(TX53_LED_GPIO, 0);
 718                         } else {
 719                                 gpio_set_value(TX53_LED_GPIO, 1);
 720                         }
 721                         led_state = 1 - led_state;
 722                 }
 723         }
 724 }
 725
 726 static const iomux_v3_cfg_t stk5_pads[] = {
 727         /* SW controlled LED on STK5 baseboard */
 728         MX53_PAD_EIM_A18__GPIO2_20,
 729
 730         /* I2C bus on DIMM pins 40/41 */
 731         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
 732         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
 733
 734         /* TSC200x PEN IRQ */
 735         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
 736
 737         /* EDT-FT5x06 Polytouch panel */
 738         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
 739         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
 740         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
 741
 742         /* USBH1 */
 743         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
 744         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
 745         /* USBOTG */
 746         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 747         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 748
 749         /* DS1339 Interrupt */
 750         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
 751 };
 752
 753 static const struct gpio stk5_gpios[] = {
 754         { TX53_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 755
 756         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 757         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 758         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 759         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 760 };
 761
 762 #ifdef CONFIG_LCD
 763 static u16 tx53_cmap[256];
 764 vidinfo_t panel_info = {
 765         /* set to max. size supported by SoC */
 766         .vl_col = 1600,
 767         .vl_row = 1200,
 768
 769         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 770         .cmap = tx53_cmap,
 771 };
 772
 773 static struct fb_videomode tx53_fb_modes[] = {
 774 #ifndef CONFIG_SYS_LVDS_IF
 775         {
 776                 /* Standard VGA timing */
 777                 .name           = "VGA",
 778                 .refresh        = 60,
 779                 .xres           = 640,
 780                 .yres           = 480,
 781                 .pixclock       = KHZ2PICOS(25175),
 782                 .left_margin    = 48,
 783                 .hsync_len      = 96,
 784                 .right_margin   = 16,
 785                 .upper_margin   = 31,
 786                 .vsync_len      = 2,
 787                 .lower_margin   = 12,
 788                 .sync           = FB_SYNC_CLK_LAT_FALL,
 789         },
 790         {
 791                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 792                  * DE high active, 115.2 mm x 86.4 mm display area
 793                  * VGA compatible timing
 794                  */
 795                 .name           = "ETV570",
 796                 .refresh        = 60,
 797                 .xres           = 640,
 798                 .yres           = 480,
 799                 .pixclock       = KHZ2PICOS(25175),
 800                 .left_margin    = 114,
 801                 .hsync_len      = 30,
 802                 .right_margin   = 16,
 803                 .upper_margin   = 32,
 804                 .vsync_len      = 3,
 805                 .lower_margin   = 10,
 806                 .sync           = FB_SYNC_CLK_LAT_FALL,
 807         },
 808         {
 809                 /* Emerging ET0350G0DH6 320 x 240 display.
 810                  * 70.08 mm x 52.56 mm display area.
 811                  */
 812                 .name           = "ET0350",
 813                 .refresh        = 60,
 814                 .xres           = 320,
 815                 .yres           = 240,
 816                 .pixclock       = KHZ2PICOS(6500),
 817                 .left_margin    = 68 - 34,
 818                 .hsync_len      = 34,
 819                 .right_margin   = 20,
 820                 .upper_margin   = 18 - 3,
 821                 .vsync_len      = 3,
 822                 .lower_margin   = 4,
 823                 .sync           = FB_SYNC_CLK_LAT_FALL,
 824         },
 825         {
 826                 /* Emerging ET0430G0DH6 480 x 272 display.
 827                  * 95.04 mm x 53.856 mm display area.
 828                  */
 829                 .name           = "ET0430",
 830                 .refresh        = 60,
 831                 .xres           = 480,
 832                 .yres           = 272,
 833                 .pixclock       = KHZ2PICOS(9000),
 834                 .left_margin    = 2,
 835                 .hsync_len      = 41,
 836                 .right_margin   = 2,
 837                 .upper_margin   = 2,
 838                 .vsync_len      = 10,
 839                 .lower_margin   = 2,
 840                 .sync           = FB_SYNC_CLK_LAT_FALL,
 841         },
 842         {
 843                 /* Emerging ET0500G0DH6 800 x 480 display.
 844                  * 109.6 mm x 66.4 mm display area.
 845                  */
 846                 .name           = "ET0500",
 847                 .refresh        = 60,
 848                 .xres           = 800,
 849                 .yres           = 480,
 850                 .pixclock       = KHZ2PICOS(33260),
 851                 .left_margin    = 216 - 128,
 852                 .hsync_len      = 128,
 853                 .right_margin   = 1056 - 800 - 216,
 854                 .upper_margin   = 35 - 2,
 855                 .vsync_len      = 2,
 856                 .lower_margin   = 525 - 480 - 35,
 857                 .sync           = FB_SYNC_CLK_LAT_FALL,
 858         },
 859         {
 860                 /* Emerging ETQ570G0DH6 320 x 240 display.
 861                  * 115.2 mm x 86.4 mm display area.
 862                  */
 863                 .name           = "ETQ570",
 864                 .refresh        = 60,
 865                 .xres           = 320,
 866                 .yres           = 240,
 867                 .pixclock       = KHZ2PICOS(6400),
 868                 .left_margin    = 38,
 869                 .hsync_len      = 30,
 870                 .right_margin   = 30,
 871                 .upper_margin   = 16, /* 15 according to datasheet */
 872                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 873                 .lower_margin   = 4, /* 4.5 according to datasheet */
 874                 .sync           = FB_SYNC_CLK_LAT_FALL,
 875         },
 876         {
 877                 /* Emerging ET0700G0DH6 800 x 480 display.
 878                  * 152.4 mm x 91.44 mm display area.
 879                  */
 880                 .name           = "ET0700",
 881                 .refresh        = 60,
 882                 .xres           = 800,
 883                 .yres           = 480,
 884                 .pixclock       = KHZ2PICOS(33260),
 885                 .left_margin    = 216 - 128,
 886                 .hsync_len      = 128,
 887                 .right_margin   = 1056 - 800 - 216,
 888                 .upper_margin   = 35 - 2,
 889                 .vsync_len      = 2,
 890                 .lower_margin   = 525 - 480 - 35,
 891                 .sync           = FB_SYNC_CLK_LAT_FALL,
 892         },
 893 #else
 894         {
 895                 /* HannStar HSD100PXN1
 896                  * 202.7m mm x 152.06 mm display area.
 897                  */
 898                 .name           = "HSD100PXN1",
 899                 .refresh        = 60,
 900                 .xres           = 1024,
 901                 .yres           = 768,
 902                 .pixclock       = KHZ2PICOS(65000),
 903                 .left_margin    = 0,
 904                 .hsync_len      = 0,
 905                 .right_margin   = 320,
 906                 .upper_margin   = 0,
 907                 .vsync_len      = 0,
 908                 .lower_margin   = 38,
 909                 .sync           = FB_SYNC_CLK_LAT_FALL,
 910         },
 911 #endif
 912         {
 913                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 914                 .refresh        = 60,
 915                 .left_margin    = 48,
 916                 .hsync_len      = 96,
 917                 .right_margin   = 16,
 918                 .upper_margin   = 31,
 919                 .vsync_len      = 2,
 920                 .lower_margin   = 12,
 921                 .sync           = FB_SYNC_CLK_LAT_FALL,
 922         },
 923 };
 924
 925 static int lcd_enabled = 1;
 926 static int lcd_bl_polarity;
 927
 928 static int lcd_backlight_polarity(void)
 929 {
 930         return lcd_bl_polarity;
 931 }
 932
 933 void lcd_enable(void)
 934 {
 935         /* HACK ALERT:
 936          * global variable from common/lcd.c
 937          * Set to 0 here to prevent messages from going to LCD
 938          * rather than serial console
 939          */
 940         lcd_is_enabled = 0;
 941
 942         if (lcd_enabled) {
 943                 karo_load_splashimage(1);
 944
 945                 debug("Switching LCD on\n");
 946                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 947                 udelay(100);
 948                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 949                 udelay(300000);
 950                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
 951                         lcd_backlight_polarity());
 952         }
 953 }
 954
 955 void lcd_disable(void)
 956 {
 957         if (lcd_enabled) {
 958                 printf("Disabling LCD\n");
 959                 ipuv3_fb_shutdown();
 960         }
 961 }
 962
 963 void lcd_panel_disable(void)
 964 {
 965         if (lcd_enabled) {
 966                 debug("Switching LCD off\n");
 967                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
 968                         !lcd_backlight_polarity());
 969                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
 970                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
 971         }
 972 }
 973
 974 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 975         /* LCD RESET */
 976         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
 977         /* LCD POWER_ENABLE */
 978         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
 979         /* LCD Backlight (PWM) */
 980         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
 981
 982         /* Display */
 983 #ifndef CONFIG_SYS_LVDS_IF
 984         /* LCD option */
 985         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 986         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 987         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 988         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 989         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 990         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 991         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 992         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 993         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 994         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 995         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 996         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 997         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 998         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 999         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
1000         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
1001         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
1002         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
1003         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
1004         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
1005         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
1006         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
1007         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
1008         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
1009         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
1010         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
1011         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
1012         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
1013 #else
1014         /* LVDS option */
1015         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
1016         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
1017         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
1018         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
1019         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
1020         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
1021         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
1022         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
1023         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
1024         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
1025 #endif
1026 };
1027
1028 static const struct gpio stk5_lcd_gpios[] = {
1029         { TX53_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1030         { TX53_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1031         { TX53_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1032 };
1033
1034 void lcd_ctrl_init(void *lcdbase)
1035 {
1036         int color_depth = 24;
1037         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1038         const char *vm;
1039         unsigned long val;
1040         int refresh = 60;
1041         struct fb_videomode *p = &tx53_fb_modes[0];
1042         struct fb_videomode fb_mode;
1043         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1044         int pix_fmt;
1045         int lcd_bus_width;
1046         ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
1047         unsigned long di_clk_rate = 65000000;
1048
1049         if (!lcd_enabled) {
1050                 debug("LCD disabled\n");
1051                 return;
1052         }
1053
1054         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1055                 debug("Disabling LCD\n");
1056                 lcd_enabled = 0;
1057                 setenv("splashimage", NULL);
1058                 return;
1059         }
1060
1061         karo_fdt_move_fdt();
1062
1063         if (video_mode == NULL) {
1064                 debug("Disabling LCD\n");
1065                 lcd_enabled = 0;
1066                 return;
1067         }
1068
1069         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1070         vm = video_mode;
1071         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1072                 p = &fb_mode;
1073                 debug("Using video mode from FDT\n");
1074                 vm += strlen(vm);
1075                 if (fb_mode.xres > panel_info.vl_col ||
1076                         fb_mode.yres > panel_info.vl_row) {
1077                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1078                                 fb_mode.xres, fb_mode.yres,
1079                                 panel_info.vl_col, panel_info.vl_row);
1080                         lcd_enabled = 0;
1081                         return;
1082                 }
1083         }
1084         if (p->name != NULL)
1085                 debug("Trying compiled-in video modes\n");
1086         while (p->name != NULL) {
1087                 if (strcmp(p->name, vm) == 0) {
1088                         debug("Using video mode: '%s'\n", p->name);
1089                         vm += strlen(vm);
1090                         break;
1091                 }
1092                 p++;
1093         }
1094         if (*vm != '\0')
1095                 debug("Trying to decode video_mode: '%s'\n", vm);
1096         while (*vm != '\0') {
1097                 if (*vm >= '0' && *vm <= '9') {
1098                         char *end;
1099
1100                         val = simple_strtoul(vm, &end, 0);
1101                         if (end > vm) {
1102                                 if (!xres_set) {
1103                                         if (val > panel_info.vl_col)
1104                                                 val = panel_info.vl_col;
1105                                         p->xres = val;
1106                                         panel_info.vl_col = val;
1107                                         xres_set = 1;
1108                                 } else if (!yres_set) {
1109                                         if (val > panel_info.vl_row)
1110                                                 val = panel_info.vl_row;
1111                                         p->yres = val;
1112                                         panel_info.vl_row = val;
1113                                         yres_set = 1;
1114                                 } else if (!bpp_set) {
1115                                         switch (val) {
1116                                         case 32:
1117                                         case 24:
1118                                                 if (is_lvds())
1119                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1120                                                 /* fallthru */
1121                                         case 16:
1122                                         case 8:
1123                                                 color_depth = val;
1124                                                 break;
1125
1126                                         case 18:
1127                                                 if (is_lvds()) {
1128                                                         color_depth = val;
1129                                                         break;
1130                                                 }
1131                                                 /* fallthru */
1132                                         default:
1133                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1134                                                         end - vm, vm, color_depth);
1135                                         }
1136                                         bpp_set = 1;
1137                                 } else if (!refresh_set) {
1138                                         refresh = val;
1139                                         refresh_set = 1;
1140                                 }
1141                         }
1142                         vm = end;
1143                 }
1144                 switch (*vm) {
1145                 case '@':
1146                         bpp_set = 1;
1147                         /* fallthru */
1148                 case '-':
1149                         yres_set = 1;
1150                         /* fallthru */
1151                 case 'x':
1152                         xres_set = 1;
1153                         /* fallthru */
1154                 case 'M':
1155                 case 'R':
1156                         vm++;
1157                         break;
1158
1159                 default:
1160                         if (*vm != '\0')
1161                                 vm++;
1162                 }
1163         }
1164         if (p->xres == 0 || p->yres == 0) {
1165                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1166                 lcd_enabled = 0;
1167                 printf("Supported video modes are:");
1168                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
1169                         printf(" %s", p->name);
1170                 }
1171                 printf("\n");
1172                 return;
1173         }
1174         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1175                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1176                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1177                 lcd_enabled = 0;
1178                 return;
1179         }
1180         panel_info.vl_col = p->xres;
1181         panel_info.vl_row = p->yres;
1182
1183         switch (color_depth) {
1184         case 8:
1185                 panel_info.vl_bpix = LCD_COLOR8;
1186                 break;
1187         case 16:
1188                 panel_info.vl_bpix = LCD_COLOR16;
1189                 break;
1190         default:
1191                 panel_info.vl_bpix = LCD_COLOR32;
1192         }
1193
1194         p->pixclock = KHZ2PICOS(refresh *
1195                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1196                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1197                                 1000);
1198         debug("Pixel clock set to %lu.%03lu MHz\n",
1199                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1200
1201         if (p != &fb_mode) {
1202                 int ret;
1203
1204                 debug("Creating new display-timing node from '%s'\n",
1205                         video_mode);
1206                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1207                 if (ret)
1208                         printf("Failed to create new display-timing node from '%s': %d\n",
1209                                 video_mode, ret);
1210         }
1211
1212         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1213         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1214                                         ARRAY_SIZE(stk5_lcd_pads));
1215
1216         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1217         switch (lcd_bus_width) {
1218         case 24:
1219                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1220                 break;
1221
1222         case 18:
1223                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1224                 break;
1225
1226         case 16:
1227                 if (!is_lvds()) {
1228                         pix_fmt = IPU_PIX_FMT_RGB565;
1229                         break;
1230                 }
1231                 /* fallthru */
1232         default:
1233                 lcd_enabled = 0;
1234                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1235                         lcd_bus_width);
1236                 return;
1237         }
1238         if (is_lvds()) {
1239                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1240                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1241                 uint32_t gpr2;
1242
1243                 if (lvds_chan_mask == 0) {
1244                         printf("No LVDS channel active\n");
1245                         lcd_enabled = 0;
1246                         return;
1247                 }
1248
1249                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1250                 if (lcd_bus_width == 24)
1251                         gpr2 |= (1 << 5) | (1 << 7);
1252                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1253                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1254                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1255                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1256         }
1257         if (karo_load_splashimage(0) == 0) {
1258                 int ret;
1259
1260                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1261
1262                 debug("Initializing LCD controller\n");
1263                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1264                 if (ret) {
1265                         printf("Failed to initialize FB driver: %d\n", ret);
1266                         lcd_enabled = 0;
1267                 }
1268         } else {
1269                 debug("Skipping initialization of LCD controller\n");
1270         }
1271 }
1272 #else
1273 #define lcd_enabled 0
1274 #endif /* CONFIG_LCD */
1275
1276 static void stk5_board_init(void)
1277 {
1278         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1279         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1280 }
1281
1282 static void stk5v3_board_init(void)
1283 {
1284         stk5_board_init();
1285 }
1286
1287 static void stk5v5_board_init(void)
1288 {
1289         stk5_board_init();
1290
1291         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1292                         "Flexcan Transceiver");
1293         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1294 }
1295
1296 static void tx53_set_cpu_clock(void)
1297 {
1298         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1299
1300         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1301                 return;
1302
1303         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1304                 printf("%s detected; skipping cpu clock change\n",
1305                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1306                 return;
1307         }
1308
1309         if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1310                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1311                 printf("CPU clock set to %lu.%03lu MHz\n",
1312                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1313         } else {
1314                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1315         }
1316 }
1317
1318 static void tx53_init_mac(void)
1319 {
1320         u8 mac[ETH_ALEN];
1321
1322         imx_get_mac_from_fuse(0, mac);
1323         if (!is_valid_ether_addr(mac)) {
1324                 printf("No valid MAC address programmed\n");
1325                 return;
1326         }
1327
1328         printf("MAC addr from fuse: %pM\n", mac);
1329         eth_setenv_enetaddr("ethaddr", mac);
1330 }
1331
1332 int board_late_init(void)
1333 {
1334         int ret = 0;
1335         const char *baseboard;
1336
1337         env_cleanup();
1338
1339         tx53_set_cpu_clock();
1340
1341         if (had_ctrlc())
1342                 setenv_ulong("safeboot", 1);
1343         else if (wrsr & WRSR_TOUT)
1344                 setenv_ulong("wdreset", 1);
1345         else
1346                 karo_fdt_move_fdt();
1347
1348         baseboard = getenv("baseboard");
1349         if (!baseboard)
1350                 goto exit;
1351
1352         printf("Baseboard: %s\n", baseboard);
1353
1354         if (strncmp(baseboard, "stk5", 4) == 0) {
1355                 if ((strlen(baseboard) == 4) ||
1356                         strcmp(baseboard, "stk5-v3") == 0) {
1357                         stk5v3_board_init();
1358                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1359                         const char *otg_mode = getenv("otg_mode");
1360
1361                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1362                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1363                                         otg_mode, baseboard);
1364                                 setenv("otg_mode", "none");
1365                         }
1366                         stk5v5_board_init();
1367                 } else {
1368                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1369                                 baseboard + 4);
1370                 }
1371         } else {
1372                 printf("WARNING: Unsupported baseboard: '%s'\n",
1373                         baseboard);
1374                 ret = -EINVAL;
1375         }
1376
1377 exit:
1378         tx53_init_mac();
1379
1380         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1381         clear_ctrlc();
1382         return ret;
1383 }
1384
1385 int checkboard(void)
1386 {
1387         tx53_print_cpuinfo();
1388 #if CONFIG_SYS_SDRAM_SIZE < SZ_1G
1389         printf("Board: Ka-Ro TX53-8%d3%c\n",
1390                 is_lvds(), '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1391 #elif CONFIG_SYS_SDRAM_SIZE < SZ_2G
1392         printf("Board: Ka-Ro TX53-1%d3%c\n",
1393                 is_lvds() + 2, '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1394 #else
1395         printf("Board: Ka-Ro TX53-123%c\n",
1396                 '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1397 #endif
1398         return 0;
1399 }
1400
1401 #if defined(CONFIG_OF_BOARD_SETUP)
1402 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1403 #include <jffs2/jffs2.h>
1404 #include <mtd_node.h>
1405 static struct node_info nodes[] = {
1406         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1407 };
1408 #else
1409 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1410 #endif
1411
1412 #ifdef CONFIG_SYS_TX53_HWREV_2
1413 static void tx53_fixup_rtc(void *blob)
1414 {
1415         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1416         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1417 }
1418 #else
1419 static inline void tx53_fixup_rtc(void *blob)
1420 {
1421 }
1422 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1423
1424 static const char *tx53_touchpanels[] = {
1425         "ti,tsc2007",
1426         "edt,edt-ft5x06",
1427         "eeti,egalax_ts",
1428 };
1429
1430 int ft_board_setup(void *blob, bd_t *bd)
1431 {
1432         const char *baseboard = getenv("baseboard");
1433         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1434         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1435         int ret;
1436
1437         ret = fdt_increase_size(blob, 4096);
1438         if (ret) {
1439                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1440                 return ret;
1441         }
1442         if (stk5_v5)
1443                 karo_fdt_enable_node(blob, "stk5led", 0);
1444
1445         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1446         fdt_fixup_ethernet(blob);
1447
1448         karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
1449                                 ARRAY_SIZE(tx53_touchpanels));
1450         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1451         karo_fdt_fixup_flexcan(blob, stk5_v5);
1452         tx53_fixup_rtc(blob);
1453         karo_fdt_update_fb_mode(blob, video_mode);
1454
1455         return 0;
1456 }
1457 #endif /* CONFIG_OF_BOARD_SETUP */