board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <i2c.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <video_fb.h>
  29 #include <ipu.h>
  30 #include <mxcfb.h>
  31 #include <linux/fb.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/iomux-mx53.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/arch/imx-regs.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <asm/arch/sys_proto.h>
  39
  40 #include "../common/karo.h"
  41
  42 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  43 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  44 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  45 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  46
  47 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  48 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  50
  51 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
  56                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  57
  58 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
  59                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
  60
  61 static iomux_v3_cfg_t tx53_pads[] = {
  62         /* NAND flash pads are set up in lowlevel_init.S */
  63
  64         /* UART pads */
  65 #if CONFIG_MXC_UART_BASE == UART1_BASE
  66         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  67         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  68         MX53_PAD_PATA_IORDY__UART1_RTS,
  69         MX53_PAD_PATA_RESET_B__UART1_CTS,
  70 #endif
  71 #if CONFIG_MXC_UART_BASE == UART2_BASE
  72         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  73         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  74         MX53_PAD_PATA_DIOR__UART2_RTS,
  75         MX53_PAD_PATA_INTRQ__UART2_CTS,
  76 #endif
  77 #if CONFIG_MXC_UART_BASE == UART3_BASE
  78         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  79         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  80         MX53_PAD_PATA_DA_2__UART3_RTS,
  81         MX53_PAD_PATA_DA_1__UART3_CTS,
  82 #endif
  83         /* internal I2C */
  84         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
  85         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
  86
  87         /* FEC PHY GPIO functions */
  88         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  89         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  90         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  91
  92         /* FEC functions */
  93         MX53_PAD_FEC_MDC__FEC_MDC,
  94         MX53_PAD_FEC_MDIO__FEC_MDIO,
  95         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  96         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  97         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  98         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  99         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 100         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 101         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 102         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 103 };
 104
 105 static const struct gpio tx53_gpios[] = {
 106         { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 107         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 108         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 109         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 110 };
 111
 112 /*
 113  * Functions
 114  */
 115 /* placed in section '.data' to prevent overwriting relocation info
 116  * overlayed with bss
 117  */
 118 static u32 wrsr __attribute__((section(".data")));
 119
 120 #define WRSR_POR        (1 << 4)
 121 #define WRSR_TOUT       (1 << 1)
 122 #define WRSR_SFTW       (1 << 0)
 123
 124 static void print_reset_cause(void)
 125 {
 126         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 127         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 128         u32 srsr;
 129         char *dlm = "";
 130
 131         printf("Reset cause: ");
 132
 133         srsr = readl(&src_regs->srsr);
 134         wrsr = readw(wdt_base + 4);
 135
 136         if (wrsr & WRSR_POR) {
 137                 printf("%sPOR", dlm);
 138                 dlm = " | ";
 139         }
 140         if (srsr & 0x00004) {
 141                 printf("%sCSU", dlm);
 142                 dlm = " | ";
 143         }
 144         if (srsr & 0x00008) {
 145                 printf("%sIPP USER", dlm);
 146                 dlm = " | ";
 147         }
 148         if (srsr & 0x00010) {
 149                 if (wrsr & WRSR_SFTW) {
 150                         printf("%sSOFT", dlm);
 151                         dlm = " | ";
 152                 }
 153                 if (wrsr & WRSR_TOUT) {
 154                         printf("%sWDOG", dlm);
 155                         dlm = " | ";
 156                 }
 157         }
 158         if (srsr & 0x00020) {
 159                 printf("%sJTAG HIGH-Z", dlm);
 160                 dlm = " | ";
 161         }
 162         if (srsr & 0x00040) {
 163                 printf("%sJTAG SW", dlm);
 164                 dlm = " | ";
 165         }
 166         if (srsr & 0x10000) {
 167                 printf("%sWARM BOOT", dlm);
 168                 dlm = " | ";
 169         }
 170         if (dlm[0] == '\0')
 171                 printf("unknown");
 172
 173         printf("\n");
 174 }
 175
 176 static void tx53_print_cpuinfo(void)
 177 {
 178         u32 cpurev;
 179
 180         cpurev = get_cpu_rev();
 181
 182         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 183                 (cpurev & 0x000F0) >> 4,
 184                 (cpurev & 0x0000F) >> 0,
 185                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 186
 187         print_reset_cause();
 188 }
 189
 190 enum LTC3589_REGS {
 191         LTC3589_SCR1 = 0x07,
 192         LTC3589_CLIRQ = 0x21,
 193         LTC3589_B1DTV1 = 0x23,
 194         LTC3589_B1DTV2 = 0x24,
 195         LTC3589_VRRCR = 0x25,
 196         LTC3589_B2DTV1 = 0x26,
 197         LTC3589_B2DTV2 = 0x27,
 198         LTC3589_B3DTV1 = 0x29,
 199         LTC3589_B3DTV2 = 0x2a,
 200         LTC3589_L2DTV1 = 0x32,
 201         LTC3589_L2DTV2 = 0x33,
 202 };
 203
 204 #define LTC3589_PGOOD_MASK      (1 << 5)
 205
 206 #define LTC3589_CLK_RATE_LOW    (1 << 5)
 207
 208 #define VDD_LDO2_VAL            mV_to_regval(vout_to_vref(1325 * 10, 2))
 209 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1240 * 10, 3))
 210 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1325 * 10, 4))
 211 #define VDD_BUCK3_VAL           mV_to_regval(vout_to_vref(2500 * 10, 5))
 212
 213 #ifndef CONFIG_SYS_TX53_HWREV_2
 214 /* LDO2 vref divider */
 215 #define R1_2    180
 216 #define R2_2    191
 217 /* BUCK1 vref divider */
 218 #define R1_3    150
 219 #define R2_3    180
 220 /* BUCK2 vref divider */
 221 #define R1_4    180
 222 #define R2_4    191
 223 /* BUCK3 vref divider */
 224 #define R1_5    270
 225 #define R2_5    100
 226 #else
 227 /* no dividers on vref */
 228 #define R1_2    0
 229 #define R2_2    1
 230 #define R1_3    0
 231 #define R2_3    1
 232 #define R1_4    0
 233 #define R2_4    1
 234 #define R1_5    0
 235 #define R2_5    1
 236 #endif
 237
 238 /* calculate voltages in 10mV */
 239 #define R1(idx)                 R1_##idx
 240 #define R2(idx)                 R2_##idx
 241
 242 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
 243 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
 244
 245 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 3625) ? 3625 : (mV)) - 3625), 125)
 246 #define regval_to_mV(v)         (((v) * 125 + 3625))
 247
 248 static struct pmic_regs {
 249         enum LTC3589_REGS addr;
 250         u8 val;
 251 } ltc3589_regs[] = {
 252         { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
 253
 254         { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_PGOOD_MASK, },
 255         { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
 256
 257         { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_PGOOD_MASK, },
 258         { LTC3589_B1DTV2, VDD_CORE_VAL, },
 259
 260         { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_PGOOD_MASK, },
 261         { LTC3589_B2DTV2, VDD_SOC_VAL, },
 262
 263         { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_PGOOD_MASK, },
 264         { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
 265
 266         { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
 267 };
 268
 269 static int setup_pmic_voltages(void)
 270 {
 271         int ret;
 272         unsigned char value;
 273         int i;
 274
 275         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 276         if (ret != 0) {
 277                 printf("Failed to initialize I2C\n");
 278                 return ret;
 279         }
 280
 281         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 282         if (ret) {
 283                 printf("%s: i2c_read error: %d\n", __func__, ret);
 284                 return ret;
 285         }
 286
 287         for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
 288                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 289                                 &value, 1);
 290                 debug("Writing %02x to reg %02x (%02x)\n",
 291                         ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
 292                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
 293                                 &ltc3589_regs[i].val, 1);
 294                 if (ret) {
 295                         printf("%s: failed to write PMIC register %02x: %d\n",
 296                                 __func__, ltc3589_regs[i].addr, ret);
 297                         return ret;
 298                 }
 299         }
 300         printf("VDDCORE set to %umV\n",
 301                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
 302
 303         printf("VDDSOC  set to %umV\n",
 304                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
 305         return 0;
 306 }
 307
 308 int board_early_init_f(void)
 309 {
 310         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 311
 312         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 313         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 314
 315         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 316         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 317
 318         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 319         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 320         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 321         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 322         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 323
 324         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 325         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 326
 327         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 328         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 329         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 330         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 331         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 332
 333         writel(0xffcf0fff, &ccm_regs->CCGR0);
 334         writel(0x000fffc3, &ccm_regs->CCGR1);
 335         writel(0x033c0000, &ccm_regs->CCGR2);
 336         writel(0x000000ff, &ccm_regs->CCGR3);
 337         writel(0x00000000, &ccm_regs->CCGR4);
 338         writel(0x00fff033, &ccm_regs->CCGR5);
 339         writel(0x0f00030f, &ccm_regs->CCGR6);
 340         writel(0xfff00000, &ccm_regs->CCGR7);
 341         writel(0x00000000, &ccm_regs->cmeor);
 342
 343         return 0;
 344 }
 345
 346 int board_init(void)
 347 {
 348         int ret;
 349
 350         /* Address of boot parameters */
 351         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 352
 353         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 354                 printf("CTRL-C detected; Skipping PMIC setup\n");
 355                 return 1;
 356         }
 357
 358         ret = setup_pmic_voltages();
 359         if (ret) {
 360                 printf("Failed to setup PMIC voltages\n");
 361                 hang();
 362         }
 363         return 0;
 364 }
 365
 366 int dram_init(void)
 367 {
 368         int ret;
 369
 370         /* dram_init must store complete ramsize in gd->ram_size */
 371         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 372                                 PHYS_SDRAM_1_SIZE);
 373
 374         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 375                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 376         if (ret)
 377                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 378                         CONFIG_SYS_SDRAM_CLK, ret);
 379         else
 380                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 381                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 382                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 383                         CONFIG_SYS_SDRAM_CLK);
 384         return ret;
 385 }
 386
 387 void dram_init_banksize(void)
 388 {
 389         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 390         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 391                         PHYS_SDRAM_1_SIZE);
 392 #if CONFIG_NR_DRAM_BANKS > 1
 393         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 394         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 395                         PHYS_SDRAM_2_SIZE);
 396 #endif
 397 }
 398
 399 #ifdef  CONFIG_CMD_MMC
 400 static const iomux_v3_cfg_t mmc0_pads[] = {
 401         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
 402         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
 403         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
 404         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
 405         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
 406         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
 407         /* SD1 CD */
 408         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
 409 };
 410
 411 static const iomux_v3_cfg_t mmc1_pads[] = {
 412         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
 413         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
 414         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
 415         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
 416         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
 417         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
 418         /* SD2 CD */
 419         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
 420 };
 421
 422 static struct tx53_esdhc_cfg {
 423         const iomux_v3_cfg_t *pads;
 424         int num_pads;
 425         struct fsl_esdhc_cfg cfg;
 426         int cd_gpio;
 427 } tx53_esdhc_cfg[] = {
 428         {
 429                 .pads = mmc0_pads,
 430                 .num_pads = ARRAY_SIZE(mmc0_pads),
 431                 .cfg = {
 432                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 433                         .max_bus_width = 4,
 434                 },
 435                 .cd_gpio = IMX_GPIO_NR(3, 24),
 436         },
 437         {
 438                 .pads = mmc1_pads,
 439                 .num_pads = ARRAY_SIZE(mmc1_pads),
 440                 .cfg = {
 441                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 442                         .max_bus_width = 4,
 443                 },
 444                 .cd_gpio = IMX_GPIO_NR(3, 25),
 445         },
 446 };
 447
 448 static inline struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 449 {
 450         return container_of(cfg, struct tx53_esdhc_cfg, cfg);
 451 }
 452
 453 int board_mmc_getcd(struct mmc *mmc)
 454 {
 455         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
 456
 457         if (cfg->cd_gpio < 0)
 458                 return cfg->cd_gpio;
 459
 460         debug("SD card %d is %spresent\n",
 461                 cfg - tx53_esdhc_cfg,
 462                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 463         return !gpio_get_value(cfg->cd_gpio);
 464 }
 465
 466 int board_mmc_init(bd_t *bis)
 467 {
 468         int i;
 469
 470         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
 471                 struct mmc *mmc;
 472                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
 473                 int ret;
 474
 475                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 476                         break;
 477
 478                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 479                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 480
 481                 ret = gpio_request_one(cfg->cd_gpio,
 482                                 GPIOF_INPUT, "MMC CD");
 483                 if (ret) {
 484                         printf("Error %d requesting GPIO%d_%d\n",
 485                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 486                         continue;
 487                 }
 488
 489                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 490                 fsl_esdhc_initialize(bis, &cfg->cfg);
 491
 492                 mmc = find_mmc_device(i);
 493                 if (mmc == NULL)
 494                         continue;
 495                 if (board_mmc_getcd(mmc) > 0)
 496                         mmc_init(mmc);
 497         }
 498         return 0;
 499 }
 500 #endif /* CONFIG_CMD_MMC */
 501
 502 #ifdef CONFIG_FEC_MXC
 503
 504 #ifndef ETH_ALEN
 505 #define ETH_ALEN 6
 506 #endif
 507
 508 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 509 {
 510         int i;
 511         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 512         struct fuse_bank *bank = &iim->bank[1];
 513         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 514
 515         if (dev_id > 0)
 516                 return;
 517
 518         for (i = 0; i < ETH_ALEN; i++)
 519                 mac[i] = readl(&fuse->mac_addr[i]);
 520 }
 521
 522 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 523                         PAD_CTL_SRE_FAST)
 524 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 525 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 526
 527 int board_eth_init(bd_t *bis)
 528 {
 529         int ret;
 530
 531         /* delay at least 21ms for the PHY internal POR signal to deassert */
 532         udelay(22000);
 533
 534         /* Deassert RESET to the external phy */
 535         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 536
 537         ret = cpu_eth_init(bis);
 538         if (ret)
 539                 printf("cpu_eth_init() failed: %d\n", ret);
 540
 541         return ret;
 542 }
 543 #endif /* CONFIG_FEC_MXC */
 544
 545 enum {
 546         LED_STATE_INIT = -1,
 547         LED_STATE_OFF,
 548         LED_STATE_ON,
 549 };
 550
 551 void show_activity(int arg)
 552 {
 553         static int led_state = LED_STATE_INIT;
 554         static ulong last;
 555
 556         if (led_state == LED_STATE_INIT) {
 557                 last = get_timer(0);
 558                 gpio_set_value(TX53_LED_GPIO, 1);
 559                 led_state = LED_STATE_ON;
 560         } else {
 561                 if (get_timer(last) > CONFIG_SYS_HZ) {
 562                         last = get_timer(0);
 563                         if (led_state == LED_STATE_ON) {
 564                                 gpio_set_value(TX53_LED_GPIO, 0);
 565                         } else {
 566                                 gpio_set_value(TX53_LED_GPIO, 1);
 567                         }
 568                         led_state = 1 - led_state;
 569                 }
 570         }
 571 }
 572
 573 static const iomux_v3_cfg_t stk5_pads[] = {
 574         /* SW controlled LED on STK5 baseboard */
 575         MX53_PAD_EIM_A18__GPIO2_20,
 576
 577         /* I2C bus on DIMM pins 40/41 */
 578         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
 579         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
 580
 581         /* TSC200x PEN IRQ */
 582         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
 583
 584         /* EDT-FT5x06 Polytouch panel */
 585         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
 586         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
 587         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
 588
 589         /* USBH1 */
 590         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
 591         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
 592         /* USBOTG */
 593         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 594         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 595
 596         /* DS1339 Interrupt */
 597         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
 598 };
 599
 600 static const struct gpio stk5_gpios[] = {
 601         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 602
 603         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 604         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 605         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 606         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 607 };
 608
 609 #ifdef CONFIG_LCD
 610 static u16 tx53_cmap[256];
 611 vidinfo_t panel_info = {
 612         /* set to max. size supported by SoC */
 613         .vl_col = 1600,
 614         .vl_row = 1200,
 615
 616         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 617         .cmap = tx53_cmap,
 618 };
 619
 620 static struct fb_videomode tx53_fb_modes[] = {
 621 #ifndef CONFIG_SYS_LVDS_IF
 622         {
 623                 /* Standard VGA timing */
 624                 .name           = "VGA",
 625                 .refresh        = 60,
 626                 .xres           = 640,
 627                 .yres           = 480,
 628                 .pixclock       = KHZ2PICOS(25175),
 629                 .left_margin    = 48,
 630                 .hsync_len      = 96,
 631                 .right_margin   = 16,
 632                 .upper_margin   = 31,
 633                 .vsync_len      = 2,
 634                 .lower_margin   = 12,
 635                 .sync           = FB_SYNC_CLK_LAT_FALL,
 636         },
 637         {
 638                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 639                  * DE high active, 115.2 mm x 86.4 mm display area
 640                  * VGA compatible timing
 641                  */
 642                 .name           = "ETV570",
 643                 .refresh        = 60,
 644                 .xres           = 640,
 645                 .yres           = 480,
 646                 .pixclock       = KHZ2PICOS(25175),
 647                 .left_margin    = 114,
 648                 .hsync_len      = 30,
 649                 .right_margin   = 16,
 650                 .upper_margin   = 32,
 651                 .vsync_len      = 3,
 652                 .lower_margin   = 10,
 653                 .sync           = FB_SYNC_CLK_LAT_FALL,
 654         },
 655         {
 656                 /* Emerging ET0350G0DH6 320 x 240 display.
 657                  * 70.08 mm x 52.56 mm display area.
 658                  */
 659                 .name           = "ET0350",
 660                 .refresh        = 60,
 661                 .xres           = 320,
 662                 .yres           = 240,
 663                 .pixclock       = KHZ2PICOS(6500),
 664                 .left_margin    = 68 - 34,
 665                 .hsync_len      = 34,
 666                 .right_margin   = 20,
 667                 .upper_margin   = 18 - 3,
 668                 .vsync_len      = 3,
 669                 .lower_margin   = 4,
 670                 .sync           = FB_SYNC_CLK_LAT_FALL,
 671         },
 672         {
 673                 /* Emerging ET0430G0DH6 480 x 272 display.
 674                  * 95.04 mm x 53.856 mm display area.
 675                  */
 676                 .name           = "ET0430",
 677                 .refresh        = 60,
 678                 .xres           = 480,
 679                 .yres           = 272,
 680                 .pixclock       = KHZ2PICOS(9000),
 681                 .left_margin    = 2,
 682                 .hsync_len      = 41,
 683                 .right_margin   = 2,
 684                 .upper_margin   = 2,
 685                 .vsync_len      = 10,
 686                 .lower_margin   = 2,
 687                 .sync           = FB_SYNC_CLK_LAT_FALL,
 688         },
 689         {
 690                 /* Emerging ET0500G0DH6 800 x 480 display.
 691                  * 109.6 mm x 66.4 mm display area.
 692                  */
 693                 .name           = "ET0500",
 694                 .refresh        = 60,
 695                 .xres           = 800,
 696                 .yres           = 480,
 697                 .pixclock       = KHZ2PICOS(33260),
 698                 .left_margin    = 216 - 128,
 699                 .hsync_len      = 128,
 700                 .right_margin   = 1056 - 800 - 216,
 701                 .upper_margin   = 35 - 2,
 702                 .vsync_len      = 2,
 703                 .lower_margin   = 525 - 480 - 35,
 704                 .sync           = FB_SYNC_CLK_LAT_FALL,
 705         },
 706         {
 707                 /* Emerging ETQ570G0DH6 320 x 240 display.
 708                  * 115.2 mm x 86.4 mm display area.
 709                  */
 710                 .name           = "ETQ570",
 711                 .refresh        = 60,
 712                 .xres           = 320,
 713                 .yres           = 240,
 714                 .pixclock       = KHZ2PICOS(6400),
 715                 .left_margin    = 38,
 716                 .hsync_len      = 30,
 717                 .right_margin   = 30,
 718                 .upper_margin   = 16, /* 15 according to datasheet */
 719                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 720                 .lower_margin   = 4, /* 4.5 according to datasheet */
 721                 .sync           = FB_SYNC_CLK_LAT_FALL,
 722         },
 723         {
 724                 /* Emerging ET0700G0DH6 800 x 480 display.
 725                  * 152.4 mm x 91.44 mm display area.
 726                  */
 727                 .name           = "ET0700",
 728                 .refresh        = 60,
 729                 .xres           = 800,
 730                 .yres           = 480,
 731                 .pixclock       = KHZ2PICOS(33260),
 732                 .left_margin    = 216 - 128,
 733                 .hsync_len      = 128,
 734                 .right_margin   = 1056 - 800 - 216,
 735                 .upper_margin   = 35 - 2,
 736                 .vsync_len      = 2,
 737                 .lower_margin   = 525 - 480 - 35,
 738                 .sync           = FB_SYNC_CLK_LAT_FALL,
 739         },
 740 #else
 741         {
 742                 /* HannStar HSD100PXN1
 743                  * 202.7m mm x 152.06 mm display area.
 744                  */
 745                 .name           = "HSD100PXN1",
 746                 .refresh        = 60,
 747                 .xres           = 1024,
 748                 .yres           = 768,
 749                 .pixclock       = KHZ2PICOS(65000),
 750                 .left_margin    = 0,
 751                 .hsync_len      = 0,
 752                 .right_margin   = 320,
 753                 .upper_margin   = 0,
 754                 .vsync_len      = 0,
 755                 .lower_margin   = 38,
 756                 .sync           = FB_SYNC_CLK_LAT_FALL,
 757         },
 758 #endif
 759         {
 760                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 761                 .refresh        = 60,
 762                 .left_margin    = 48,
 763                 .hsync_len      = 96,
 764                 .right_margin   = 16,
 765                 .upper_margin   = 31,
 766                 .vsync_len      = 2,
 767                 .lower_margin   = 12,
 768                 .sync           = FB_SYNC_CLK_LAT_FALL,
 769         },
 770 };
 771
 772 static int lcd_enabled = 1;
 773
 774 void lcd_enable(void)
 775 {
 776         /* HACK ALERT:
 777          * global variable from common/lcd.c
 778          * Set to 0 here to prevent messages from going to LCD
 779          * rather than serial console
 780          */
 781         lcd_is_enabled = 0;
 782
 783         if (lcd_enabled) {
 784                 karo_load_splashimage(1);
 785
 786                 debug("Switching LCD on\n");
 787                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 788                 udelay(100);
 789                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 790                 udelay(300000);
 791                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, is_lvds());
 792         }
 793 }
 794
 795 void lcd_disable(void)
 796 {
 797         if (lcd_enabled) {
 798                 printf("Disabling LCD\n");
 799                 ipuv3_fb_shutdown();
 800         }
 801 }
 802
 803 void lcd_panel_disable(void)
 804 {
 805         if (lcd_enabled) {
 806                 debug("Switching LCD off\n");
 807                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, !is_lvds());
 808                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
 809                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
 810         }
 811 }
 812
 813 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 814         /* LCD RESET */
 815         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
 816         /* LCD POWER_ENABLE */
 817         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
 818         /* LCD Backlight (PWM) */
 819         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
 820
 821         /* Display */
 822 #ifndef CONFIG_SYS_LVDS_IF
 823         /* LCD option */
 824         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 825         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 826         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 827         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 828         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 829         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 830         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 831         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 832         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 833         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 834         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 835         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 836         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 837         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 838         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 839         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 840         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 841         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 842         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 843         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 844         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 845         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 846         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 847         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 848         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 849         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 850         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 851         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 852 #else
 853         /* LVDS option */
 854         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 855         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 856         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 857         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 858         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 859         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 860         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 861         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 862         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 863         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 864 #endif
 865 };
 866
 867 static const struct gpio stk5_lcd_gpios[] = {
 868         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 869         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 870         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 871 };
 872
 873 void lcd_ctrl_init(void *lcdbase)
 874 {
 875         int color_depth = 24;
 876         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 877         const char *vm;
 878         unsigned long val;
 879         int refresh = 60;
 880         struct fb_videomode *p = &tx53_fb_modes[0];
 881         struct fb_videomode fb_mode;
 882         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 883         int pix_fmt;
 884         int lcd_bus_width;
 885         ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
 886         unsigned long di_clk_rate = 65000000;
 887
 888         if (!lcd_enabled) {
 889                 debug("LCD disabled\n");
 890                 return;
 891         }
 892
 893         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 894                 debug("Disabling LCD\n");
 895                 lcd_enabled = 0;
 896                 setenv("splashimage", NULL);
 897                 return;
 898         }
 899
 900         karo_fdt_move_fdt();
 901
 902         if (video_mode == NULL) {
 903                 debug("Disabling LCD\n");
 904                 lcd_enabled = 0;
 905                 return;
 906         }
 907         vm = video_mode;
 908         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 909                 p = &fb_mode;
 910                 debug("Using video mode from FDT\n");
 911                 vm += strlen(vm);
 912                 if (fb_mode.xres > panel_info.vl_col ||
 913                         fb_mode.yres > panel_info.vl_row) {
 914                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 915                                 fb_mode.xres, fb_mode.yres,
 916                                 panel_info.vl_col, panel_info.vl_row);
 917                         lcd_enabled = 0;
 918                         return;
 919                 }
 920         }
 921         if (p->name != NULL)
 922                 debug("Trying compiled-in video modes\n");
 923         while (p->name != NULL) {
 924                 if (strcmp(p->name, vm) == 0) {
 925                         debug("Using video mode: '%s'\n", p->name);
 926                         vm += strlen(vm);
 927                         break;
 928                 }
 929                 p++;
 930         }
 931         if (*vm != '\0')
 932                 debug("Trying to decode video_mode: '%s'\n", vm);
 933         while (*vm != '\0') {
 934                 if (*vm >= '0' && *vm <= '9') {
 935                         char *end;
 936
 937                         val = simple_strtoul(vm, &end, 0);
 938                         if (end > vm) {
 939                                 if (!xres_set) {
 940                                         if (val > panel_info.vl_col)
 941                                                 val = panel_info.vl_col;
 942                                         p->xres = val;
 943                                         panel_info.vl_col = val;
 944                                         xres_set = 1;
 945                                 } else if (!yres_set) {
 946                                         if (val > panel_info.vl_row)
 947                                                 val = panel_info.vl_row;
 948                                         p->yres = val;
 949                                         panel_info.vl_row = val;
 950                                         yres_set = 1;
 951                                 } else if (!bpp_set) {
 952                                         switch (val) {
 953                                         case 32:
 954                                         case 24:
 955                                                 if (is_lvds())
 956                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 957                                                 /* fallthru */
 958                                         case 16:
 959                                         case 8:
 960                                                 color_depth = val;
 961                                                 break;
 962
 963                                         case 18:
 964                                                 if (is_lvds()) {
 965                                                         color_depth = val;
 966                                                         break;
 967                                                 }
 968                                                 /* fallthru */
 969                                         default:
 970                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 971                                                         end - vm, vm, color_depth);
 972                                         }
 973                                         bpp_set = 1;
 974                                 } else if (!refresh_set) {
 975                                         refresh = val;
 976                                         refresh_set = 1;
 977                                 }
 978                         }
 979                         vm = end;
 980                 }
 981                 switch (*vm) {
 982                 case '@':
 983                         bpp_set = 1;
 984                         /* fallthru */
 985                 case '-':
 986                         yres_set = 1;
 987                         /* fallthru */
 988                 case 'x':
 989                         xres_set = 1;
 990                         /* fallthru */
 991                 case 'M':
 992                 case 'R':
 993                         vm++;
 994                         break;
 995
 996                 default:
 997                         if (*vm != '\0')
 998                                 vm++;
 999                 }
1000         }
1001         if (p->xres == 0 || p->yres == 0) {
1002                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1003                 lcd_enabled = 0;
1004                 printf("Supported video modes are:");
1005                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
1006                         printf(" %s", p->name);
1007                 }
1008                 printf("\n");
1009                 return;
1010         }
1011         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1012                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1013                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1014                 lcd_enabled = 0;
1015                 return;
1016         }
1017         panel_info.vl_col = p->xres;
1018         panel_info.vl_row = p->yres;
1019
1020         switch (color_depth) {
1021         case 8:
1022                 panel_info.vl_bpix = LCD_COLOR8;
1023                 break;
1024         case 16:
1025                 panel_info.vl_bpix = LCD_COLOR16;
1026                 break;
1027         default:
1028                 panel_info.vl_bpix = LCD_COLOR24;
1029         }
1030
1031         p->pixclock = KHZ2PICOS(refresh *
1032                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1033                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1034                                 1000);
1035         debug("Pixel clock set to %lu.%03lu MHz\n",
1036                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1037
1038         if (p != &fb_mode) {
1039                 int ret;
1040
1041                 debug("Creating new display-timing node from '%s'\n",
1042                         video_mode);
1043                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1044                 if (ret)
1045                         printf("Failed to create new display-timing node from '%s': %d\n",
1046                                 video_mode, ret);
1047         }
1048
1049         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1050         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1051                                         ARRAY_SIZE(stk5_lcd_pads));
1052
1053         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1054         switch (lcd_bus_width) {
1055         case 24:
1056                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1057                 break;
1058
1059         case 18:
1060                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1061                 break;
1062
1063         case 16:
1064                 if (!is_lvds()) {
1065                         pix_fmt = IPU_PIX_FMT_RGB565;
1066                         break;
1067                 }
1068                 /* fallthru */
1069         default:
1070                 lcd_enabled = 0;
1071                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1072                         lcd_bus_width);
1073                 return;
1074         }
1075         if (is_lvds()) {
1076                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1077                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1078                 uint32_t gpr2;
1079
1080                 if (lvds_chan_mask == 0) {
1081                         printf("No LVDS channel active\n");
1082                         lcd_enabled = 0;
1083                         return;
1084                 }
1085
1086                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1087                 if (lcd_bus_width == 24)
1088                         gpr2 |= (1 << 5) | (1 << 7);
1089                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1090                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1091                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1092                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1093         }
1094         if (karo_load_splashimage(0) == 0) {
1095                 int ret;
1096
1097                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1098
1099                 debug("Initializing LCD controller\n");
1100                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1101                 if (ret) {
1102                         printf("Failed to initialize FB driver: %d\n", ret);
1103                         lcd_enabled = 0;
1104                 }
1105         } else {
1106                 debug("Skipping initialization of LCD controller\n");
1107         }
1108 }
1109 #else
1110 #define lcd_enabled 0
1111 #endif /* CONFIG_LCD */
1112
1113 static void stk5_board_init(void)
1114 {
1115         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1116         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1117 }
1118
1119 static void stk5v3_board_init(void)
1120 {
1121         stk5_board_init();
1122 }
1123
1124 static void stk5v5_board_init(void)
1125 {
1126         stk5_board_init();
1127
1128         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1129                         "Flexcan Transceiver");
1130         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1131 }
1132
1133 static void tx53_set_cpu_clock(void)
1134 {
1135         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1136
1137         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1138                 return;
1139
1140         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1141                 return;
1142
1143         if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1144                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1145                 printf("CPU clock set to %lu.%03lu MHz\n",
1146                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1147         } else {
1148                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1149         }
1150 }
1151
1152 static void tx53_init_mac(void)
1153 {
1154         u8 mac[ETH_ALEN];
1155
1156         imx_get_mac_from_fuse(0, mac);
1157         if (!is_valid_ether_addr(mac)) {
1158                 printf("No valid MAC address programmed\n");
1159                 return;
1160         }
1161
1162         printf("MAC addr from fuse: %pM\n", mac);
1163         eth_setenv_enetaddr("ethaddr", mac);
1164 }
1165
1166 int board_late_init(void)
1167 {
1168         int ret = 0;
1169         const char *baseboard;
1170
1171         tx53_set_cpu_clock();
1172         karo_fdt_move_fdt();
1173
1174         baseboard = getenv("baseboard");
1175         if (!baseboard)
1176                 goto exit;
1177
1178         printf("Baseboard: %s\n", baseboard);
1179
1180         if (strncmp(baseboard, "stk5", 4) == 0) {
1181                 if ((strlen(baseboard) == 4) ||
1182                         strcmp(baseboard, "stk5-v3") == 0) {
1183                         stk5v3_board_init();
1184                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1185                         const char *otg_mode = getenv("otg_mode");
1186
1187                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1188                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1189                                         otg_mode, baseboard);
1190                                 setenv("otg_mode", "none");
1191                         }
1192                         stk5v5_board_init();
1193                 } else {
1194                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1195                                 baseboard + 4);
1196                 }
1197         } else {
1198                 printf("WARNING: Unsupported baseboard: '%s'\n",
1199                         baseboard);
1200                 ret = -EINVAL;
1201         }
1202
1203 exit:
1204         tx53_init_mac();
1205
1206         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1207         clear_ctrlc();
1208         return ret;
1209 }
1210
1211 int checkboard(void)
1212 {
1213         tx53_print_cpuinfo();
1214
1215         printf("Board: Ka-Ro TX53-x%d3%s\n",
1216                 is_lvds(), TX53_MOD_SUFFIX);
1217
1218         return 0;
1219 }
1220
1221 #if defined(CONFIG_OF_BOARD_SETUP)
1222 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1223 #include <jffs2/jffs2.h>
1224 #include <mtd_node.h>
1225 static struct node_info nodes[] = {
1226         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1227 };
1228 #else
1229 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1230 #endif
1231
1232 #ifdef CONFIG_SYS_TX53_HWREV_2
1233 static void tx53_fixup_rtc(void *blob)
1234 {
1235         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1236         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1237 }
1238 #else
1239 static inline void tx53_fixup_rtc(void *blob)
1240 {
1241 }
1242 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1243
1244 static const char *tx53_touchpanels[] = {
1245         "ti,tsc2007",
1246         "edt,edt-ft5x06",
1247         "eeti,egalax_ts",
1248 };
1249
1250 void ft_board_setup(void *blob, bd_t *bd)
1251 {
1252         const char *baseboard = getenv("baseboard");
1253         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1254         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1255
1256         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1257         fdt_fixup_ethernet(blob);
1258
1259         karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
1260                                 ARRAY_SIZE(tx53_touchpanels));
1261         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1262         karo_fdt_fixup_flexcan(blob, stk5_v5);
1263         tx53_fixup_rtc(blob);
1264         karo_fdt_update_fb_mode(blob, video_mode);
1265 }
1266 #endif /* CONFIG_OF_BOARD_SETUP */