karo: tx6: implement secure boot support
[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S
1 #include <config.h>
2 #include <asm-offsets.h>
3 #include <configs/tx6.h>
4 #include <linux/linkage.h>
5 #include <asm/arch/imx-regs.h>
6 #include <generated/asm-offsets.h>
7
8 #ifndef CCM_CCR
9 #error asm-offsets not included
10 #endif
11
12 #define DEBUG_LED_BIT           20
13 #define LED_GPIO_BASE           GPIO2_BASE_ADDR
14 #define LED_MUX_OFFSET          0x0ec
15 #define LED_MUX_MODE            0x15
16
17 #define SDRAM_CLK               CONFIG_SYS_SDRAM_CLK
18
19 #ifdef PHYS_SDRAM_2_SIZE
20 #define SDRAM_SIZE              (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
21 #else
22 #define SDRAM_SIZE              PHYS_SDRAM_1_SIZE
23 #endif
24
25 #define CPU_2_BE_32(l)                  \
26         ((((l) << 24) & 0xFF000000) |   \
27         (((l) << 8) & 0x00FF0000) |     \
28         (((l) >> 8) & 0x0000FF00) |     \
29         (((l) >> 24) & 0x000000FF))
30
31 #define CHECK_DCD_ADDR(a)       (                       \
32         ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||        \
33         ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||   \
34         ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||        \
35         ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||  \
36         ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
37         ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||     \
38         ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
39
40         .macro  mxc_dcd_item    addr, val
41         .ifne   CHECK_DCD_ADDR(\addr)
42         .word   CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
43         .else
44         .error  "Address \addr not accessible from DCD"
45         .endif
46         .endm
47
48 #define MXC_DCD_ITEM(addr, val)         mxc_dcd_item    (addr), (val)
49 #if PHYS_SDRAM_1_WIDTH == 16
50 #define MXC_DCD_ITEM_16(addr, val)              mxc_dcd_item    (addr), (val)
51 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
52 #else
53 #define MXC_DCD_ITEM_16(addr, val)
54 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
55 #endif
56 #if PHYS_SDRAM_1_WIDTH > 16
57 #define MXC_DCD_ITEM_32(addr, val)              mxc_dcd_item    (addr), (val)
58 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
59 #else
60 #define MXC_DCD_ITEM_32(addr, val)
61 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
62 #endif
63 #if PHYS_SDRAM_1_WIDTH == 64
64 #define MXC_DCD_ITEM_64(addr, val)              mxc_dcd_item    (addr), (val)
65 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
66 #else
67 #define MXC_DCD_ITEM_64(addr, val)
68 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask)
69 #endif
70
71 #define MXC_DCD_CMD_SZ_BYTE             1
72 #define MXC_DCD_CMD_SZ_SHORT            2
73 #define MXC_DCD_CMD_SZ_WORD             4
74 #define MXC_DCD_CMD_FLAG_WRITE          0x0
75 #define MXC_DCD_CMD_FLAG_CLR            0x1
76 #define MXC_DCD_CMD_FLAG_SET            0x3
77 #define MXC_DCD_CMD_FLAG_CHK_CLR        ((0 << 0) | (0 << 1))
78 #define MXC_DCD_CMD_FLAG_CHK_SET        ((0 << 0) | (1 << 1))
79 #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR    ((1 << 0) | (0 << 1))
80 #define MXC_DCD_CMD_FLAG_CHK_ANY_SET    ((1 << 0) | (1 << 1))
81
82 #define MXC_DCD_START                                                   \
83         .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
84 dcd_start:
85
86         .macro  MXC_DCD_END
87 1:
88         .ifgt   . - dcd_start - 1768
89         .error  "DCD too large!"
90         .endif
91 dcd_end:
92         .section ".pad"
93         .section ".text"
94         .endm
95
96 #define MXC_DCD_CMD_WRT(type, flags)                                    \
97 1:      .word   CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
98
99 #define MXC_DCD_CMD_CHK(type, flags, addr, mask)                        \
100 1:      .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
101                 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
102
103 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)             \
104 1:      .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
105                 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
106
107 #define MXC_DCD_CMD_NOP()                               \
108 1:      .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
109
110
111 #define CK_TO_NS(ck)    (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
112 #define NS_TO_CK(ns)    (((ns) * SDRAM_CLK + 999) / 1000)
113 #define NS_TO_CK10(ns)  DIV_ROUND_UP(NS_TO_CK(ns), 10)
114
115         .macro          CK_VAL, name, clks, offs, max
116         .iflt           \clks - \offs
117         .set            \name, 0
118         .else
119         .ifle           \clks - \offs - \max
120         .set            \name, \clks - \offs
121         .else
122         .error          "Value \clks out of range for parameter \name"
123         .endif
124         .endif
125         .endm
126
127         .macro          NS_VAL, name, ns, offs, max
128         .iflt           \ns - \offs
129         .set            \name, 0
130         .else
131         CK_VAL          \name, NS_TO_CK(\ns), \offs, \max
132         .endif
133         .endm
134
135         .macro          CK_MAX, name, ck1, ck2, offs, max
136         .ifgt           \ck1 - \ck2
137         CK_VAL          \name, \ck1, \offs, \max
138         .else
139         CK_VAL          \name, \ck2, \offs, \max
140         .endif
141         .endm
142
143 #define MDMISC_DDR_TYPE_DDR3            0
144 #define MDMISC_DDR_TYPE_LPDDR2          1
145 #define MDMISC_DDR_TYPE_DDR2            2
146
147 #define DIV_ROUND_UP(m,d)               (((m) + (d) - 1) / (d))
148
149 #define MDOR_CLK_PERIOD_ns              15258   /* base clock for MDOR values */
150
151 /* DDR3 SDRAM */
152 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
153 #define BANK_ADDR_BITS                  2
154 #else
155 #define BANK_ADDR_BITS                  1
156 #endif
157 #define SDRAM_BURST_LENGTH              8
158 #define RALAT                           5
159 #define WALAT                           0
160 #define BI_ON                           0
161 #define ADDR_MIRROR                     0
162 #define DDR_TYPE                        MDMISC_DDR_TYPE_DDR3
163
164 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
165 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
166 #define CL_VAL  11
167 #define CWL_VAL 8
168 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
169 #define CL_VAL  9 // or 10
170 #define CWL_VAL 7
171 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
172 #define CL_VAL  7 // or 8
173 #define CWL_VAL 6
174 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
175 #define CL_VAL  6
176 #define CWL_VAL 5
177 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
178 #define CL_VAL  5
179 #define CWL_VAL 5
180 #else
181 #error SDRAM clock out of range: 303 .. 800
182 #endif
183
184 /* MDCFG0 0x0c */
185 NS_VAL  tRFC,   160, 1, 255             /* clks - 1 (0..255) */
186 CK_MAX  tXS,    NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
187 CK_MAX  tXP,    NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
188 CK_MAX  tXPDLL, NS_TO_CK(24), 2, 1, 15  /* clks - 1 (0..15) */
189 NS_VAL  tFAW,   50, 1, 31               /* clks - 1 (0..31) */
190 CK_VAL  tCL,    CL_VAL, 3, 8            /* clks - 3 (0..8) CAS Latency */
191
192 /* MDCFG1 0x10 */
193 CK_VAL  tRCD,   NS_TO_CK10(125), 1, 7   /* clks - 1 (0..7) */ /* 12.5 */
194 CK_VAL  tRP,    NS_TO_CK10(125), 1, 7   /* clks - 1 (0..7) */ /* 12.5 */
195 NS_VAL  tRC,    50, 1, 31               /* clks - 1 (0..31) */
196 CK_VAL  tRAS,   NS_TO_CK10(375), 1, 31  /* clks - 1 (0..31) */ /* 37.5 */
197 CK_VAL  tRPA,   1, 0, 1                 /* clks     (0..1) */
198 NS_VAL  tWR,    15, 1, 15               /* clks - 1 (0..15) */
199 CK_VAL  tMRD,   4, 1, 15                /* clks - 1 (0..15) */
200 CK_VAL  tCWL,   CWL_VAL, 2, 6           /* clks - 2 (0..6) */
201
202 /* MDCFG2 0x14 */
203 CK_VAL  tDLLK,  512, 1, 511             /* clks - 1 (0..511) */
204 CK_MAX  tRTP,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
205 CK_MAX  tWTR,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
206 CK_MAX  tRRD,   NS_TO_CK(10), 4, 1, 7   /* clks - 1 (0..7) */
207
208 /* MDOR 0x30 */
209 CK_MAX  tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
210 #define tSDE_RST        (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
211 #define tRST_CKE        (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
212
213 /* MDOTC 0x08 */
214 CK_VAL  tAOFPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 8.5ns */
215 CK_VAL  tAONPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 8.5ns */
216 CK_VAL  tANPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
217 CK_VAL  tAXPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
218 CK_VAL  tODTLon tCWL, 0, 7              /* clks - 1 (0..7) */ /* CWL+AL-2 */
219 CK_VAL  tODTLoff tCWL, 0, 31            /* clks - 1 (0..31) */ /* CWL+AL-2 */
220
221 /* MDPDC 0x04 */
222 CK_MAX  tCKE,   NS_TO_CK(5), 3, 1, 7
223 CK_MAX  tCKSRX, NS_TO_CK(10), 5, 0, 7
224 CK_MAX  tCKSRE, NS_TO_CK(10), 5, 0, 7
225
226 #define PRCT            0
227 #define PWDT            5
228 #define SLOW_PD         0
229 #define BOTH_CS_PD      1
230
231 #define MDPDC_VAL_0     (       \
232         (PRCT << 28) |          \
233         (PRCT << 24) |          \
234         (tCKE << 16) |          \
235         (SLOW_PD << 7) |        \
236         (BOTH_CS_PD << 6) |     \
237         (tCKSRX << 3) |         \
238         (tCKSRE << 0)           \
239         )
240
241 #define MDPDC_VAL_1     (MDPDC_VAL_0 |          \
242         (PWDT << 12) |                          \
243         (PWDT << 8)                             \
244         )
245
246 #define ROW_ADDR_BITS                   14
247 #define COL_ADDR_BITS                   10
248
249 #define Rtt_Nom                         1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
250 #define Rtt_WR                          0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
251 #define DLL_DISABLE                     0
252
253         .iflt   tWR - 7
254         .set    mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ |    \
255                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
256                         ((tWR + 1 - 4) << 9) |                          \
257                         ((((tCL + 3) - 4) & 0x7) << 4) |                \
258                         ((((tCL + 3) - 4) & 0x8) >> 1))
259         .else
260         .set    mr0_val, ((1 << 8) /* DLL Reset */ |                    \
261                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
262                         (((tWR + 1) / 2) << 9) |        \
263                         ((((tCL + 3) - 4) & 0x7) << 4) | \
264                         ((((tCL + 3) - 4) & 0x8) >> 1))
265         .endif
266
267 #define mr1_val                         (                                       \
268                                          ((Rtt_Nom & 1) << 2) |                 \
269                                          (((Rtt_Nom >> 1) & 1) << 6) |          \
270                                          (((Rtt_Nom >> 2) & 1) << 9) |          \
271                                          (DLL_DISABLE << 0) |                   \
272                                         0)
273 #define mr2_val                         (                                       \
274                                          (Rtt_WR << 9) /* dynamic ODT */ |      \
275                                          (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
276                                          (1 << 6) | /* ASR: Automatic Self Refresh */ \
277                                          (((tCWL + 2) - 5) << 3) |              \
278                                         0)
279 #define mr3_val                         0
280
281 #define MDSCR_MRS_VAL(cs, mr, val)      (((val) << 16) |                \
282                                         (1 << 15) /* CON_REQ */ |       \
283                                         (3 << 4) /* MRS command */ |    \
284                                         ((cs) << 3) |                   \
285                                         ((mr) << 0) |                   \
286                                         0)
287
288 #define MDCFG0_VAL      (       \
289         (tRFC << 24) |          \
290         (tXS << 16) |           \
291         (tXP << 13) |           \
292         (tXPDLL << 9) |         \
293         (tFAW << 4) |           \
294         (tCL << 0))             \
295
296 #define MDCFG1_VAL      (       \
297         (tRCD << 29) |          \
298         (tRP << 26) |           \
299         (tRC << 21) |           \
300         (tRAS << 16) |          \
301         (tRPA << 15) |          \
302         (tWR << 9) |            \
303         (tMRD << 5) |           \
304         (tCWL << 0))            \
305
306 #define MDCFG2_VAL      (       \
307         (tDLLK << 16) |         \
308         (tRTP << 6) |           \
309         (tWTR << 3) |           \
310         (tRRD << 0))
311
312 #define BURST_LEN               (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
313
314 #define MDCTL_VAL               (((ROW_ADDR_BITS - 11) << 24) |         \
315                                 ((COL_ADDR_BITS - 9) << 20) |           \
316                                 (BURST_LEN << 19) |                     \
317                                 ((PHYS_SDRAM_1_WIDTH / 32) << 16) |     \
318                                 ((-1) << (32 - BANK_ADDR_BITS)))
319
320 #define MDMISC_VAL              ((ADDR_MIRROR << 19) |  \
321                                 (WALAT << 16) |         \
322                                 (BI_ON << 12) |         \
323                                 (0x3 << 9) |            \
324                                 (RALAT << 6) |          \
325                                 (DDR_TYPE << 3))
326
327 #define MDOR_VAL                ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
328
329 #define MDOTC_VAL               ((tAOFPD << 27) |       \
330                                 (tAONPD << 24) |        \
331                                 (tANPD << 20) |         \
332                                 (tAXPD << 16) |         \
333                                 (tODTLon << 12) |       \
334                                 (tODTLoff << 4))
335
336         .section ".ivt"
337 ivt_header:
338         .word   CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
339 app_start_addr:
340         .long   _start
341         .long   0x0
342 dcd_ptr:
343         .long   dcd_hdr
344 boot_data_ptr:
345         .word   boot_data
346 self_ptr:
347         .word   ivt_header
348 app_code_csf:
349 #ifdef CONFIG_SECURE_BOOT
350         .word   __csf_data
351 #else
352         .word   0x0
353 #endif
354         .word   0x0
355 boot_data:
356         .long   CONFIG_SYS_TEXT_BASE
357 image_len:
358         .long   __uboot_img_len
359 plugin:
360         .word   0
361 ivt_end:
362 #define DCD_VERSION     0x40
363
364 #define DDR_SEL_VAL     3 /* DDR3 */
365 #if PHYS_SDRAM_1_WIDTH == 16
366 #define DSE1_VAL        6 /* Drive Strength for DATA lines */
367 #define DSE2_VAL        6 /* Drive Strength for ADDR/CMD lines */
368 #else
369 #define DSE1_VAL        6 /* Drive Strength for DATA lines */
370 #define DSE2_VAL        6 /* Drive Strength for ADDR/CMD lines */
371 #endif
372 #define ODT_VAL         2
373 #define DDR_PKE_VAL     0
374
375 #define DDR_SEL_SHIFT   18
376 #define DDR_MODE_SHIFT  17
377 #define ODT_SHIFT       8
378 #define DSE_SHIFT       3
379 #define HYS_SHIFT       16
380 #define PKE_SHIFT       12
381 #define PUE_SHIFT       13
382 #define PUS_SHIFT       14
383
384 #define DDR_SEL_MASK    (DDR_SEL_VAL << DDR_SEL_SHIFT)
385 #define DDR_MODE_MASK   (1 << DDR_MODE_SHIFT) /* differential input mode */
386 #define DSE1_MASK       (DSE1_VAL << DSE_SHIFT)
387 #define DSE2_MASK       (DSE2_VAL << DSE_SHIFT)
388 #define ODT_MASK        (ODT_VAL << ODT_SHIFT)
389 #define DDR_PKE_MASK    (DDR_PKE_VAL << PKE_SHIFT)
390
391 #define DQM_MASK        (DDR_MODE_MASK | DSE2_MASK)
392 #define SDQS_MASK       DSE2_MASK
393 #define SDODT_MASK      (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
394 #define SDCLK_MASK      (DDR_MODE_MASK | DSE2_MASK)
395 #define SDCKE_MASK      ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
396 #define DDR_ADDR_MASK   (ODT_MASK | DDR_MODE_MASK)
397 #define DDR_CTRL_MASK   (DDR_MODE_MASK | DSE2_MASK)
398
399 #define MMDC1_MDCTL                             0x021b0000
400 #define MMDC1_MDPDC                             0x021b0004
401 #define MMDC1_MDOTC                             0x021b0008
402 #define MMDC1_MDCFG0                            0x021b000c
403 #define MMDC1_MDCFG1                            0x021b0010
404 #define MMDC1_MDCFG2                            0x021b0014
405 #define MMDC1_MDMISC                            0x021b0018
406 #define MMDC1_MDSCR                             0x021b001c
407 #define MMDC1_MDREF                             0x021b0020
408 #define MMDC1_MDRWD                             0x021b002c
409 #define MMDC1_MDOR                              0x021b0030
410 #define MMDC1_MDASP                             0x021b0040
411 #define MMDC1_MAPSR                             0x021b0404
412 #define MMDC1_MPZQHWCTRL                        0x021b0800
413 #define MMDC1_MPWLGCR                           0x021b0808
414 #define MMDC1_MPWLDECTRL0                       0x021b080c
415 #define MMDC1_MPWLDECTRL1                       0x021b0810
416 #define MMDC1_MPWLDLST                          0x021b0814
417 #define MMDC1_MPODTCTRL                         0x021b0818
418 #define MMDC1_MPRDDQBY0DL                       0x021b081c
419 #define MMDC1_MPRDDQBY1DL                       0x021b0820
420 #define MMDC1_MPRDDQBY2DL                       0x021b0824
421 #define MMDC1_MPRDDQBY3DL                       0x021b0828
422 #define MMDC1_MPDGCTRL0                         0x021b083c
423 #define MMDC1_MPDGCTRL1                         0x021b0840
424 #define MMDC1_MPDGDLST0                         0x021b0844
425 #define MMDC1_MPRDDLCTL                         0x021b0848
426 #define MMDC1_MPRDDLST                          0x021b084c
427 #define MMDC1_MPWRDLCTL                         0x021b0850
428 #define MMDC1_MPWRDLST                          0x021b0854
429 #define MMDC1_MPRDDLHWCTL                       0x021b0860
430 #define MMDC1_MPWRDLHWCTL                       0x021b0864
431 #define MMDC1_MPPDCMPR2                         0x021b0890
432 #define MMDC1_MPSWDRDR0                         0x021b0898
433 #define MMDC1_MPSWDRDR1                         0x021b089c
434 #define MMDC1_MPSWDRDR2                         0x021b08a0
435 #define MMDC1_MPSWDRDR3                         0x021b08a4
436 #define MMDC1_MPSWDRDR4                         0x021b08a8
437 #define MMDC1_MPSWDRDR5                         0x021b08ac
438 #define MMDC1_MPSWDRDR6                         0x021b08b0
439 #define MMDC1_MPSWDRDR7                         0x021b08b4
440 #define MMDC1_MPMUR0                            0x021b08b8
441
442 #if PHYS_SDRAM_1_WIDTH == 64
443 #define MMDC2_MDPDC                             0x021b4004
444 #define MMDC2_MPWLGCR                           0x021b4808
445 #define MMDC2_MPWLDECTRL0                       0x021b480c
446 #define MMDC2_MPWLDECTRL1                       0x021b4810
447 #define MMDC2_MPWLDLST                          0x021b4814
448 #define MMDC2_MPODTCTRL                         0x021b4818
449 #define MMDC2_MPRDDQBY0DL                       0x021b481c
450 #define MMDC2_MPRDDQBY1DL                       0x021b4820
451 #define MMDC2_MPRDDQBY2DL                       0x021b4824
452 #define MMDC2_MPRDDQBY3DL                       0x021b4828
453 #define MMDC2_MPDGCTRL0                         0x021b483c
454 #define MMDC2_MPDGCTRL1                         0x021b4840
455 #define MMDC2_MPDGDLST0                         0x021b4844
456 #define MMDC2_MPRDDLCTL                         0x021b4848
457 #define MMDC2_MPRDDLST                          0x021b484c
458 #define MMDC2_MPWRDLCTL                         0x021b4850
459 #define MMDC2_MPWRDLST                          0x021b4854
460 #define MMDC2_MPRDDLHWCTL                       0x021b4860
461 #define MMDC2_MPWRDLHWCTL                       0x021b4864
462 #define MMDC2_MPRDDLHWST0                       0x021b4868
463 #define MMDC2_MPRDDLHWST1                       0x021b486c
464 #define MMDC2_MPWRDLHWST0                       0x021b4870
465 #define MMDC2_MPWRDLHWST1                       0x021b4874
466 #define MMDC2_MPWLHWERR                         0x021b4878
467 #define MMDC2_MPDGHWST0                         0x021b487c
468 #define MMDC2_MPDGHWST1                         0x021b4880
469 #define MMDC2_MPDGHWST2                         0x021b4884
470 #define MMDC2_MPDGHWST3                         0x021b4888
471 #define MMDC2_MPSWDAR0                          0x021b4894
472 #define MMDC2_MPSWDRDR0                         0x021b4898
473 #define MMDC2_MPSWDRDR1                         0x021b489c
474 #define MMDC2_MPSWDRDR2                         0x021b48a0
475 #define MMDC2_MPSWDRDR3                         0x021b48a4
476 #define MMDC2_MPSWDRDR4                         0x021b48a8
477 #define MMDC2_MPSWDRDR5                         0x021b48ac
478 #define MMDC2_MPSWDRDR6                         0x021b48b0
479 #define MMDC2_MPSWDRDR7                         0x021b48b4
480 #endif
481
482 #ifdef CONFIG_SOC_MX6Q
483 #define IOMUXC_GPR1                             0x020e0004
484 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e024c
485 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e02a8
486 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e02ac
487 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e02c0
488 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e02c4
489 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e02d4
490 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e02d8
491 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02dc
492 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02e0
493 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e02e4
494 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e02ec
495 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e02f4
496 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e02f8
497 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e02fc
498 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0300
499 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e0304
500 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0308
501 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e030c
502 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0310
503 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e0314
504 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e0318
505 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e050c
506 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0510
507 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0514
508 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e0518
509 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e051c
510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e0520
511 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e0524
512 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0528
513 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e052c
514 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0530
515 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0534
516 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0538
517 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e053c
518 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0540
519 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0544
520 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0548
521 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e054c
522 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0550
523 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e0554
524 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0558
525 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e055c
526 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0560
527 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e0564
528 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0568
529 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e056c
530 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0578
531 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e057c
532 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0580
533 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e0584
534 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e0588
535 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e058c
536 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e0590
537 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e0594
538 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e0598
539 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e059c
540 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e05a0
541 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e05a8
542 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e05ac
543 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e05b0
544 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e05b4
545 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e05b8
546 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e05bc
547 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e05c0
548 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e05c4
549 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
550 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
551 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
552 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0         0x020e0754
553 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0758
554 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1         0x020e075c
555 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2         0x020e0760
556 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3         0x020e0764
557 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0768
558 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4         0x020e076c
559 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e0770
560 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0774
561 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5         0x020e0778
562 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6         0x020e077c
563 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7         0x020e0780
564 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
565 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
566 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
567 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
568 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
569 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
570 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
571 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
572 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
573 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
574 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
575 #endif
576
577 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
578 #define IOMUXC_GPR1                             0x020e0004
579 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e0218
580 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e0330
581 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e032c
582 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e0314
583 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e0318
584 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e0270
585 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e026c
586 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02a8
587 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02a4
588 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e0274
589 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e027c
590 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e033c
591 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e0338
592 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e0284
593 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0288
594 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e028c
595 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0290
596 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e0294
597 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0298
598 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e029c
599 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e02a0
600 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e04d0
601 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0484
602 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0480
603 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e04cc
604 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e04c8
605 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e047c
606 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e04c4
607 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0478
608 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e0424
609 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0428
610 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0444
611 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0448
612 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e044c
613 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0450
614 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0454
615 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0458
616 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e045c
617 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0460
618 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e042c
619 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0430
620 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e0434
621 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0438
622 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e043c
623 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0440
624 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e0464
625 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0490
626 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e0494
627 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0498
628 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e049c
629 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e04ac
630 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e04a0
631 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e04a4
632 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e04b0
633 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e04a8
634 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e04b4
635 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e04b8
636 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e04bc
637 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e0470
638 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e04c0
639 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e0474
640 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e04d4
641 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e0488
642 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e04d8
643 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e048c
644 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
645 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
646 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
647 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0754
648 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0758
649 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e075c
650 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0760
651 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
652 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
653 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
654 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
655 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
656 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
657 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
658 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
659 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
660 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e08f8
661 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e08fc
662 #endif
663
664 dcd_hdr:
665         MXC_DCD_START
666         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
667         /* RESET_OUT GPIO_7_12 */
668         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
669
670         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */
671         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */
672         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
673
674         MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
675
676         /* enable all relevant clocks... */
677         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
678         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
679         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
680         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
681         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
682         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
683         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
684         MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
685         MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
686         MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
687
688         /* IOMUX: */
689         MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
690         /* UART1 pad config */
691         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
692         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
693 #ifdef CONFIG_SOC_MX6Q
694         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
695 #else
696         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002)        /* UART1 RXD INPUT_SEL */
697 #endif
698         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0,        0x00000001)        /* UART1 CTS */
699         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1,        0x00000001)        /* UART1 RTS */
700         MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT,   0x00000003)        /* UART1 RTS INPUT_SEL */
701
702 #ifdef CONFIG_NAND_MXS
703         /* NAND */
704         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE,    0x00000000)     /* NANDF_CLE: NANDF_CLE */
705         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE,    0x00000000)     /* NANDF_ALE: NANDF_ALE */
706         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B,   0x00000000)     /* NANDF_WP_B: NANDF_WPn */
707         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY,  0x00000000)     /* NANDF_RB0: NANDF_READY0 */
708         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B,  0x00000000)     /* NANDF_CS0: NANDF_CS0 */
709         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD,     0x00000001)     /* SD4_CMD: NANDF_RDn */
710         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK,     0x00000001)     /* SD4_CLK: NANDF_WRn */
711         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000)     /* NANDF_D0: NANDF_D0 */
712         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000)     /* NANDF_D1: NANDF_D1 */
713         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000)     /* NANDF_D2: NANDF_D2 */
714         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000)     /* NANDF_D3: NANDF_D3 */
715         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000)     /* NANDF_D4: NANDF_D4 */
716         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000)     /* NANDF_D5: NANDF_D5 */
717         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000)     /* NANDF_D6: NANDF_D6 */
718         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000)     /* NANDF_D7: NANDF_D7 */
719 #endif
720         /* ext. mem CS */
721         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000)      /* NANDF_CS2: NANDF_CS2 */
722         /* DRAM_DQM[0..7] */
723         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
724         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
725         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
726         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
727         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
728         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
729         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
730         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
731
732         /* DRAM_A[0..15] */
733         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
734         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
735         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
736         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
737         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
738         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
739         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
740         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
741         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
742         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
743         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
744         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
745         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
746         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
747         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
748         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
749         /* DRAM_CAS */
750         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
751         /* DRAM_RAS */
752         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
753         /* DRAM_SDCLK[0..1] */
754         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
755         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
756         /* DRAM_RESET */
757         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
758         /* DRAM_SDCKE[0..1] */
759         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
760         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
761         /* DRAM_SDBA[0..2] */
762         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
763         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
764         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
765         /* DRAM_SDODT[0..1] */
766         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
767         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
768         /* DRAM_B[0..7]DS */
769         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK)
770         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK)
771         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE1_MASK)
772         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE1_MASK)
773         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE1_MASK)
774         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE1_MASK)
775         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE1_MASK)
776         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE1_MASK)
777         /* ADDDS */
778         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK)
779         /* DDRMODE_CTL */
780         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
781         /* DDRPKE */
782         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
783         /* DDRMODE */
784         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
785         /* CTLDS */
786         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK)
787         /* DDR_TYPE */
788         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
789         /* DDRPK */
790         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
791         /* DDRHYS */
792         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
793
794 #ifdef CONFIG_SOC_MX6Q
795         /* TERM_CTL[0..7] */
796         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
797         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
798         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
799         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
800         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
801         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
802         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
803         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
804 #endif
805         /* SDRAM initialization */
806         /* MPRDDQBY[0..7]DL */
807         MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
808         MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
809         MXC_DCD_ITEM_32(MMDC1_MPRDDQBY2DL, 0x33333333)
810         MXC_DCD_ITEM_32(MMDC1_MPRDDQBY3DL, 0x33333333)
811         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
812         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
813         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
814         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
815         /* MDMISC */
816         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
817         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
818         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
819
820         /* MSDSCR Conf Req */
821         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
822         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
823         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
824
825         /* MDCTL */
826         MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
827         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
828         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
829
830         MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
831         MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
832         MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
833         MXC_DCD_ITEM(MMDC1_MDRWD,  0x000026d2)
834         MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
835         MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
836         MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
837         MXC_DCD_ITEM_64(MMDC2_MDPDC,  MDPDC_VAL_0)
838         MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)
839
840         /* CS0 MRS: */
841         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
842         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
843         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
844         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
845 #if BANK_ADDR_BITS > 1
846         /* CS1 MRS: */
847         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
848         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
849         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
850         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
851 #endif
852
853         MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
854         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
855
856         MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222)
857         MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
858
859         /* DDR3 calibration */
860         MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
861         MXC_DCD_ITEM(MMDC1_MAPSR,     0x00001007)
862
863         /* ZQ calibration */
864         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
865         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
866         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
867
868         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
869         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
870
871         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
872
873 #define WL_DLY_DQS_VAL  30
874 #define WL_DLY_DQS0     (WL_DLY_DQS_VAL + 0)
875 #define WL_DLY_DQS1     (WL_DLY_DQS_VAL + 0)
876 #define WL_DLY_DQS2     (WL_DLY_DQS_VAL + 0)
877 #define WL_DLY_DQS3     (WL_DLY_DQS_VAL + 0)
878 #define WL_DLY_DQS4     (WL_DLY_DQS_VAL + 0)
879 #define WL_DLY_DQS5     (WL_DLY_DQS_VAL + 0)
880 #define WL_DLY_DQS6     (WL_DLY_DQS_VAL + 0)
881 #define WL_DLY_DQS7     (WL_DLY_DQS_VAL + 0)
882         /* Write leveling */
883         MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
884         MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
885         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
886         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
887
888 #if PHYS_SDRAM_1_WIDTH > 16
889 #define DO_DDR_CALIB
890 #endif
891         /* DQS gating calibration */
892         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
893 #if BANK_ADDR_BITS > 1
894         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
895 #endif
896         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
897         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
898         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
899         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
900         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
901         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
902         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
903         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
904
905         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
906         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
907
908         MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
909         MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
910         MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
911         MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
912 #ifdef DO_DDR_CALIB
913         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
914         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
915         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
916         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
917         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
918         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
919         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
920         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000)
921         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
922 #else /* DO_DDR_CALIB */
923 #define MPMUR_FRC_MSR   (1 << 11)
924         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160)
925         MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f)
926         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
927         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
928 #endif /* DO_DDR_CALIB */
929         /* DRAM_SDQS[0..7] pad config */
930         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
931         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
932         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
933         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
934         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
935         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
936         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
937         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
938 #ifdef DO_DDR_CALIB
939         /* Read delay calibration */
940         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
941         MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
942         MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
943         MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000013)
944         MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
945         MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
946         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
947 #else /* DO_DDR_CALIB */
948         MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x4a4f4e4c)
949         MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x4e50504a)
950 #endif /* DO_DDR_CALIB */
951 #ifdef DO_DDR_CALIB
952         /* Write delay calibration */
953         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
954         MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
955         MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
956         MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
957 #if PHYS_SDRAM_1_WIDTH == 64
958         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
959
960         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
961         MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
962         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
963 #endif
964         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
965 #else /* DO_DDR_CALIB */
966         MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f)
967         MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f)
968         MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
969 #endif /* DO_DDR_CALIB */
970         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
971 #if BANK_ADDR_BITS > 1
972         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
973 #endif
974         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
975         MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
976         MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006)
977         MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
978         MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1)
979
980         /* MDSCR: Normal operation */
981         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
982         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
983         MXC_DCD_END