karo: tx6ul: disable the PMIC for '_noenv' U-Boot
[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S
1 #include <config.h>
2 #include <asm-offsets.h>
3 #include <configs/tx6.h>
4 #include <linux/linkage.h>
5 #include <asm/arch/imx-regs.h>
6 #include <generated/asm-offsets.h>
7
8 #ifndef CCM_CCR
9 #error asm-offsets not included
10 #endif
11
12 #define DEBUG_LED_BIT           20
13 #define LED_GPIO_BASE           GPIO2_BASE_ADDR
14 #define LED_MUX_OFFSET          0x0ec
15 #define LED_MUX_MODE            0x15
16
17 #define SDRAM_CLK               CONFIG_SYS_SDRAM_CLK
18
19 #ifdef PHYS_SDRAM_2_SIZE
20 #define SDRAM_SIZE              ((PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) / SZ_1M)
21 #else
22 #define SDRAM_SIZE              (PHYS_SDRAM_1_SIZE / SZ_1M)
23 #endif
24
25 #define BIT(x)                  (1 << (x))
26 #define CCGR(m)                 (3 << ((m) * 2))
27
28 #define CPU_2_BE_32(l)                  \
29         ((((l) << 24) & 0xFF000000) |   \
30         (((l) << 8) & 0x00FF0000) |     \
31         (((l) >> 8) & 0x0000FF00) |     \
32         (((l) >> 24) & 0x000000FF))
33
34 #ifndef CONFIG_TX6QP
35 #define CHECK_DCD_ADDR(a)       (                                       \
36         ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||        \
37         ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||           \
38         ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||        \
39         ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||          \
40         ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ ||         \
41         ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||     \
42         ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
43         ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
44 #else
45 #define CHECK_DCD_ADDR(a)       (                                       \
46         ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||        \
47         ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||           \
48         ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||        \
49         ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||          \
50         ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ ||         \
51         ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||     \
52         ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
53         ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */ ||         \
54         ((a) >= 0x00BB0000 && (a) <= 0x00BB003F) /* NoC DDR config */)
55 #endif
56
57         .macro  mxc_dcd_item    addr, val
58         .ifne   CHECK_DCD_ADDR(\addr)
59         .word   CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
60         .else
61         .error  "Address \addr not accessible from DCD"
62         .endif
63         .endm
64
65 #define MXC_DCD_ITEM(addr, val)         mxc_dcd_item    (addr), (val)
66 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
67 #define MXC_DCD_ITEM_16(addr, val)      mxc_dcd_item    (addr), (val)
68 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
69 #else
70 #define MXC_DCD_ITEM_16(addr, val)
71 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
72 #endif
73 #if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
74 #define MXC_DCD_ITEM_32(addr, val)      mxc_dcd_item    (addr), (val)
75 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
76 #else
77 #define MXC_DCD_ITEM_32(addr, val)
78 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
79 #endif
80 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
81 #define MXC_DCD_ITEM_64(addr, val)      mxc_dcd_item    (addr), (val)
82 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
83 #else
84 #define MXC_DCD_ITEM_64(addr, val)
85 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask)
86 #endif
87
88 #define MXC_DCD_CMD_SZ_BYTE             1
89 #define MXC_DCD_CMD_SZ_SHORT            2
90 #define MXC_DCD_CMD_SZ_WORD             4
91 #define MXC_DCD_CMD_FLAG_WRITE          0x0
92 #define MXC_DCD_CMD_FLAG_CLR            0x1
93 #define MXC_DCD_CMD_FLAG_SET            0x3
94 #define MXC_DCD_CMD_FLAG_CHK_CLR        ((0 << 0) | (0 << 1))
95 #define MXC_DCD_CMD_FLAG_CHK_SET        ((0 << 0) | (1 << 1))
96 #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR    ((1 << 0) | (0 << 1))
97 #define MXC_DCD_CMD_FLAG_CHK_ANY_SET    ((1 << 0) | (1 << 1))
98
99 #define MXC_DCD_START                                                   \
100         .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
101 dcd_start:
102
103         .macro  MXC_DCD_END
104 1:
105         .ifgt   . - dcd_start - 1768
106         .error  "DCD too large!"
107         .endif
108 dcd_end:
109         .section ".pad"
110         .section ".text"
111         .endm
112
113 #define MXC_DCD_CMD_WRT(type, flags)                                    \
114 1:      .word   CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
115
116 #define MXC_DCD_CMD_CHK(type, flags, addr, mask)                        \
117 1:      .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
118                 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
119
120 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)             \
121 1:      .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
122                 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
123
124 #define MXC_DCD_CMD_NOP()                               \
125 1:      .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
126
127
128 #define CK_TO_NS(ck)    (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
129 #define NS_TO_CK(ns)    (((ns) * SDRAM_CLK + 999) / 1000)
130 #define NS_TO_CK10(ns)  DIV_ROUND_UP(NS_TO_CK(ns), 10)
131 #define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100)
132 #define PS_TO_CK(ps)    DIV_ROUND_UP(NS_TO_CK(ps), 1000)
133
134         .macro          CK_VAL, name, clks, offs, max
135         .iflt           \clks - \offs
136         .set            \name, 0
137         .else
138         .ifle           \clks - \offs - \max
139         .set            \name, \clks - \offs
140         .else
141         .error          "Value \clks out of range for parameter \name"
142         .endif
143         .endif
144         .endm
145
146         .macro          NS_VAL, name, ns, offs, max
147         .iflt           \ns - \offs
148         .set            \name, 0
149         .else
150         CK_VAL          \name, NS_TO_CK(\ns), \offs, \max
151         .endif
152         .endm
153
154         .macro          CK_MAX, name, ck1, ck2, offs, max
155         .ifgt           \ck1 - \ck2
156         CK_VAL          \name, \ck1, \offs, \max
157         .else
158         CK_VAL          \name, \ck2, \offs, \max
159         .endif
160         .endm
161
162 #define MDMISC_DDR_TYPE_DDR3            0
163 #define MDMISC_DDR_TYPE_LPDDR2          1
164 #define MDMISC_DDR_TYPE_DDR2            2
165
166 #define DIV_ROUND_UP(m,d)               (((m) + (d) - 1) / (d))
167
168 #define MDOR_CLK_PERIOD_ns              15258   /* base clock for MDOR values */
169
170 /* DDR3 SDRAM */
171 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
172 #define BANK_ADDR_BITS                  2
173 #else
174 #define BANK_ADDR_BITS                  1
175 #endif
176 #define SDRAM_BURST_LENGTH              8
177 #define RALAT                           5
178 #define WALAT                           0
179 #define BI_ON                           0
180 #define ADDR_MIRROR                     0
181 #define DDR_TYPE                        MDMISC_DDR_TYPE_DDR3
182
183 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII or MT41K128M16JT-125 */
184 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
185 #define CL_VAL  11
186 #define CWL_VAL 8
187 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
188 #define CL_VAL  9 // or 10
189 #define CWL_VAL 7
190 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
191 #define CL_VAL  7 // or 8
192 #define CWL_VAL 6
193 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
194 #define CL_VAL  6
195 #define CWL_VAL 5
196 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
197 #define CL_VAL  5
198 #define CWL_VAL 5
199 #else
200 #error SDRAM clock out of range: 303 .. 800
201 #endif
202
203 #if SDRAM_SIZE < 2048
204 #define ROW_ADDR_BITS                   14
205 #define COL_ADDR_BITS                   10
206
207 /* MDCFG0 0x0c */
208 NS_VAL  tRFC,   160, 1, 255             /* clks - 1 (0..255) */
209 CK_MAX  tXS,    NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
210 CK_MAX  tXP,    NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) (MT41K128M16JT: 6ns) */
211 CK_MAX  tXPDLL, NS_TO_CK(24), 10, 1, 15 /* clks - 1 (0..15) */
212 NS_VAL  tFAW,   50, 1, 31               /* clks - 1 (0..31) (MT41K128M16JT: 30ns) */
213 CK_VAL  tCL,    CL_VAL, 3, 8            /* clks - 3 (0..8) CAS Latency */
214
215 /* MDCFG1 0x10 */
216 CK_VAL  tRCD,   PS_TO_CK(13750), 1, 7   /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
217 CK_VAL  tRP,    PS_TO_CK(13750), 1, 7   /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
218 NS_VAL  tRC,    50, 1, 31               /* clks - 1 (0..31) (MT41K128M16JT: 49ns) */
219 CK_VAL  tRAS,   NS_TO_CK10(375), 1, 31  /* clks - 1 (0..31) (MT41K128M16JT: 3.5ns) */
220 CK_VAL  tRPA,   1, 0, 1                 /* clks     (0..1) */
221 NS_VAL  tWR,    15, 1, 15               /* clks - 1 (0..15) */
222 CK_VAL  tMRD,   4, 1, 15                /* clks - 1 (0..15) */
223 CK_VAL  tCWL,   CWL_VAL, 2, 6           /* clks - 2 (0..6) */
224
225 /* MDCFG2 0x14 */
226 CK_VAL  tDLLK,  512, 1, 511             /* clks - 1 (0..511) */ /* (Jedec Standard) */
227 CK_MAX  tRTP,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
228 CK_MAX  tWTR,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
229 CK_MAX  tRRD,   NS_TO_CK(10), 4, 1, 7   /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */
230
231 /* MDOR 0x30 */
232 CK_MAX  tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
233 #else
234 /* 4096MiB SDRAM: IM4G16D3EABG-125I */
235 #define ROW_ADDR_BITS                   15
236 #define COL_ADDR_BITS                   10
237
238 /* MDCFG0 0x0c */
239 NS_VAL  tRFC,   260, 1, 255             /* clks - 1 (0..255) */
240 CK_MAX  tXS,    NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
241 CK_MAX  tXP,    NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
242 CK_MAX  tXPDLL, NS_TO_CK(24), 2, 1, 15  /* clks - 1 (0..15) */
243 NS_VAL  tFAW,   30, 1, 31               /* clks - 1 (0..31) */
244 CK_VAL  tCL,    CL_VAL, 3, 8            /* clks - 3 (0..8) CAS Latency */
245
246 /* MDCFG1 0x10 */
247 CK_VAL  tRCD,   NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
248 CK_VAL  tRP,    NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
249 CK_VAL  tRC,    NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */
250 CK_VAL  tRAS,   NS_TO_CK(35), 1, 31     /* clks - 1 (0..31) */ /* 35 */
251 CK_VAL  tRPA,   1, 0, 1                 /* clks     (0..1) */
252 NS_VAL  tWR,    15, 1, 15               /* clks - 1 (0..15) */
253 CK_VAL  tMRD,   4, 1, 15                /* clks - 1 (0..15) */
254 CK_VAL  tCWL,   CWL_VAL, 2, 6           /* clks - 2 (0..6) */
255
256 /* MDCFG2 0x14 */
257 CK_VAL  tDLLK,  512, 1, 511             /* clks - 1 (0..511) */
258 CK_MAX  tRTP,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
259 CK_MAX  tWTR,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
260 CK_MAX  tRRD,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
261
262 /* MDOR 0x30 */
263 CK_MAX  tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
264 #endif
265
266 #define tSDE_RST        (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
267 #define tRST_CKE        (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
268
269 /* MDOTC 0x08 */
270 CK_VAL  tAOFPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
271 CK_VAL  tAONPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
272 CK_VAL  tANPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
273 CK_VAL  tAXPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
274 CK_VAL  tODTLon tCWL, 0, 7              /* clks - 1 (0..7) */ /* CWL+AL-2 */
275 CK_VAL  tODTLoff tCWL, 0, 31            /* clks - 1 (0..31) */ /* CWL+AL-2 */
276
277 /* MDPDC 0x04 */
278 CK_MAX  tCKE,   NS_TO_CK(5), 3, 1, 7
279 CK_MAX  tCKSRX, NS_TO_CK(10), 5, 0, 7
280 CK_MAX  tCKSRE, NS_TO_CK(10), 5, 0, 7
281
282 #define PRCT            0
283 #define PWDT            5
284 #define SLOW_PD         0
285 #define BOTH_CS_PD      1
286
287 #define MDPDC_VAL_0     (       \
288         (PRCT << 28) |          \
289         (PRCT << 24) |          \
290         (tCKE << 16) |          \
291         (SLOW_PD << 7) |        \
292         (BOTH_CS_PD << 6) |     \
293         (tCKSRX << 3) |         \
294         (tCKSRE << 0)           \
295         )
296
297 #define MDPDC_VAL_1     (MDPDC_VAL_0 |          \
298         (PWDT << 12) |                          \
299         (PWDT << 8)                             \
300         )
301
302 #define Rtt_Nom                         1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
303 #define Rtt_WR                          0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
304 #define DLL_DISABLE                     0
305
306         .iflt   tWR - 7
307         .set    mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ |    \
308                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
309                         ((tWR + 1 - 4) << 9) |                          \
310                         ((((tCL + 3) - 4) & 0x7) << 4) |                \
311                         ((((tCL + 3) - 4) & 0x8) >> 1))
312         .else
313         .set    mr0_val, ((1 << 8) /* DLL Reset */ |                    \
314                         (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
315                         (((tWR + 1) / 2) << 9) |        \
316                         ((((tCL + 3) - 4) & 0x7) << 4) | \
317                         ((((tCL + 3) - 4) & 0x8) >> 1))
318         .endif
319
320 #define mr1_val                         (                                       \
321                                          ((Rtt_Nom & 1) << 2) |                 \
322                                          (((Rtt_Nom >> 1) & 1) << 6) |          \
323                                          (((Rtt_Nom >> 2) & 1) << 9) |          \
324                                          (DLL_DISABLE << 0) |                   \
325                                         0)
326 #define mr2_val                         (                                       \
327                                          (Rtt_WR << 9) /* dynamic ODT */ |      \
328                                          (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
329                                          (1 << 6) | /* ASR: Automatic Self Refresh */ \
330                                          (((tCWL + 2) - 5) << 3) |              \
331                                         0)
332 #define mr3_val                         0
333
334 #define MDSCR_MRS_VAL(cs, mr, val)      (((val) << 16) |                \
335                                         (1 << 15) /* CON_REQ */ |       \
336                                         (3 << 4) /* MRS command */ |    \
337                                         ((cs) << 3) |                   \
338                                         ((mr) << 0) |                   \
339                                         0)
340
341 #define MDCFG0_VAL      (       \
342         (tRFC << 24) |          \
343         (tXS << 16) |           \
344         (tXP << 13) |           \
345         (tXPDLL << 9) |         \
346         (tFAW << 4) |           \
347         (tCL << 0))             \
348
349 #define MDCFG1_VAL      (       \
350         (tRCD << 29) |          \
351         (tRP << 26) |           \
352         (tRC << 21) |           \
353         (tRAS << 16) |          \
354         (tRPA << 15) |          \
355         (tWR << 9) |            \
356         (tMRD << 5) |           \
357         (tCWL << 0))            \
358
359 #define MDCFG2_VAL      (       \
360         (tDLLK << 16) |         \
361         (tRTP << 6) |           \
362         (tWTR << 3) |           \
363         (tRRD << 0))
364
365 #define BURST_LEN               (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
366
367 #define MDCTL_VAL               (((ROW_ADDR_BITS - 11) << 24) |         \
368                                 ((COL_ADDR_BITS - 9) << 20) |           \
369                                 (BURST_LEN << 19) |                     \
370                                 ((CONFIG_SYS_SDRAM_BUS_WIDTH / 32) << 16) | \
371                                 ((-1) << (32 - BANK_ADDR_BITS)))
372
373 #define MDMISC_WALAT(n)         (((n) & 3) << 16)
374 #define MDMISC_RALAT(n)         (((n) & 7) << 6)
375
376 #define MDMISC_VAL              ((ADDR_MIRROR << 19) |  \
377                                 MDMISC_WALAT(WALAT) |   \
378                                 (BI_ON << 12) |         \
379                                 (0x3 << 9) |            \
380                                 MDMISC_RALAT(RALAT) |   \
381                                 (DDR_TYPE << 3))
382
383 #define MDOR_VAL                ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
384
385 #define MDOTC_VAL               ((tAOFPD << 27) |       \
386                                 (tAONPD << 24) |        \
387                                 (tANPD << 20) |         \
388                                 (tAXPD << 16) |         \
389                                 (tODTLon << 12) |       \
390                                 (tODTLoff << 4))
391
392         .section ".ivt"
393 ivt_header:
394         .word   CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
395 app_start_addr:
396         .long   _start
397         .long   0x0
398 dcd_ptr:
399         .long   dcd_hdr
400 boot_data_ptr:
401         .word   boot_data
402 self_ptr:
403         .word   ivt_header
404 app_code_csf:
405 #ifdef CONFIG_SECURE_BOOT
406         .word   __csf_data
407 #else
408         .word   0x0
409 #endif
410         .word   0x0
411 boot_data:
412         .long   CONFIG_SYS_TEXT_BASE
413 image_len:
414         .long   __uboot_img_len
415 plugin:
416         .word   0
417 ivt_end:
418 #define DCD_VERSION     0x40
419
420 #define DDR_SEL_VAL     3 /* DDR3 */
421 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
422 #define DSE1_VAL        6 /* Drive Strength for DATA lines */
423 #define DSE2_VAL        6 /* Drive Strength for ADDR/CMD lines */
424 #else
425 #define DSE1_VAL        6 /* Drive Strength for DATA lines */
426 #define DSE2_VAL        6 /* Drive Strength for ADDR/CMD lines */
427 #endif
428 #define ODT_VAL         2
429 #define DDR_PKE_VAL     0
430
431 #define DDR_SEL_SHIFT   18
432 #define DDR_MODE_SHIFT  17
433 #define ODT_SHIFT       8
434 #define DSE_SHIFT       3
435 #define HYS_SHIFT       16
436 #define PKE_SHIFT       12
437 #define PUE_SHIFT       13
438 #define PUS_SHIFT       14
439
440 #define DDR_SEL_MASK    (DDR_SEL_VAL << DDR_SEL_SHIFT)
441 #define DDR_MODE_MASK   (1 << DDR_MODE_SHIFT) /* differential input mode */
442 #define DSE1_MASK       (DSE1_VAL << DSE_SHIFT)
443 #define DSE2_MASK       (DSE2_VAL << DSE_SHIFT)
444 #define ODT_MASK        (ODT_VAL << ODT_SHIFT)
445 #define DDR_PKE_MASK    (DDR_PKE_VAL << PKE_SHIFT)
446
447 #define DQM_MASK        (DDR_MODE_MASK | DSE2_MASK)
448 #define SDQS_MASK       DSE2_MASK
449 #define SDODT_MASK      (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
450 #define SDCLK_MASK      (DDR_MODE_MASK | DSE2_MASK)
451 #define SDCKE_MASK      ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
452 #define DDR_ADDR_MASK   (ODT_MASK | DDR_MODE_MASK)
453 #define DDR_CTRL_MASK   (DDR_MODE_MASK | DSE2_MASK)
454
455 #define MMDC1_MDCTL                             0x021b0000
456 #define MMDC1_MDPDC                             0x021b0004
457 #define MMDC1_MDOTC                             0x021b0008
458 #define MMDC1_MDCFG0                            0x021b000c
459 #define MMDC1_MDCFG1                            0x021b0010
460 #define MMDC1_MDCFG2                            0x021b0014
461 #define MMDC1_MDMISC                            0x021b0018
462 #define MMDC1_MDSCR                             0x021b001c
463 #define MMDC1_MDREF                             0x021b0020
464 #define MMDC1_MDRWD                             0x021b002c
465 #define MMDC1_MDOR                              0x021b0030
466 #define MMDC1_MDASP                             0x021b0040
467
468 #define MMDC1_MAARCR                            0x021b0400
469 #define MMDC1_MAPSR                             0x021b0404
470 #define MMDC1_MADPCR0                           0x021b0410
471
472 #define MMDC1_MPZQHWCTRL                        0x021b0800
473 #define MMDC1_MPWLGCR                           0x021b0808
474 #define MMDC1_MPWLDECTRL0                       0x021b080c
475 #define MMDC1_MPWLDECTRL1                       0x021b0810
476 #define MMDC1_MPWLDLST                          0x021b0814
477 #define MMDC1_MPODTCTRL                         0x021b0818
478 #define MMDC1_MPRDDQBY0DL                       0x021b081c
479 #define MMDC1_MPRDDQBY1DL                       0x021b0820
480 #define MMDC1_MPRDDQBY2DL                       0x021b0824
481 #define MMDC1_MPRDDQBY3DL                       0x021b0828
482 #define MMDC1_MPDGCTRL0                         0x021b083c
483 #define MMDC1_MPDGCTRL1                         0x021b0840
484 #define MMDC1_MPDGDLST0                         0x021b0844
485 #define MMDC1_MPRDDLCTL                         0x021b0848
486 #define MMDC1_MPRDDLST                          0x021b084c
487 #define MMDC1_MPWRDLCTL                         0x021b0850
488 #define MMDC1_MPWRDLST                          0x021b0854
489 #define MMDC1_MPRDDLHWCTL                       0x021b0860
490 #define MMDC1_MPWRDLHWCTL                       0x021b0864
491 #define MMDC1_MPDGHWST0                         0x021b087c
492 #define MMDC1_MPDGHWST1                         0x021b0880
493 #define MMDC1_MPPDCMPR2                         0x021b0890
494 #define MMDC1_MPDGHWST2                         0x021b0884
495 #define MMDC1_MPDGHWST3                         0x021b0888
496 #define MMDC1_MPSWDRDR0                         0x021b0898
497 #define MMDC1_MPSWDRDR1                         0x021b089c
498 #define MMDC1_MPSWDRDR2                         0x021b08a0
499 #define MMDC1_MPSWDRDR3                         0x021b08a4
500 #define MMDC1_MPSWDRDR4                         0x021b08a8
501 #define MMDC1_MPSWDRDR5                         0x021b08ac
502 #define MMDC1_MPSWDRDR6                         0x021b08b0
503 #define MMDC1_MPSWDRDR7                         0x021b08b4
504 #define MMDC1_MPMUR0                            0x021b08b8
505
506 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
507 #define MMDC2_MPWLGCR                           0x021b4808
508 #define MMDC2_MPWLDECTRL0                       0x021b480c
509 #define MMDC2_MPWLDECTRL1                       0x021b4810
510 #define MMDC2_MPWLDLST                          0x021b4814
511 #define MMDC2_MPODTCTRL                         0x021b4818
512 #define MMDC2_MPRDDQBY0DL                       0x021b481c
513 #define MMDC2_MPRDDQBY1DL                       0x021b4820
514 #define MMDC2_MPRDDQBY2DL                       0x021b4824
515 #define MMDC2_MPRDDQBY3DL                       0x021b4828
516 #define MMDC2_MPDGCTRL0                         0x021b483c
517 #define MMDC2_MPDGCTRL1                         0x021b4840
518 #define MMDC2_MPDGDLST0                         0x021b4844
519 #define MMDC2_MPRDDLCTL                         0x021b4848
520 #define MMDC2_MPRDDLST                          0x021b484c
521 #define MMDC2_MPWRDLCTL                         0x021b4850
522 #define MMDC2_MPWRDLST                          0x021b4854
523 #define MMDC2_MPRDDLHWCTL                       0x021b4860
524 #define MMDC2_MPWRDLHWCTL                       0x021b4864
525 #define MMDC2_MPRDDLHWST0                       0x021b4868
526 #define MMDC2_MPRDDLHWST1                       0x021b486c
527 #define MMDC2_MPWRDLHWST0                       0x021b4870
528 #define MMDC2_MPWRDLHWST1                       0x021b4874
529 #define MMDC2_MPWLHWERR                         0x021b4878
530 #define MMDC2_MPDGHWST0                         0x021b487c
531 #define MMDC2_MPDGHWST1                         0x021b4880
532 #define MMDC2_MPDGHWST2                         0x021b4884
533 #define MMDC2_MPDGHWST3                         0x021b4888
534 #define MMDC2_MPSWDAR0                          0x021b4894
535 #define MMDC2_MPSWDRDR0                         0x021b4898
536 #define MMDC2_MPSWDRDR1                         0x021b489c
537 #define MMDC2_MPSWDRDR2                         0x021b48a0
538 #define MMDC2_MPSWDRDR3                         0x021b48a4
539 #define MMDC2_MPSWDRDR4                         0x021b48a8
540 #define MMDC2_MPSWDRDR5                         0x021b48ac
541 #define MMDC2_MPSWDRDR6                         0x021b48b0
542 #define MMDC2_MPSWDRDR7                         0x021b48b4
543 #define MMDC2_MPMUR0                            0x021b48b8
544 #endif
545
546 #ifdef CONFIG_SOC_MX6Q
547 #define IOMUXC_GPR0                             0x020e0000
548 #define IOMUXC_GPR1                             0x020e0004
549 #define IOMUXC_GPR2                             0x020e0008
550 #define IOMUXC_GPR3                             0x020e000c
551 #define IOMUXC_GPR4                             0x020e0010
552 #define IOMUXC_GPR5                             0x020e0014
553 #define IOMUXC_GPR6                             0x020e0018
554 #define IOMUXC_GPR7                             0x020e001c
555 #define IOMUXC_GPR8                             0x020e0020
556 #define IOMUXC_GPR9                             0x020e0024
557 #define IOMUXC_GPR10                            0x020e0028
558 #define IOMUXC_GPR11                            0x020e002c
559 #define IOMUXC_GPR12                            0x020e0030
560 #define IOMUXC_GPR13                            0x020e0034
561 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20        0x020e00a0
562 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
563 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
564 #define IOMUXC_SW_MUX_CTL_PAD_GPIO16            0x020e0248
565 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e024c
566 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e02a8
567 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e02ac
568 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e02c0
569 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e02c4
570 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2         0x020e02c8
571 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e02d4
572 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e02d8
573 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02dc
574 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02e0
575 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e02e4
576 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e02ec
577 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e02f4
578 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e02f8
579 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e02fc
580 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0300
581 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e0304
582 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0308
583 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e030c
584 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0310
585 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e0314
586 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e0318
587
588 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20        0x020e03b4
589 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
590 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
591 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e050c
592 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0510
593 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0514
594 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e0518
595 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e051c
596 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e0520
597 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e0524
598 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0528
599 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e052c
600 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0530
601 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0534
602 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0538
603 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e053c
604 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0540
605 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0544
606 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0548
607 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e054c
608 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0550
609 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e0554
610 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0558
611 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e055c
612 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0560
613 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e0564
614 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0568
615 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e056c
616 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0578
617 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e057c
618 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0580
619 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e0584
620 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e0588
621 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e058c
622 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e0590
623 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e0594
624 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e0598
625 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e059c
626 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e05a0
627 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e05a8
628 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e05ac
629 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e05b0
630 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e05b4
631 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e05b8
632 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e05bc
633 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e05c0
634 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e05c4
635 #define IOMUXC_SW_PAD_CTL_PAD_GPIO16            0x020e0618
636 #define IOMUXC_SW_PAD_CTL_PAD_GPIO17            0x020e061c
637 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2         0x020e06b0
638 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
639 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
640 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
641 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0         0x020e0754
642 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0758
643 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1         0x020e075c
644 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2         0x020e0760
645 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3         0x020e0764
646 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0768
647 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4         0x020e076c
648 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e0770
649 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0774
650 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5         0x020e0778
651 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6         0x020e077c
652 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7         0x020e0780
653 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
654 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
655 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
656 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
657 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
658 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
659 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
660 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
661 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
662
663 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
664 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
665
666 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
667 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
668 #define TX6_I2C1_SEL_INP_VAL                    0
669 #elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
670 #define IOMUXC_GPR1                             0x020e0004
671 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20        0x020e0154
672 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
673 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
674 #define IOMUXC_SW_MUX_CTL_PAD_GPIO16            0x020e0214
675 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e0218
676 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e0330
677 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e032c
678 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e0314
679 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e0318
680 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2         0x020e031c
681 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e0270
682 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e026c
683 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02a8
684 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02a4
685 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e0274
686 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e027c
687 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e033c
688 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e0338
689 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e0284
690 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0288
691 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e028c
692 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0290
693 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e0294
694 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0298
695 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e029c
696 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e02a0
697
698 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20        0x020e0524
699 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
700 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
701 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e04d0
702 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0484
703 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0480
704 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e04cc
705 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e04c8
706 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e047c
707 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e04c4
708 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0478
709 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e0424
710 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0428
711 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0444
712 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0448
713 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e044c
714 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0450
715 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0454
716 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0458
717 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e045c
718 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0460
719 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e042c
720 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0430
721 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e0434
722 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0438
723 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e043c
724 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0440
725 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e0464
726 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0490
727 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e0494
728 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0498
729 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e049c
730 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e04ac
731 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e04a0
732 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e04a4
733 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e04b0
734 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e04a8
735 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e04b4
736 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e04b8
737 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e04bc
738 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e0470
739 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e04c0
740 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e0474
741 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e04d4
742 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e0488
743 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e04d8
744 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e048c
745 #define IOMUXC_SW_PAD_CTL_PAD_GPIO16            0x020e05e4
746 #define IOMUXC_SW_PAD_CTL_PAD_GPIO17            0x020e05e8
747 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2         0x020e0704
748 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
749 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
750 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
751 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0754
752 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0758
753 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e075c
754 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0760
755 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
756 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
757 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
758 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
759 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
760 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
761 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
762 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
763 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
764
765 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e08f8
766 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e08fc
767
768 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
769 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
770 #define TX6_I2C1_SEL_INP_VAL                    1
771 #endif
772
773 dcd_hdr:
774         MXC_DCD_START
775         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
776         /* setup I2C pads for PMIC */
777         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21, 0x00000016)
778         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28, 0x00000011)
779         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, 0x0000f079)
780         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, 0x0000f079)
781         MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, TX6_I2C1_SEL_INP_VAL)
782         MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, TX6_I2C1_SEL_INP_VAL)
783
784         /* ENET_REF_CLK */
785         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO16, 0x00000012)
786         /* ETN PHY nRST */
787         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2, 0x00000015)
788         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, 0x000030b0)
789         /* ETN PHY Power */
790         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20, 0x00000015)
791         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, 0x000030b0)
792         /* RESET_OUT GPIO_7_12 */
793         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
794         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0)
795 #ifndef CONFIG_TX6_EMMC
796         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR)
797         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
798         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
799         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
800 #ifndef CONFIG_TX6QP
801         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */
802 #else
803         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x007236c1 */
804 #endif
805         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
806         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
807         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
808         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
809 #endif
810         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 (0x00029148) */
811         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 (0x00029148) */
812         MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
813
814         /* enable all relevant clocks... */
815         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
816         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* 0xf0c03f3f default: 0xf0c03f0f APBH-DMA */
817         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* 0xf0fc0c00 default: 0xf0fc0000 ENET */
818         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(3)) /* 0xfc3fc0cc default: 0xfc3fc00c I2C1 */
819 //      MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR()) /* 0x3ff00000 default: 0x3ff0000f */
820         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* 0xff00ff00 default: 0x0000ff00 GPMI BCH */
821         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(13) | CCGR(12)) /* 0xff033f3f default: 0xf0033f3f UART1 */
822         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(4) | CCGR(3) | CCGR(2) | CCGR(1)) /* 0xffff03ff default: 0xffff0000 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) USDHC1 USDHC1 */
823         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
824         MXC_DCD_ITEM(0x020c80a0, 0x00082029) /* set video PLL to 498MHz */
825         MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
826         MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
827
828         /* IOMUX: */
829         MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
830 #ifdef CONFIG_TX6QP
831         /* enable AXI cache for VDOA/VPU/IPU */
832         MXC_DCD_ITEM(IOMUXC_GPR4, 0xf00000cf)
833         /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
834         MXC_DCD_ITEM(IOMUXC_GPR6, 0x77177717)
835         MXC_DCD_ITEM(IOMUXC_GPR7, 0x77177717)
836 #endif
837         /* UART1 pad config */
838         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
839         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
840 #ifdef CONFIG_SOC_MX6Q
841         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
842 #else
843         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002)        /* UART1 RXD INPUT_SEL */
844 #endif
845         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0,        0x00000001)        /* UART1 CTS */
846         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1,        0x00000001)        /* UART1 RTS */
847         MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT,   0x00000003)        /* UART1 RTS INPUT_SEL */
848
849 #ifdef CONFIG_NAND_MXS
850         /* NAND */
851         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE,    0x00000000)     /* NANDF_CLE: NANDF_CLE */
852         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE,    0x00000000)     /* NANDF_ALE: NANDF_ALE */
853         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B,   0x00000000)     /* NANDF_WP_B: NANDF_WPn */
854         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY,  0x00000000)     /* NANDF_RB0: NANDF_READY0 */
855         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B,  0x00000000)     /* NANDF_CS0: NANDF_CS0 */
856         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD,     0x00000001)     /* SD4_CMD: NANDF_RDn */
857         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK,     0x00000001)     /* SD4_CLK: NANDF_WRn */
858         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000)     /* NANDF_D0: NANDF_D0 */
859         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000)     /* NANDF_D1: NANDF_D1 */
860         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000)     /* NANDF_D2: NANDF_D2 */
861         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000)     /* NANDF_D3: NANDF_D3 */
862         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000)     /* NANDF_D4: NANDF_D4 */
863         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000)     /* NANDF_D5: NANDF_D5 */
864         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000)     /* NANDF_D6: NANDF_D6 */
865         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000)     /* NANDF_D7: NANDF_D7 */
866 #endif
867         /* ext. mem CS */
868         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000)      /* NANDF_CS2: NANDF_CS2 */
869         /* DRAM_DQM[0..7] */
870         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
871         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
872         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
873         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
874         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
875         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
876         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
877         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
878
879         /* DRAM_A[0..15] */
880         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
881         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
882         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
883         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
884         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
885         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
886         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
887         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
888         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
889         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
890         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
891         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
892         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
893         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
894         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
895         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
896         /* DRAM_CAS */
897         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
898         /* DRAM_RAS */
899         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
900         /* DRAM_SDCLK[0..1] */
901         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
902         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
903         /* DRAM_RESET */
904         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
905         /* DRAM_SDCKE[0..1] */
906         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
907         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
908         /* DRAM_SDBA[0..2] */
909         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
910         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
911         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
912         /* DRAM_SDODT[0..1] */
913         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
914         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
915         /* DRAM_B[0..7]DS */
916         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK)
917         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK)
918         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE1_MASK)
919         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE1_MASK)
920         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE1_MASK)
921         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE1_MASK)
922         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE1_MASK)
923         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE1_MASK)
924         /* ADDDS */
925         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK)
926         /* DDRMODE_CTL */
927         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
928         /* DDRPKE */
929         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
930         /* DDRMODE */
931         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
932         /* CTLDS */
933         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK)
934         /* DDR_TYPE */
935         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
936         /* DDRPK */
937         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
938         /* DDRHYS */
939         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
940
941 #ifdef CONFIG_SOC_MX6Q
942         /* TERM_CTL[0..7] */
943         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
944         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
945         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
946         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
947         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
948         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
949         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
950         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
951 #endif
952 #if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
953 #define DO_DDR_CALIB
954 #endif
955         /* SDRAM initialization */
956 #define WL_DLY_DQS_VAL  30
957 #define WL_DLY_DQS0     (WL_DLY_DQS_VAL + 0)
958 #define WL_DLY_DQS1     (WL_DLY_DQS_VAL + 0)
959 #define WL_DLY_DQS2     (WL_DLY_DQS_VAL + 0)
960 #define WL_DLY_DQS3     (WL_DLY_DQS_VAL + 0)
961 #define WL_DLY_DQS4     (WL_DLY_DQS_VAL + 0)
962 #define WL_DLY_DQS5     (WL_DLY_DQS_VAL + 0)
963 #define WL_DLY_DQS6     (WL_DLY_DQS_VAL + 0)
964 #define WL_DLY_DQS7     (WL_DLY_DQS_VAL + 0)
965
966         /* ZQ calibration */
967         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
968         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
969         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
970
971         MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
972         MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
973         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
974         MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
975 #if defined(CONFIG_SOC_MX6Q)
976         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43430349)
977         MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x03330334)
978         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x434b0351)
979         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x033d030e)
980 #elif defined(CONFIG_SOC_MX6DL)
981         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x423a0236)
982         MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x02210227)
983         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x42240226)
984         MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x02120223)
985 #elif defined(CONFIG_SOC_MX6S)
986         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x42490244)
987         MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x022f0238)
988 #else
989 #error No DGCTRL settings for selected SoC
990 #endif
991         MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
992         MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
993         MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
994         MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
995
996         /* MPRDDQBY[0..7]DL */
997         MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
998         MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
999         MXC_DCD_ITEM_32(MMDC1_MPRDDQBY2DL, 0x33333333)
1000         MXC_DCD_ITEM_32(MMDC1_MPRDDQBY3DL, 0x33333333)
1001         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
1002         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
1003         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
1004         MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
1005 #define MPMUR_FRC_MSR   (1 << 11)
1006         MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
1007         MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
1008         /* MDMISC */
1009         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
1010         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
1011         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1012
1013         /* MSDSCR Conf Req */
1014         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
1015         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
1016         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1017
1018         /* MDCTL */
1019         MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
1020 #if BANK_ADDR_BITS > 1
1021         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (3 << 30))
1022 #else
1023         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (1 << 30))
1024 #endif
1025         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1026
1027         MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
1028         MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
1029         MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
1030         MXC_DCD_ITEM(MMDC1_MDRWD,  0x000026d2)
1031         MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
1032         MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
1033         MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
1034         MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)
1035
1036         /* CS0 MRS: */
1037         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
1038         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
1039         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
1040         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
1041 #if BANK_ADDR_BITS > 1
1042         /* CS1 MRS: */
1043         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
1044         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
1045         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
1046         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
1047 #endif
1048         MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
1049         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
1050
1051         MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222)
1052         MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
1053
1054         /* DDR3 calibration */
1055         MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
1056 #ifdef CONFIG_TX6QP
1057         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
1058         MXC_DCD_ITEM(MMDC1_MAARCR, BIT(25)) /* MMDC reorder disable BOOT_CFG3[5:4] */
1059         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1060 #endif
1061         MXC_DCD_ITEM(MMDC1_MAPSR, 1)
1062
1063 #ifdef DO_DDR_CALIB
1064         /* ZQ calibration */
1065         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
1066         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
1067         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
1068
1069         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
1070         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1071         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
1072 #endif
1073         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
1074 #if BANK_ADDR_BITS > 1
1075         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
1076 #endif
1077         /* DRAM_SDQS[0..7] pad config */
1078         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
1079         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
1080         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
1081         MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
1082         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
1083         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
1084         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
1085         MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
1086 #ifdef DO_DDR_CALIB
1087         /* Read delay calibration */
1088         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
1089         MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
1090         MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
1091         MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000013)
1092         MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
1093         MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
1094         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1095
1096         /* Write delay calibration */
1097         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
1098         MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
1099         MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
1100         MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
1101 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
1102         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1103
1104         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
1105         MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
1106         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
1107 #endif
1108         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
1109 #endif /* DO_DDR_CALIB */
1110         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
1111 #if BANK_ADDR_BITS > 1
1112         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
1113 #endif
1114         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
1115         MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
1116         MXC_DCD_ITEM(MMDC1_MAPSR, (16 << 8))
1117         MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
1118
1119         /* MDSCR: Normal operation */
1120         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
1121         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
1122         MXC_DCD_END