Merge remote branch 'remotes/kc/karo-tx6q' into karo-tx28-devel
[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S
1 #include <config.h>
2 #include <configs/tx6.h>
3 #include <asm/arch/imx-regs.h>
4 #include <generated/asm-offsets.h>
5
6 #ifndef CCM_CCR
7 #error asm-offsets not included
8 #endif
9
10 #define DEBUG_LED_BIT           20
11 #define LED_GPIO_BASE           GPIO2_BASE_ADDR
12 #define LED_MUX_OFFSET          0x0ec
13 #define LED_MUX_MODE            0x15
14
15 #define SDRAM_CLK               CONFIG_SYS_SDRAM_CLK
16
17 #ifdef PHYS_SDRAM_2_SIZE
18 #define SDRAM_SIZE              (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
19 #else
20 #define SDRAM_SIZE              PHYS_SDRAM_1_SIZE
21 #endif
22
23 #define CPU_2_BE_32(l)                  \
24         ((((l) << 24) & 0xFF000000) |   \
25         (((l) << 8) & 0x00FF0000) |     \
26         (((l) >> 8) & 0x0000FF00) |     \
27         (((l) >> 24) & 0x000000FF))
28
29 #define CHECK_DCD_ADDR(a)       (                       \
30         ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||        \
31         ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||   \
32         ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||        \
33         ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||  \
34         ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
35         ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||     \
36         ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
37
38         .macro  mxc_dcd_item    addr, val
39         .ifne   CHECK_DCD_ADDR(\addr)
40         .word   CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
41         .else
42         .error  "Address \addr not accessible from DCD"
43         .endif
44         .endm
45
46 #define MXC_DCD_ITEM(addr, val)         mxc_dcd_item    addr, val
47
48 #define MXC_DCD_CMD_SZ_BYTE             1
49 #define MXC_DCD_CMD_SZ_SHORT            2
50 #define MXC_DCD_CMD_SZ_WORD             4
51 #define MXC_DCD_CMD_FLAG_WRITE          0x0
52 #define MXC_DCD_CMD_FLAG_CLR            0x1
53 #define MXC_DCD_CMD_FLAG_SET            0x3
54 #define MXC_DCD_CMD_FLAG_CHK_ANY        (1 << 0)
55 #define MXC_DCD_CMD_FLAG_CHK_SET        (1 << 1)
56 #define MXC_DCD_CMD_FLAG_CHK_CLR        (0 << 1)
57
58 #define MXC_DCD_CMD_WRT(type, flags, next)                                      \
59         .word   CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
60
61 #define MXC_DCD_CMD_CHK(type, flags, addr, mask)                                \
62         .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
63                 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
64
65 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)                     \
66         .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
67                 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
68
69 #define MXC_DCD_CMD_NOP                                                         \
70         .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
71
72 #define CK_TO_NS(ck)    (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
73 #define NS_TO_CK(ns)    (((ns) * SDRAM_CLK + 999) / 1000)
74
75         .macro          CK_VAL, name, clks, offs, max
76         .iflt           \clks - \offs
77         .set            \name, 0
78         .else
79         .ifle           \clks - \offs - \max
80         .set            \name, \clks - \offs
81         .else
82         .error          "Value \clks out of range for parameter \name"
83         .endif
84         .endif
85         .endm
86
87         .macro          NS_VAL, name, ns, offs, max
88         .iflt           \ns - \offs
89         .set            \name, 0
90         .else
91         CK_VAL          \name, NS_TO_CK(\ns), \offs, \max
92         .endif
93         .endm
94
95         .macro          CK_MAX, name, ck1, ck2, offs, max
96         .ifgt           \ck1 - \ck2
97         CK_VAL          \name, \ck1, \offs, \max
98         .else
99         CK_VAL          \name, \ck2, \offs, \max
100         .endif
101         .endm
102
103 #define MDMISC_DDR_TYPE_DDR3            0
104 #define MDMISC_DDR_TYPE_LPDDR2          1
105 #define MDMISC_DDR_TYPE_DDR2            2
106
107 #define DIV_ROUND_UP(m,d)               (((m) + (d) - 1) / (d))
108
109 #define MDOR_CLK_PERIOD_ns              15258   /* base clock for MDOR values */
110
111 /* DDR3 SDRAM */
112 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
113 #define BANK_ADDR_BITS                  2
114 #else
115 #define BANK_ADDR_BITS                  1
116 #endif
117 #define SDRAM_BURST_LENGTH              8
118 #define RALAT                           5
119 #define WALAT                           0
120 #define BI_ON                           1
121 #define ADDR_MIRROR                     1
122 #define DDR_TYPE                        MDMISC_DDR_TYPE_DDR3
123
124 /* 512/1024MiB SDRAM: NT5CB128M16P-CG */
125 /* MDCFG0 0x0c */
126 NS_VAL  tRFC,   160, 1, 255             /* clks - 1 (0..255) */
127 CK_MAX  tXS,    tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
128 CK_MAX  tXP,    3, NS_TO_CK(6), 1, 7    /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
129 CK_MAX  tXPDLL, NS_TO_CK(24), 2, 1, 15  /* clks - 1 (0..15) */
130 NS_VAL  tFAW,   45, 1, 31               /* clks - 1 (0..31) */
131 CK_VAL  tCL,    8, 3, 8                 /* clks - 3 (0..8) CAS Latency */
132
133 /* MDCFG1 0x10 */
134 NS_VAL  tRCD,   14, 1, 7                /* clks - 1 (0..7) */
135 NS_VAL  tRP,    14, 1, 7                /* clks - 1 (0..7) */
136 NS_VAL  tRC,    50, 1, 31               /* clks - 1 (0..31) */
137 NS_VAL  tRAS,   36, 1, 31               /* clks - 1 (0..31) */
138 CK_VAL  tRPA,   0, 0, 1                 /* clks     (0..1) */
139 NS_VAL  tWR,    15, 1, 15               /* clks - 1 (0..15) */
140 CK_VAL  tMRD,   4, 1, 15                /* clks - 1 (0..15) */
141 CK_VAL  tCWL,   6, 2, 6                 /* clks - 2 (0..6) */
142
143 /* MDCFG2 0x14 */
144 CK_VAL  tDLLK,  512, 1, 511             /* clks - 1 (0..511) */
145 CK_MAX  tRTP,   4, NS_TO_CK(8), 1, 7    /* clks - 1 (0..7) */
146 CK_MAX  tWTR,   4, NS_TO_CK(8), 1, 7    /* clks - 1 (0..7) */
147 CK_MAX  tRRD,   4, NS_TO_CK(8), 1, 7    /* clks - 1 (0..7) */
148
149 /* MDOR 0x30 */
150 CK_MAX  tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
151 #define tSDE_RST        (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
152 #define tRST_CKE        (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
153
154 /* MDOTC 0x08 */
155 NS_VAL  tAOFPD, 9, 1, 7                 /* clks - 1 (0..7) */
156 NS_VAL  tAONPD, 9, 1, 7                 /* clks - 1 (0..7) */
157 CK_VAL  tANPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
158 CK_VAL  tAXPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
159 CK_VAL  tODTLon tCWL, 1, 7              /* clks - 1 (0..7) */
160 CK_VAL  tODTLoff tCWL, 1, 31            /* clks - 1 (0..31) */
161
162 /* MDPDC 0x04 */
163 CK_MAX  tCKE,   NS_TO_CK(6), 3, 1, 7
164 CK_MAX  tCKSRX, NS_TO_CK(10), 5, 0, 7
165 CK_MAX  tCKSRE, NS_TO_CK(10), 5, 0, 7
166
167 #define PRCT            0
168 #define PWDT            5
169 #define SLOW_PD         0
170 #define BOTH_CS_PD      1
171
172 #define MDPDC_VAL_0     (       \
173         (PRCT << 28) |          \
174         (PRCT << 24) |          \
175         (tCKE << 16) |          \
176         (SLOW_PD << 7) |        \
177         (BOTH_CS_PD << 6) |     \
178         (tCKSRX << 3) |         \
179         (tCKSRE << 0)           \
180         )
181
182 #define MDPDC_VAL_1     (MDPDC_VAL_0 |          \
183         (PWDT << 12) |                          \
184         (PWDT << 8)                             \
185         )
186
187 #define ROW_ADDR_BITS   14
188 #define COL_ADDR_BITS   10
189
190         .iflt   tWR - 7
191         .set    mr0_val, ((1 << 8) /* DLL Reset */ |    \
192                         ((tWR + 1 - 4) << 9) |          \
193                         (((tCL + 3) - 4) << 4))
194         .else
195         .set    mr0_val, ((1 << 8) /* DLL Reset */ |    \
196                         (((tWR + 1) / 2) << 9) |        \
197                         (((tCL + 3) - 4) << 4))
198         .endif
199
200 #define MDSCR_MRS_VAL(cs, mr, val)      (((val) << 16) |                \
201                                         (1 << 15) /* CON REQ */ |       \
202                                         (3 << 4) /* MRS command */ |    \
203                                         ((cs) << 3) |                   \
204                                         ((mr) << 0))
205
206 #define mr1_val                         0x0040
207 #define mr2_val                         0x0408
208
209 #define MDCFG0_VAL      (       \
210         (tRFC << 24) |          \
211         (tXS << 16) |           \
212         (tXP << 13) |           \
213         (tXPDLL << 9) |         \
214         (tFAW << 4) |           \
215         (tCL << 0))             \
216
217 #define MDCFG1_VAL      (       \
218         (tRCD << 29) |          \
219         (tRP << 26) |           \
220         (tRC << 21) |           \
221         (tRAS << 16) |          \
222         (tRPA << 15) |          \
223         (tWR << 9) |            \
224         (tMRD << 5) |           \
225         (tCWL << 0))            \
226
227 #define MDCFG2_VAL      (       \
228         (tDLLK << 16) |         \
229         (tRTP << 6) |           \
230         (tWTR << 3) |           \
231         (tRRD << 0))
232
233 #define BURST_LEN       (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
234
235 #if PHYS_SDRAM_1_WIDTH == 64
236 #define MDCTL_VAL       (((ROW_ADDR_BITS - 11) << 24) |         \
237                         ((COL_ADDR_BITS - 9) << 20) |           \
238                         (BURST_LEN << 19) |                     \
239                         (2 << 16) | /* SDRAM bus width */       \
240                         ((-1) << (32 - BANK_ADDR_BITS)))
241 #else
242 #define MDCTL_VAL       (((ROW_ADDR_BITS - 11) << 24) |         \
243                         ((COL_ADDR_BITS - 9) << 20) |           \
244                         (BURST_LEN << 19) |                     \
245                         (1 << 16) | /* SDRAM bus width */       \
246                         ((-1) << (32 - BANK_ADDR_BITS)))
247 #endif
248
249 #define MDMISC_VAL      ((ADDR_MIRROR << 19) |  \
250                         (WALAT << 16) |         \
251                         (BI_ON << 12) |         \
252                         (0x3 << 9) |            \
253                         (RALAT << 6) |          \
254                         (DDR_TYPE << 3))
255
256 #define MDOR_VAL        ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
257
258 #define MDOTC_VAL       ((tAOFPD << 27) |       \
259                         (tAONPD << 24) |        \
260                         (tANPD << 20) |         \
261                         (tAXPD << 16) |         \
262                         (tODTLon << 12) |       \
263                         (tODTLoff << 4))
264
265 fcb_start:
266         b               _start
267         .org            0x400
268 ivt_header:
269         .word           CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
270 app_start_addr:
271         .long           _start
272         .long           0x0
273 dcd_ptr:
274         .long           dcd_hdr
275 boot_data_ptr:
276         .word           boot_data
277 self_ptr:
278         .word           ivt_header
279 app_code_csf:
280         .word           0x0
281         .word           0x0
282 boot_data:
283         .long           fcb_start
284 image_len:
285         .long           CONFIG_U_BOOT_IMG_SIZE
286 plugin:
287         .word           0
288 ivt_end:
289 #define DCD_VERSION     0x40
290
291 #define CLKCTL_CCGR0    0x68
292 #define CLKCTL_CCGR1    0x6c
293 #define CLKCTL_CCGR2    0x70
294 #define CLKCTL_CCGR3    0x74
295 #define CLKCTL_CCGR4    0x78
296 #define CLKCTL_CCGR5    0x7c
297 #define CLKCTL_CCGR6    0x80
298 #define CLKCTL_CCGR7    0x84
299 #define CLKCTL_CMEOR    0x88
300
301 #define DDR_SEL_VAL     3
302 #define DSE_VAL         6
303 #define ODT_VAL         2
304
305 #define DDR_SEL_SHIFT   18
306 #define DDR_MODE_SHIFT  17
307 #define ODT_SHIFT       8
308 #define DSE_SHIFT       3
309 #define HYS_SHIFT       16
310 #define PKE_SHIFT       12
311 #define PUE_SHIFT       13
312 #define PUS_SHIFT       14
313
314 #define DDR_SEL_MASK    (DDR_SEL_VAL << DDR_SEL_SHIFT)
315 #define DDR_MODE_MASK   (1 << DDR_MODE_SHIFT)
316 #define DSE_MASK        (DSE_VAL << DSE_SHIFT)
317 #define ODT_MASK        (ODT_VAL << ODT_SHIFT)
318
319 #define DQM_MASK        (DDR_MODE_MASK | DSE_MASK)
320 #define SDQS_MASK       DSE_MASK
321 #define SDODT_MASK      (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
322 #define SDCLK_MASK      (DDR_MODE_MASK | DSE_MASK)
323 #define SDCKE_MASK      ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
324 #define DDR_ADDR_MASK   0
325 #define DDR_CTRL_MASK   (DDR_MODE_MASK | DSE_MASK)
326
327 #define MMDC1_MDCTL                             0x021b0000
328 #define MMDC1_MDPDC                             0x021b0004
329 #define MMDC1_MDOTC                             0x021b0008
330 #define MMDC1_MDCFG0                            0x021b000c
331 #define MMDC1_MDCFG1                            0x021b0010
332 #define MMDC1_MDCFG2                            0x021b0014
333 #define MMDC1_MDMISC                            0x021b0018
334 #define MMDC1_MDSCR                             0x021b001c
335 #define MMDC1_MDREF                             0x021b0020
336 #define MMDC1_MDRWD                             0x021b002c
337 #define MMDC1_MDOR                              0x021b0030
338 #define MMDC1_MDASP                             0x021b0040
339 #define MMDC1_MAPSR                             0x021b0404
340 #define MMDC1_MPZQHWCTRL                        0x021b0800
341 #define MMDC1_MPWLGCR                           0x021b0808
342 #define MMDC1_MPODTCTRL                         0x021b0818
343 #define MMDC1_MPRDDQBY0DL                       0x021b081c
344 #define MMDC1_MPRDDQBY1DL                       0x021b0820
345 #define MMDC1_MPRDDQBY2DL                       0x021b0824
346 #define MMDC1_MPRDDQBY3DL                       0x021b0828
347 #define MMDC1_MPDGCTRL0                         0x021b083c
348 #define MMDC1_MPRDDLCTL                         0x021b0848
349 #define MMDC1_MPWRDLCTL                         0x021b0850
350 #define MMDC1_MPRDDLHWCTL                       0x021b0860
351 #define MMDC1_MPWRDLHWCTL                       0x021b0864
352 #define MMDC1_MPPDCMPR2                         0x021b0890
353 #define MMDC1_MPMUR0                            0x021b08b8
354 #define MMDC2_MPZQHWCTRL                        0x021b4800
355 #define MMDC2_MPWLGCR                           0x021b4808
356 #define MMDC2_MPODTCTRL                         0x021b4818
357 #define MMDC2_MPRDDQBY0DL                       0x021b481c
358 #define MMDC2_MPRDDQBY1DL                       0x021b4820
359 #define MMDC2_MPRDDQBY2DL                       0x021b4824
360 #define MMDC2_MPRDDQBY3DL                       0x021b4828
361 #define MMDC2_MPDGCTRL0                         0x021b483c
362 #define MMDC2_MPRDDLCTL                         0x021b4848
363 #define MMDC2_MPWRDLCTL                         0x021b4850
364 #define MMDC2_MPRDDLHWCTL                       0x021b4860
365 #define MMDC2_MPWRDLHWCTL                       0x021b4864
366 #define MMDC2_MPMUR0                            0x021b48b8
367
368 #ifdef CONFIG_MX6Q
369 #define IOMUXC_GPR1                             0x020e0004
370 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e024c
371 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e02a8
372 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e02ac
373 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e02c0
374 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e02c4
375 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e02d4
376 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e02d8
377 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02dc
378 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02e0
379 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e02e4
380 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e02ec
381 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e02f4
382 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e02f8
383 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e02fc
384 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0300
385 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e0304
386 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0308
387 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e030c
388 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0310
389 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e0314
390 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e0318
391 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e050c
392 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0510
393 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0514
394 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e0518
395 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e051c
396 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e0520
397 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e0524
398 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0528
399 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e052c
400 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0530
401 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0534
402 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0538
403 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e053c
404 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0540
405 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0544
406 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0548
407 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e054c
408 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0550
409 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e0554
410 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0558
411 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e055c
412 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0560
413 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e0564
414 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0568
415 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e056c
416 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0578
417 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e057c
418 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0580
419 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e0584
420 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e0588
421 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e058c
422 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e0590
423 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e0594
424 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e0598
425 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e059c
426 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e05a0
427 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e05a8
428 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e05ac
429 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e05b0
430 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e05b4
431 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e05b8
432 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e05bc
433 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e05c0
434 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e05c4
435 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
436 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
437 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
438 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0         0x020e0754
439 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0758
440 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1         0x020e075c
441 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2         0x020e0760
442 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3         0x020e0764
443 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0768
444 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4         0x020e076c
445 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e0770
446 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0774
447 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5         0x020e0778
448 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6         0x020e077c
449 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7         0x020e0780
450 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
451 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
452 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
453 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
454 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
455 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
456 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
457 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
458 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
459 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
460 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
461 #endif
462
463 #ifdef CONFIG_MX6DL
464 #define IOMUXC_GPR1                             0x020e0004
465 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17            0x020e0218
466 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7         0x020e0330
467 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6         0x020e032c
468 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0         0x020e0314
469 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1         0x020e0318
470 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE          0x020e0270
471 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE          0x020e026c
472 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B         0x020e02a8
473 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY        0x020e02a4
474 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B        0x020e0274
475 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B        0x020e027c
476 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           0x020e033c
477 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           0x020e0338
478 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00       0x020e0284
479 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01       0x020e0288
480 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02       0x020e028c
481 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03       0x020e0290
482 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04       0x020e0294
483 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05       0x020e0298
484 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06       0x020e029c
485 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07       0x020e02a0
486 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P      0x020e04d0
487 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5         0x020e0484
488 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4         0x020e0480
489 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P      0x020e04cc
490 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P      0x020e04c8
491 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3         0x020e047c
492 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P      0x020e04c4
493 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2         0x020e0478
494 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00       0x020e0424
495 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01       0x020e0428
496 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02       0x020e0444
497 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03       0x020e0448
498 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04       0x020e044c
499 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05       0x020e0450
500 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06       0x020e0454
501 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07       0x020e0458
502 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08       0x020e045c
503 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09       0x020e0460
504 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10       0x020e042c
505 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11       0x020e0430
506 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12       0x020e0434
507 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13       0x020e0438
508 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14       0x020e043c
509 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15       0x020e0440
510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS          0x020e0464
511 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS          0x020e0490
512 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET        0x020e0494
513 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0        0x020e0498
514 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1        0x020e049c
515 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P     0x020e04ac
516 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2        0x020e04a0
517 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0       0x020e04a4
518 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P     0x020e04b0
519 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1       0x020e04a8
520 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0         0x020e04b4
521 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1         0x020e04b8
522 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P      0x020e04bc
523 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0         0x020e0470
524 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P      0x020e04c0
525 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1         0x020e0474
526 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P      0x020e04d4
527 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6         0x020e0488
528 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P      0x020e04d8
529 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7         0x020e048c
530 #define IOMUXC_SW_PAD_CTL_GRP_B7DS              0x020e0748
531 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS             0x020e074c
532 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL       0x020e0750
533 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE            0x020e0754
534 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK             0x020e0754
535 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS            0x020e075c
536 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE           0x020e0760
537 #define IOMUXC_SW_PAD_CTL_GRP_B0DS              0x020e0784
538 #define IOMUXC_SW_PAD_CTL_GRP_B1DS              0x020e0788
539 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS             0x020e078c
540 #define IOMUXC_SW_PAD_CTL_GRP_B2DS              0x020e0794
541 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE          0x020e0798
542 #define IOMUXC_SW_PAD_CTL_GRP_B3DS              0x020e079c
543 #define IOMUXC_SW_PAD_CTL_GRP_B4DS              0x020e07a0
544 #define IOMUXC_SW_PAD_CTL_GRP_B5DS              0x020e07a4
545 #define IOMUXC_SW_PAD_CTL_GRP_B6DS              0x020e07a8
546 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT    0x020e091c
547 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT  0x020e0920
548 #endif
549
550 dcd_hdr:
551         .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
552 dcd_start:
553         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
554         /* RESET_OUT GPIO_7_12 */
555         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
556
557         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */
558
559         MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
560
561         /* enable all relevant clocks... */
562         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
563         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
564         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
565         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
566         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
567         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
568         MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
569
570         /* IOMUX: */
571         MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
572         /* UART1 pad config */
573         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
574         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
575         MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
576         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0,        0x00000001)        /* UART1 CTS */
577         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1,        0x00000001)        /* UART1 RTS */
578         MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT,   0x00000003)        /* UART1 RTS INPUT_SEL */
579
580         /* NAND */
581         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE,     0x00000000)    /* NANDF_CLE: NANDF_CLE */
582         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE,     0x00000000)    /* NANDF_ALE: NANDF_ALE */
583         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B,    0x00000000)    /* NANDF_WP_B: NANDF_WPn */
584         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY,   0x00000000)    /* NANDF_RB0: NANDF_READY0 */
585         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B,   0x00000000)    /* NANDF_CS0: NANDF_CS0 */
586         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD,      0x00000001)    /* SD4_CMD: NANDF_RDn */
587         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK,      0x00000001)    /* SD4_CLK: NANDF_WRn */
588         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00,  0x00000000)    /* NANDF_D0: NANDF_D0 */
589         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01,  0x00000000)    /* NANDF_D1: NANDF_D1 */
590         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02,  0x00000000)    /* NANDF_D2: NANDF_D2 */
591         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03,  0x00000000)    /* NANDF_D3: NANDF_D3 */
592         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04,  0x00000000)    /* NANDF_D4: NANDF_D4 */
593         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05,  0x00000000)    /* NANDF_D5: NANDF_D5 */
594         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06,  0x00000000)    /* NANDF_D6: NANDF_D6 */
595         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07,  0x00000000)    /* NANDF_D7: NANDF_D7 */
596
597         /* ext. mem CS */
598         MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000)      /* NANDF_CS2: NANDF_CS2 */
599         /* DRAM_DQM[0..7] */
600         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
601         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
602         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
603         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
604 #if PHYS_SDRAM_1_WIDTH == 64
605         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
606         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
607         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
608         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
609 #endif
610
611         /* DRAM_A[0..15] */
612         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
613         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
614         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
615         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
616         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
617         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
618         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
619         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
620         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
621         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
622         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
623         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
624         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
625         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
626         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
627         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
628         /* DRAM_CAS */
629         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
630         /* DRAM_RAS */
631         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
632         /* DRAM_SDCLK[0..1] */
633         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
634         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
635         /* DRAM_RESET */
636         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
637         /* DRAM_SDCKE[0..1] */
638         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
639         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
640         /* DRAM_SDBA[0..2] */
641         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
642         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
643         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
644         /* DRAM_SDODT[0..1] */
645         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
646         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
647         /* DRAM_B[0..7]DS */
648         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK)
649         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
650         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
651         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
652 #if PHYS_SDRAM_1_WIDTH == 64
653         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
654         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
655         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
656         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
657 #endif
658         /* ADDDS */
659         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK)
660         /* DDRMODE_CTL */
661         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
662         /* DDRPKE */
663         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
664         /* DDRMODE */
665         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
666         /* CTLDS */
667         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK)
668         /* DDR_TYPE */
669         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
670         /* DDRPK */
671         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
672         /* DDRHYS */
673         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
674
675 #ifdef CONFIG_MX6Q
676         /* TERM_CTL[0..7] */
677         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
678         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
679         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
680         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
681         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
682         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
683         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
684         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
685 #endif
686
687         /* SDRAM initialization */
688         /* MPRDDQBY[0..7]DL */
689         MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
690         MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
691         MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333)
692         MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333)
693 #if PHYS_SDRAM_1_WIDTH == 64
694         MXC_DCD_ITEM(MMDC2_MPRDDQBY0DL, 0x33333333)
695         MXC_DCD_ITEM(MMDC2_MPRDDQBY1DL, 0x33333333)
696         MXC_DCD_ITEM(MMDC2_MPRDDQBY2DL, 0x33333333)
697         MXC_DCD_ITEM(MMDC2_MPRDDQBY3DL, 0x33333333)
698 #endif
699         /* MDMISC */
700         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
701 ddr_reset:
702         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
703         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
704
705         /* MSDSCR Conf Req */
706         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
707 con_ack:
708         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
709         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
710         /* MDCTL */
711         MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
712 ddr_calib:
713         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
714         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
715
716         MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
717         MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
718         MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
719         MXC_DCD_ITEM(MMDC1_MDRWD,  0x000026d2) /* MDRWD */
720         MXC_DCD_ITEM(MMDC1_MDOR,   MDOR_VAL)
721         MXC_DCD_ITEM(MMDC1_MDOTC,  MDOTC_VAL)
722         MXC_DCD_ITEM(MMDC1_MDPDC,  MDPDC_VAL_0)
723         MXC_DCD_ITEM(MMDC1_MDASP,  (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */
724
725         /* CS0 MRS: */
726         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
727         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
728         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
729         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
730 #if BANK_ADDR_BITS > 1
731         /* CS1 MRS: MR2 */
732         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
733         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
734         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
735         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
736 #endif
737
738         MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
739
740         MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00011112) /* MPODTCTRL */
741 #if PHYS_SDRAM_1_WIDTH == 64
742         MXC_DCD_ITEM(MMDC2_MPODTCTRL, 0x00011112)
743 #endif
744
745         /* DDR3 calibration */
746         MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
747         MXC_DCD_ITEM(MMDC1_MAPSR,     0x00011007)
748
749         /* ZQ calibration */
750         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
751         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
752
753         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b)
754 #if PHYS_SDRAM_1_WIDTH == 64
755         MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa138002b)
756 #endif
757
758 zq_calib:
759         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
760         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
761
762         /* Write leveling */
763         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
764 #if PHYS_SDRAM_1_WIDTH == 64
765         MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa1380000)
766 #endif
767
768         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
769         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
770
771         MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
772 wl_calib:
773         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
774         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
775 #if PHYS_SDRAM_1_WIDTH == 64
776         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
777         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
778 #endif
779         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
780
781         MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
782 #if PHYS_SDRAM_1_WIDTH == 64
783         MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa138002b)
784 #endif
785
786         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
787
788         /* DQS gating calibration */
789         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
790         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
791         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
792         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
793 #if PHYS_SDRAM_1_WIDTH == 64
794         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
795         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
796         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
797         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
798 #endif
799         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
800
801         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
802         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
803
804         MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
805         MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
806         MXC_DCD_ITEM(MMDC1_MPMUR0,    0x00000800)
807 #if PHYS_SDRAM_1_WIDTH == 64
808         MXC_DCD_ITEM(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
809         MXC_DCD_ITEM(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
810         MXC_DCD_ITEM(MMDC2_MPMUR0,    0x00000800)
811 #endif
812
813         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
814 dqs_fifo_reset:
815         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
816         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
817         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
818 dqs_fifo_reset2:
819         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
820         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
821         MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
822 dqs_calib:
823         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000)
824         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000)
825 #if PHYS_SDRAM_1_WIDTH == 64
826         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPDGCTRL0, 0x10000000)
827         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPDGCTRL0, 0x00001000)
828 #endif
829         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
830
831         /* DRAM_SDQS[0..7] pad config */
832         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
833         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
834         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
835         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
836 #if PHYS_SDRAM_1_WIDTH == 64
837         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
838         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
839         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
840         MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
841 #endif
842
843         MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
844
845         /* Read delay calibration */
846         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
847         MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
848 rd_dl_calib:
849         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010)
850         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f)
851 #if PHYS_SDRAM_1_WIDTH == 64
852         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
853         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
854 #endif
855         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
856
857         MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
858         MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
859 wr_dl_calib:
860         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010)
861         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f)
862 #if PHYS_SDRAM_1_WIDTH == 64
863         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010)
864         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f)
865 #endif
866         MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
867
868         MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
869         MXC_DCD_ITEM(MMDC1_MDREF, 0x00005800) /* MDREF */
870         MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011006) /* MAPSR */
871         MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
872
873         /* MDSCR: Normal operation */
874         MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
875
876 con_ack_clr:
877         MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)
878 dcd_end:
879         .ifgt   dcd_end - dcd_start - 1768
880         .error  "DCD too large!"
881         .endif