board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  35 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  36 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  37 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  38
  39 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  40 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  41 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  42
  43 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  44 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
  45 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
  46
  47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  48 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  49 #else
  50 #define TEMPERATURE_MIN                 (-40)
  51 #endif
  52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  53 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  54 #else
  55 #define TEMPERATURE_HOT                 80
  56 #endif
  57
  58 DECLARE_GLOBAL_DATA_PTR;
  59
  60 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  61
  62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  63 #ifdef CONFIG_SECURE_BOOT
  64 char __csf_data[0] __attribute__((section(".__csf_data")));
  65 #endif
  66
  67 #define TX6_DEFAULT_PAD_CTRL    MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  68                                         PAD_CTL_SPEED_MED |             \
  69                                         PAD_CTL_DSE_40ohm |             \
  70                                         PAD_CTL_SRE_FAST)
  71 #define TX6_FEC_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  72                                         PAD_CTL_SPEED_MED |             \
  73                                         PAD_CTL_DSE_40ohm |             \
  74                                         PAD_CTL_SRE_FAST)
  75 #define TX6_GPIO_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  76                                         PAD_CTL_SPEED_MED |             \
  77                                         PAD_CTL_DSE_34ohm |             \
  78                                         PAD_CTL_SRE_FAST)
  79 #define TX6_I2C_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  80                                         PAD_CTL_HYS |                   \
  81                                         PAD_CTL_SPEED_LOW |             \
  82                                         PAD_CTL_DSE_40ohm |             \
  83                                         PAD_CTL_SRE_SLOW)
  84
  85 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
  86         /* RESET_OUT */
  87         MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
  88
  89         /* UART pads */
  90 #if CONFIG_MXC_UART_BASE == UART1_BASE
  91         MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
  92         MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
  93         MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
  94         MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
  95 #endif
  96 #if CONFIG_MXC_UART_BASE == UART2_BASE
  97         MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
  98         MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
  99         MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
 100         MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
 101 #endif
 102 #if CONFIG_MXC_UART_BASE == UART3_BASE
 103         MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
 104         MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
 105         MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
 106         MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
 107 #endif
 108         /* internal I2C */
 109         MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
 110         MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
 111
 112         /* FEC PHY GPIO functions */
 113         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
 114                         TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
 115         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
 116                         TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
 117         MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
 118 };
 119
 120 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 121         /* FEC functions */
 122         MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
 123         MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
 124         MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL,
 125         MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
 126         MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
 127         MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
 128         MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
 129         MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
 130         MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
 131         MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
 132 };
 133
 134 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
 135         /* internal I2C */
 136         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
 137                         TX6_GPIO_PAD_CTRL,
 138         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
 139                         TX6_GPIO_PAD_CTRL,
 140 };
 141
 142 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
 143         /* internal I2C */
 144         MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
 145         MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
 146 };
 147
 148 static const struct gpio const tx6qdl_gpios[] = {
 149         /* These two entries are used to forcefully reinitialize the I2C bus */
 150         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 151         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 152
 153         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 154         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 155         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 156         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 157 };
 158
 159 static int pmic_addr __data;
 160
 161 #if defined(TX6_I2C1_SCL_GPIO) && defined(TX6_I2C1_SDA_GPIO)
 162 #define SCL_BANK        (TX6_I2C1_SCL_GPIO / 32)
 163 #define SDA_BANK        (TX6_I2C1_SDA_GPIO / 32)
 164 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
 165 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
 166
 167 static void * const gpio_ports[] = {
 168         (void *)GPIO1_BASE_ADDR,
 169         (void *)GPIO2_BASE_ADDR,
 170         (void *)GPIO3_BASE_ADDR,
 171         (void *)GPIO4_BASE_ADDR,
 172         (void *)GPIO5_BASE_ADDR,
 173         (void *)GPIO6_BASE_ADDR,
 174         (void *)GPIO7_BASE_ADDR,
 175 };
 176
 177 static void tx6_i2c_recover(void)
 178 {
 179         int i;
 180         int bad = 0;
 181         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
 182         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 183
 184         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
 185             (readl(&sda_regs->gpio_psr) & SDA_BIT))
 186                 return;
 187
 188         debug("Clearing I2C bus\n");
 189         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
 190                 printf("I2C SCL stuck LOW\n");
 191                 bad++;
 192
 193                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 194                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 195
 196                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
 197                                                  ARRAY_SIZE(tx6_i2c_gpio_pads));
 198         }
 199         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
 200                 printf("I2C SDA stuck LOW\n");
 201
 202                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
 203                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 204                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 205
 206                 if (!bad++)
 207                         imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
 208                                                          ARRAY_SIZE(tx6_i2c_gpio_pads));
 209
 210                 udelay(10);
 211
 212                 for (i = 0; i < 18; i++) {
 213                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
 214
 215                         debug("%sing SCL\n",
 216                               (reg & SCL_BIT) ? "Sett" : "Clear");
 217                         writel(reg, &scl_regs->gpio_dr);
 218                         udelay(5);
 219                         if (reg & SCL_BIT) {
 220                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
 221                                         break;
 222                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
 223                                         break;
 224                                 break;
 225                         }
 226                 }
 227         }
 228         if (bad) {
 229                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
 230                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 231
 232                 if (scl && sda) {
 233                         printf("I2C bus recovery succeeded\n");
 234                 } else {
 235                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
 236                                scl, sda);
 237                 }
 238                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
 239                                                  ARRAY_SIZE(tx6_i2c_pads));
 240         }
 241 }
 242 #endif
 243
 244 /* placed in section '.data' to prevent overwriting relocation info
 245  * overlayed with bss
 246  */
 247 static u32 wrsr __data;
 248
 249 #define WRSR_POR                        (1 << 4)
 250 #define WRSR_TOUT                       (1 << 1)
 251 #define WRSR_SFTW                       (1 << 0)
 252
 253 static void print_reset_cause(void)
 254 {
 255         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 256         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 257         u32 srsr;
 258         char *dlm = "";
 259
 260         printf("Reset cause: ");
 261
 262         srsr = readl(&src_regs->srsr);
 263         wrsr = readw(wdt_base + 4);
 264
 265         if (wrsr & WRSR_POR) {
 266                 printf("%sPOR", dlm);
 267                 dlm = " | ";
 268         }
 269         if (srsr & 0x00004) {
 270                 printf("%sCSU", dlm);
 271                 dlm = " | ";
 272         }
 273         if (srsr & 0x00008) {
 274                 printf("%sIPP USER", dlm);
 275                 dlm = " | ";
 276         }
 277         if (srsr & 0x00010) {
 278                 if (wrsr & WRSR_SFTW) {
 279                         printf("%sSOFT", dlm);
 280                         dlm = " | ";
 281                 }
 282                 if (wrsr & WRSR_TOUT) {
 283                         printf("%sWDOG", dlm);
 284                         dlm = " | ";
 285                 }
 286         }
 287         if (srsr & 0x00020) {
 288                 printf("%sJTAG HIGH-Z", dlm);
 289                 dlm = " | ";
 290         }
 291         if (srsr & 0x00040) {
 292                 printf("%sJTAG SW", dlm);
 293                 dlm = " | ";
 294         }
 295         if (srsr & 0x10000) {
 296                 printf("%sWARM BOOT", dlm);
 297                 dlm = " | ";
 298         }
 299         if (dlm[0] == '\0')
 300                 printf("unknown");
 301
 302         printf("\n");
 303 }
 304
 305 static const char __data *tx6_mod_suffix;
 306
 307 #ifdef CONFIG_IMX6_THERMAL
 308 #include <thermal.h>
 309 #include <imx_thermal.h>
 310 #include <fuse.h>
 311
 312 static void print_temperature(void)
 313 {
 314         struct udevice *thermal_dev;
 315         int cpu_tmp, minc, maxc, ret;
 316         char const *grade_str;
 317         static u32 __data thermal_calib;
 318
 319         puts("Temperature: ");
 320         switch (get_cpu_temp_grade(&minc, &maxc)) {
 321         case TEMP_AUTOMOTIVE:
 322                 grade_str = "Automotive";
 323                 break;
 324         case TEMP_INDUSTRIAL:
 325                 grade_str = "Industrial";
 326                 break;
 327         case TEMP_EXTCOMMERCIAL:
 328                 grade_str = "Extended Commercial";
 329                 break;
 330         default:
 331                 grade_str = "Commercial";
 332         }
 333         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 334         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 335         if (ret == 0) {
 336                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 337
 338                 if (ret == 0)
 339                         printf(" at %dC", cpu_tmp);
 340                 else
 341                         puts(" - failed to read sensor data");
 342         } else {
 343                 puts(" - no sensor device found");
 344         }
 345
 346         if (fuse_read(1, 6, &thermal_calib) == 0) {
 347                 printf(" - calibration data 0x%08x\n", thermal_calib);
 348         } else {
 349                 puts(" - Failed to read thermal calib fuse\n");
 350         }
 351 }
 352 #else
 353 static inline void print_temperature(void)
 354 {
 355 }
 356 #endif
 357
 358 int checkboard(void)
 359 {
 360         u32 cpurev = get_cpu_rev();
 361         char *cpu_str = "?";
 362
 363         if (is_cpu_type(MXC_CPU_MX6SL)) {
 364                 cpu_str = "SL";
 365                 tx6_mod_suffix = "?";
 366         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
 367                 cpu_str = "DL";
 368                 tx6_mod_suffix = "U";
 369         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 370                 cpu_str = "SOLO";
 371                 tx6_mod_suffix = "S";
 372         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
 373                 cpu_str = "Q";
 374                 tx6_mod_suffix = "Q";
 375         } else if (is_cpu_type(MXC_CPU_MX6QP)) {
 376                 cpu_str = "QP";
 377                 tx6_mod_suffix = "QP";
 378         }
 379
 380         printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
 381                 cpu_str,
 382                 (cpurev & 0x000F0) >> 4,
 383                 (cpurev & 0x0000F) >> 0,
 384                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 385
 386         print_temperature();
 387         print_reset_cause();
 388 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 389         check_cpu_temperature(1);
 390 #endif
 391         tx6_i2c_recover();
 392         return 0;
 393 }
 394
 395 /* serial port not initialized at this point */
 396 int board_early_init_f(void)
 397 {
 398         return 0;
 399 }
 400
 401 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 402 static bool tx6_temp_check_enabled = true;
 403 #else
 404 #define tx6_temp_check_enabled  0
 405 #endif
 406
 407 #ifdef CONFIG_TX6_NAND
 408 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
 409 #else
 410 #ifdef CONFIG_MMC_BOOT_SIZE
 411 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
 412 #else
 413 #define TX6_FLASH_SZ    2
 414 #endif
 415 #endif /* CONFIG_TX6_NAND */
 416
 417 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
 418
 419 static char tx6_mem_table[] = {
 420         '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
 421         '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
 422         '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
 423         '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
 424         '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
 425         '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
 426         '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
 427         '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
 428         '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
 429         '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
 430         '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
 431         '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
 432 };
 433
 434 #ifdef CONFIG_RN5T567
 435 /* PMIC settings */
 436 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 437 #define VDD_CORE_VAL            rn5t_mV_to_regval(1400)         /* DCDC1 */
 438 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 439 #define VDD_SOC_VAL             rn5t_mV_to_regval(1400)         /* DCDC2 */
 440 #define VDD_SOC_VAL_LP          rn5t_mV_to_regval(1400)
 441 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
 442 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 443 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3000)         /* DCDC4 */
 444 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3000)
 445 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
 446 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
 447 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval2(3300)        /* LDO2 */
 448 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval2(3300)
 449
 450 static struct pmic_regs rn5t567_regs[] = {
 451         { RN5T567_NOETIMSET, 0x5, },
 452         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 453         { RN5T567_DC2DAC, VDD_SOC_VAL, },
 454         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 455         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
 456         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 457         { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
 458         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 459         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
 460         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 461         { RN5T567_DC2CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 462         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 463         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 464         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 465         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 466         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
 467         { RN5T567_LDO2DAC, VDD_IO_EXT_VAL, },
 468         { RN5T567_LDOEN1, 0x03, ~0x1f, },
 469         { RN5T567_LDOEN2, 0x10, ~0x30, },
 470         { RN5T567_LDODIS, 0x1c, ~0x1f, },
 471         { RN5T567_INTPOL, 0, },
 472         { RN5T567_INTEN, 0x3, },
 473         { RN5T567_IREN, 0xf, },
 474         { RN5T567_EN_GPIR, 0, },
 475 };
 476 #endif
 477
 478 static struct {
 479         uchar addr;
 480         uchar rev;
 481         struct pmic_regs *regs;
 482         size_t num_regs;
 483 } tx6_mod_revs[] = {
 484 #ifdef CONFIG_LTC3676
 485         { 0x3c, 1, NULL, 0, },
 486 #endif
 487 #ifdef CONFIG_RN5T567
 488         { 0x33, 3, rn5t567_regs, ARRAY_SIZE(rn5t567_regs), },
 489 #endif
 490 };
 491
 492 static inline char tx6_mem_suffix(void)
 493 {
 494         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
 495
 496         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
 497                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
 498
 499         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
 500                 return '?';
 501         if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
 502                 return '7';
 503         if (mem_idx == 8)
 504                 return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
 505         return tx6_mem_table[mem_idx];
 506 };
 507
 508 static int tx6_get_mod_rev(unsigned int pmic_id)
 509 {
 510         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
 511                 return tx6_mod_revs[pmic_id].rev;
 512
 513         return 0;
 514 }
 515
 516 static int tx6_pmic_probe(void)
 517 {
 518         int i;
 519
 520         debug("%s@%d: \n", __func__, __LINE__);
 521
 522         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
 523                 u8 i2c_addr = tx6_mod_revs[i].addr;
 524                 int ret = i2c_probe(i2c_addr);
 525
 526                 if (ret == 0) {
 527                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
 528                         return i;
 529                 }
 530                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
 531         }
 532         return -EINVAL;
 533 }
 534
 535 static int tx6_mipi(void)
 536 {
 537         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 538         struct fuse_bank4_regs *fuse = (void *)ocotp->bank[4].fuse_regs;
 539         u32 gp1 = readl(&fuse->gp1);
 540
 541         debug("Fuse gp1 @ %p = %08x\n", &fuse->gp1, gp1);
 542         return gp1 & 1;
 543 }
 544
 545 int board_init(void)
 546 {
 547         int ret;
 548         int pmic_id;
 549
 550         debug("%s@%d: \n", __func__, __LINE__);
 551
 552         pmic_id = tx6_pmic_probe();
 553         if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
 554                 pmic_addr = tx6_mod_revs[pmic_id].addr;
 555
 556         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
 557                 tx6_mod_suffix,
 558                 is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
 559                 tx6_mipi() ? 2 : is_lvds(), tx6_get_mod_rev(pmic_id),
 560                 tx6_mem_suffix());
 561
 562         get_hab_status();
 563
 564         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 565         if (ret < 0) {
 566                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
 567         }
 568         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 569
 570         /* Address of boot parameters */
 571         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 572         gd->bd->bi_arch_number = -1;
 573
 574         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 575                 if (wrsr & WRSR_TOUT)
 576                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 577                 else
 578                         printf("<CTRL-C> detected; safeboot enabled\n");
 579 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 580                 tx6_temp_check_enabled = false;
 581 #endif
 582                 return 0;
 583         }
 584
 585         ret = tx6_pmic_init(pmic_addr, tx6_mod_revs[pmic_id].regs,
 586                         tx6_mod_revs[pmic_id].num_regs);
 587         if (ret) {
 588                 printf("Failed to setup PMIC voltages: %d\n", ret);
 589                 hang();
 590         }
 591         return 0;
 592 }
 593
 594 int dram_init(void)
 595 {
 596         debug("%s@%d: \n", __func__, __LINE__);
 597
 598         /* dram_init must store complete ramsize in gd->ram_size */
 599         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 600                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 601         return 0;
 602 }
 603
 604 void dram_init_banksize(void)
 605 {
 606         debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
 607                 CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
 608         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 609         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 610                         PHYS_SDRAM_1_SIZE);
 611 #if CONFIG_NR_DRAM_BANKS > 1
 612         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 613         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 614                         PHYS_SDRAM_2_SIZE);
 615 #endif
 616 }
 617
 618 #ifdef  CONFIG_FSL_ESDHC
 619 #define SD_PAD_CTRL             MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
 620                                 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 621                                 PAD_CTL_SRE_FAST)
 622
 623 static const iomux_v3_cfg_t mmc0_pads[] = {
 624         MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
 625         MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
 626         MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
 627         MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
 628         MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
 629         MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
 630         /* SD1 CD */
 631         MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
 632 };
 633
 634 static const iomux_v3_cfg_t mmc1_pads[] = {
 635         MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
 636         MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
 637         MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
 638         MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
 639         MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
 640         MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
 641         /* SD2 CD */
 642         MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
 643 };
 644
 645 #ifdef CONFIG_TX6_EMMC
 646 static const iomux_v3_cfg_t mmc3_pads[] = {
 647         MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
 648         MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
 649         MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
 650         MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
 651         MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
 652         MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
 653         /* eMMC RESET */
 654         MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
 655 };
 656 #endif
 657
 658 static struct tx6_esdhc_cfg {
 659         const iomux_v3_cfg_t *pads;
 660         int num_pads;
 661         enum mxc_clock clkid;
 662         struct fsl_esdhc_cfg cfg;
 663         int cd_gpio;
 664 } tx6qdl_esdhc_cfg[] = {
 665 #ifdef CONFIG_TX6_EMMC
 666         {
 667                 .pads = mmc3_pads,
 668                 .num_pads = ARRAY_SIZE(mmc3_pads),
 669                 .clkid = MXC_ESDHC4_CLK,
 670                 .cfg = {
 671                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 672                         .max_bus_width = 4,
 673                 },
 674                 .cd_gpio = -EINVAL,
 675         },
 676 #endif
 677         {
 678                 .pads = mmc0_pads,
 679                 .num_pads = ARRAY_SIZE(mmc0_pads),
 680                 .clkid = MXC_ESDHC_CLK,
 681                 .cfg = {
 682                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 683                         .max_bus_width = 4,
 684                 },
 685                 .cd_gpio = IMX_GPIO_NR(7, 2),
 686         },
 687         {
 688                 .pads = mmc1_pads,
 689                 .num_pads = ARRAY_SIZE(mmc1_pads),
 690                 .clkid = MXC_ESDHC2_CLK,
 691                 .cfg = {
 692                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 693                         .max_bus_width = 4,
 694                 },
 695                 .cd_gpio = IMX_GPIO_NR(7, 3),
 696         },
 697 };
 698
 699 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 700 {
 701         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 702 }
 703
 704 int board_mmc_getcd(struct mmc *mmc)
 705 {
 706         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 707
 708         if (cfg->cd_gpio < 0)
 709                 return 1;
 710
 711         debug("SD card %d is %spresent (GPIO %d)\n",
 712                 cfg - tx6qdl_esdhc_cfg,
 713                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 714                 cfg->cd_gpio);
 715         return !gpio_get_value(cfg->cd_gpio);
 716 }
 717
 718 int board_mmc_init(bd_t *bis)
 719 {
 720         int i;
 721
 722         debug("%s@%d: \n", __func__, __LINE__);
 723
 724         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 725                 struct mmc *mmc;
 726                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 727                 int ret;
 728
 729                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 730                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 731
 732                 if (cfg->cd_gpio >= 0) {
 733                         ret = gpio_request_one(cfg->cd_gpio,
 734                                         GPIOFLAG_INPUT, "MMC CD");
 735                         if (ret) {
 736                                 printf("Error %d requesting GPIO%d_%d\n",
 737                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 738                                 continue;
 739                         }
 740                 }
 741
 742                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 743                 fsl_esdhc_initialize(bis, &cfg->cfg);
 744
 745                 mmc = find_mmc_device(i);
 746                 if (mmc == NULL)
 747                         continue;
 748                 if (board_mmc_getcd(mmc))
 749                         mmc_init(mmc);
 750         }
 751         return 0;
 752 }
 753 #endif /* CONFIG_CMD_MMC */
 754
 755 #ifdef CONFIG_FEC_MXC
 756
 757 #ifndef ETH_ALEN
 758 #define ETH_ALEN 6
 759 #endif
 760
 761 int board_eth_init(bd_t *bis)
 762 {
 763         int ret;
 764
 765         debug("%s@%d: \n", __func__, __LINE__);
 766
 767         /* delay at least 21ms for the PHY internal POR signal to deassert */
 768         udelay(22000);
 769
 770         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
 771                                         ARRAY_SIZE(tx6qdl_fec_pads));
 772
 773         /* Deassert RESET to the external phy */
 774         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 775
 776         ret = cpu_eth_init(bis);
 777         if (ret)
 778                 printf("cpu_eth_init() failed: %d\n", ret);
 779
 780         return ret;
 781 }
 782
 783 static void tx6_init_mac(void)
 784 {
 785         u8 mac[ETH_ALEN];
 786
 787         imx_get_mac_from_fuse(0, mac);
 788         if (!is_valid_ethaddr(mac)) {
 789                 printf("No valid MAC address programmed\n");
 790                 return;
 791         }
 792
 793         printf("MAC addr from fuse: %pM\n", mac);
 794         eth_setenv_enetaddr("ethaddr", mac);
 795 }
 796 #else
 797 static inline void tx6_init_mac(void)
 798 {
 799 }
 800 #endif /* CONFIG_FEC_MXC */
 801
 802 enum {
 803         LED_STATE_INIT = -1,
 804         LED_STATE_OFF,
 805         LED_STATE_ON,
 806 };
 807
 808 static inline int calc_blink_rate(void)
 809 {
 810         if (!tx6_temp_check_enabled)
 811                 return CONFIG_SYS_HZ;
 812
 813         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 814                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 815                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 816 }
 817
 818 void show_activity(int arg)
 819 {
 820         static int led_state = LED_STATE_INIT;
 821         static int blink_rate;
 822         static ulong last;
 823
 824         if (led_state == LED_STATE_INIT) {
 825                 last = get_timer(0);
 826                 gpio_set_value(TX6_LED_GPIO, 1);
 827                 led_state = LED_STATE_ON;
 828                 blink_rate = calc_blink_rate();
 829         } else {
 830                 if (get_timer(last) > blink_rate) {
 831                         blink_rate = calc_blink_rate();
 832                         last = get_timer_masked();
 833                         if (led_state == LED_STATE_ON) {
 834                                 gpio_set_value(TX6_LED_GPIO, 0);
 835                         } else {
 836                                 gpio_set_value(TX6_LED_GPIO, 1);
 837                         }
 838                         led_state = 1 - led_state;
 839                 }
 840         }
 841 }
 842
 843 static const iomux_v3_cfg_t stk5_pads[] = {
 844         /* SW controlled LED on STK5 baseboard */
 845         MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
 846
 847         /* I2C bus on DIMM pins 40/41 */
 848         MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
 849         MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
 850
 851         /* TSC200x PEN IRQ */
 852         MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
 853
 854         /* EDT-FT5x06 Polytouch panel */
 855         MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
 856         MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
 857         MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
 858
 859         /* USBH1 */
 860         MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
 861         MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
 862         /* USBOTG */
 863         MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
 864         MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
 865         MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
 866 };
 867
 868 static const struct gpio stk5_gpios[] = {
 869         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 870
 871         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 872         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 873         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 874         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 875         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 876 };
 877
 878 #ifdef CONFIG_LCD
 879 vidinfo_t panel_info = {
 880         /* set to max. size supported by SoC */
 881         .vl_col = 1920,
 882         .vl_row = 1080,
 883
 884         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 885 };
 886
 887 static struct fb_videomode tx6_fb_modes[] = {
 888         {
 889                 /* Standard VGA timing */
 890                 .name           = "VGA",
 891                 .refresh        = 60,
 892                 .xres           = 640,
 893                 .yres           = 480,
 894                 .pixclock       = KHZ2PICOS(25175),
 895                 .left_margin    = 48,
 896                 .hsync_len      = 96,
 897                 .right_margin   = 16,
 898                 .upper_margin   = 31,
 899                 .vsync_len      = 2,
 900                 .lower_margin   = 12,
 901                 .sync           = FB_SYNC_CLK_LAT_FALL,
 902         },
 903         {
 904                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 905                  * DE high active, 115.2 mm x 86.4 mm display area
 906                  * VGA compatible timing
 907                  */
 908                 .name           = "ETV570",
 909                 .refresh        = 60,
 910                 .xres           = 640,
 911                 .yres           = 480,
 912                 .pixclock       = KHZ2PICOS(25175),
 913                 .left_margin    = 114,
 914                 .hsync_len      = 30,
 915                 .right_margin   = 16,
 916                 .upper_margin   = 32,
 917                 .vsync_len      = 3,
 918                 .lower_margin   = 10,
 919                 .sync           = FB_SYNC_CLK_LAT_FALL,
 920         },
 921         {
 922                 /* Emerging ETM0700G0DH6 800 x 480 display.
 923                  * 152.4 mm x 91.44 mm display area.
 924                  */
 925                 .name           = "ET0700",
 926                 .refresh        = 60,
 927                 .xres           = 800,
 928                 .yres           = 480,
 929                 .pixclock       = KHZ2PICOS(33260),
 930                 .left_margin    = 88,
 931                 .hsync_len      = 128,
 932                 .right_margin   = 40,
 933                 .upper_margin   = 33,
 934                 .vsync_len      = 2,
 935                 .lower_margin   = 10,
 936                 .sync           = FB_SYNC_CLK_LAT_FALL,
 937         },
 938 #ifndef CONFIG_SYS_LVDS_IF
 939         {
 940                 /* Emerging ET0350G0DH6 320 x 240 display.
 941                  * 70.08 mm x 52.56 mm display area.
 942                  */
 943                 .name           = "ET0350",
 944                 .refresh        = 60,
 945                 .xres           = 320,
 946                 .yres           = 240,
 947                 .pixclock       = KHZ2PICOS(6500),
 948                 .left_margin    = 34,
 949                 .hsync_len      = 34,
 950                 .right_margin   = 20,
 951                 .upper_margin   = 15,
 952                 .vsync_len      = 3,
 953                 .lower_margin   = 4,
 954                 .sync           = FB_SYNC_CLK_LAT_FALL,
 955         },
 956         {
 957                 /* Emerging ET0430G0DH6 480 x 272 display.
 958                  * 95.04 mm x 53.856 mm display area.
 959                  */
 960                 .name           = "ET0430",
 961                 .refresh        = 60,
 962                 .xres           = 480,
 963                 .yres           = 272,
 964                 .pixclock       = KHZ2PICOS(9000),
 965                 .left_margin    = 2,
 966                 .hsync_len      = 41,
 967                 .right_margin   = 2,
 968                 .upper_margin   = 2,
 969                 .vsync_len      = 10,
 970                 .lower_margin   = 2,
 971         },
 972         {
 973                 /* Emerging ET0500G0DH6 800 x 480 display.
 974                  * 109.6 mm x 66.4 mm display area.
 975                  */
 976                 .name           = "ET0500",
 977                 .refresh        = 60,
 978                 .xres           = 800,
 979                 .yres           = 480,
 980                 .pixclock       = KHZ2PICOS(33260),
 981                 .left_margin    = 88,
 982                 .hsync_len      = 128,
 983                 .right_margin   = 40,
 984                 .upper_margin   = 33,
 985                 .vsync_len      = 2,
 986                 .lower_margin   = 10,
 987                 .sync           = FB_SYNC_CLK_LAT_FALL,
 988         },
 989         {
 990                 /* Emerging ETQ570G0DH6 320 x 240 display.
 991                  * 115.2 mm x 86.4 mm display area.
 992                  */
 993                 .name           = "ETQ570",
 994                 .refresh        = 60,
 995                 .xres           = 320,
 996                 .yres           = 240,
 997                 .pixclock       = KHZ2PICOS(6400),
 998                 .left_margin    = 38,
 999                 .hsync_len      = 30,
1000                 .right_margin   = 30,
1001                 .upper_margin   = 16, /* 15 according to datasheet */
1002                 .vsync_len      = 3, /* TVP -> 1>x>5 */
1003                 .lower_margin   = 4, /* 4.5 according to datasheet */
1004                 .sync           = FB_SYNC_CLK_LAT_FALL,
1005         },
1006 #else
1007         {
1008                 /* HannStar HSD100PXN1
1009                  * 202.7m mm x 152.06 mm display area.
1010                  */
1011                 .name           = "HSD100PXN1",
1012                 .refresh        = 60,
1013                 .xres           = 1024,
1014                 .yres           = 768,
1015                 .pixclock       = KHZ2PICOS(65000),
1016                 .left_margin    = 0,
1017                 .hsync_len      = 0,
1018                 .right_margin   = 320,
1019                 .upper_margin   = 0,
1020                 .vsync_len      = 0,
1021                 .lower_margin   = 38,
1022                 .sync           = FB_SYNC_CLK_LAT_FALL,
1023         },
1024 #endif
1025         {
1026                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1027                 .refresh        = 60,
1028                 .left_margin    = 48,
1029                 .hsync_len      = 96,
1030                 .right_margin   = 16,
1031                 .upper_margin   = 31,
1032                 .vsync_len      = 2,
1033                 .lower_margin   = 12,
1034                 .sync           = FB_SYNC_CLK_LAT_FALL,
1035         },
1036 };
1037
1038 static int lcd_enabled = 1;
1039 static int lcd_bl_polarity;
1040
1041 static int lcd_backlight_polarity(void)
1042 {
1043         return lcd_bl_polarity;
1044 }
1045
1046 void lcd_enable(void)
1047 {
1048         /* HACK ALERT:
1049          * global variable from common/lcd.c
1050          * Set to 0 here to prevent messages from going to LCD
1051          * rather than serial console
1052          */
1053         lcd_is_enabled = 0;
1054
1055         if (lcd_enabled) {
1056                 karo_load_splashimage(1);
1057
1058                 debug("Switching LCD on\n");
1059                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1060                 udelay(100);
1061                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1062                 udelay(300000);
1063                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1064                         lcd_backlight_polarity());
1065         }
1066 }
1067
1068 void lcd_disable(void)
1069 {
1070         if (lcd_enabled) {
1071                 printf("Disabling LCD\n");
1072                 ipuv3_fb_shutdown();
1073         }
1074 }
1075
1076 void lcd_panel_disable(void)
1077 {
1078         if (lcd_enabled) {
1079                 debug("Switching LCD off\n");
1080                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1081                         !lcd_backlight_polarity());
1082                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1083                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1084         }
1085 }
1086
1087 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1088         /* LCD RESET */
1089         MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
1090         /* LCD POWER_ENABLE */
1091         MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
1092         /* LCD Backlight (PWM) */
1093         MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
1094
1095 #ifndef CONFIG_SYS_LVDS_IF
1096         /* Display */
1097         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
1098         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
1099         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
1100         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
1101         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
1102         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
1103         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
1104         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
1105         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
1106         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
1107         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
1108         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
1109         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
1110         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
1111         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
1112         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
1113         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
1114         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
1115         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
1116         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
1117         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
1118         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
1119         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
1120         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
1121         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
1122         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
1123         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
1124         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
1125 #endif
1126 };
1127
1128 static const struct gpio stk5_lcd_gpios[] = {
1129         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1130         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1131         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1132 };
1133
1134 void lcd_ctrl_init(void *lcdbase)
1135 {
1136         int color_depth = 24;
1137         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1138         const char *vm;
1139         unsigned long val;
1140         int refresh = 60;
1141         struct fb_videomode *p = &tx6_fb_modes[0];
1142         struct fb_videomode fb_mode;
1143         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1144         int pix_fmt;
1145         int lcd_bus_width;
1146         unsigned long di_clk_rate = 65000000;
1147
1148         if (!lcd_enabled) {
1149                 debug("LCD disabled\n");
1150                 goto disable;
1151         }
1152
1153         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1154                 debug("Disabling LCD\n");
1155                 lcd_enabled = 0;
1156                 setenv("splashimage", NULL);
1157                 goto disable;
1158         }
1159
1160         karo_fdt_move_fdt();
1161         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1162
1163         if (video_mode == NULL) {
1164                 debug("Disabling LCD\n");
1165                 lcd_enabled = 0;
1166                 goto disable;
1167         }
1168         vm = video_mode;
1169         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1170                 p = &fb_mode;
1171                 debug("Using video mode from FDT\n");
1172                 vm += strlen(vm);
1173                 if (fb_mode.xres > panel_info.vl_col ||
1174                         fb_mode.yres > panel_info.vl_row) {
1175                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1176                                 fb_mode.xres, fb_mode.yres,
1177                                 panel_info.vl_col, panel_info.vl_row);
1178                         lcd_enabled = 0;
1179                         goto disable;
1180                 }
1181         }
1182         if (p->name != NULL)
1183                 debug("Trying compiled-in video modes\n");
1184         while (p->name != NULL) {
1185                 if (strcmp(p->name, vm) == 0) {
1186                         debug("Using video mode: '%s'\n", p->name);
1187                         vm += strlen(vm);
1188                         break;
1189                 }
1190                 p++;
1191         }
1192         if (*vm != '\0')
1193                 debug("Trying to decode video_mode: '%s'\n", vm);
1194         while (*vm != '\0') {
1195                 if (*vm >= '0' && *vm <= '9') {
1196                         char *end;
1197
1198                         val = simple_strtoul(vm, &end, 0);
1199                         if (end > vm) {
1200                                 if (!xres_set) {
1201                                         if (val > panel_info.vl_col)
1202                                                 val = panel_info.vl_col;
1203                                         p->xres = val;
1204                                         panel_info.vl_col = val;
1205                                         xres_set = 1;
1206                                 } else if (!yres_set) {
1207                                         if (val > panel_info.vl_row)
1208                                                 val = panel_info.vl_row;
1209                                         p->yres = val;
1210                                         panel_info.vl_row = val;
1211                                         yres_set = 1;
1212                                 } else if (!bpp_set) {
1213                                         switch (val) {
1214                                         case 32:
1215                                         case 24:
1216                                                 if (is_lvds())
1217                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1218                                                 /* fallthru */
1219                                         case 16:
1220                                         case 8:
1221                                                 color_depth = val;
1222                                                 break;
1223
1224                                         case 18:
1225                                                 if (is_lvds()) {
1226                                                         color_depth = val;
1227                                                         break;
1228                                                 }
1229                                                 /* fallthru */
1230                                         default:
1231                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1232                                                         end - vm, vm, color_depth);
1233                                         }
1234                                         bpp_set = 1;
1235                                 } else if (!refresh_set) {
1236                                         refresh = val;
1237                                         refresh_set = 1;
1238                                 }
1239                         }
1240                         vm = end;
1241                 }
1242                 switch (*vm) {
1243                 case '@':
1244                         bpp_set = 1;
1245                         /* fallthru */
1246                 case '-':
1247                         yres_set = 1;
1248                         /* fallthru */
1249                 case 'x':
1250                         xres_set = 1;
1251                         /* fallthru */
1252                 case 'M':
1253                 case 'R':
1254                         vm++;
1255                         break;
1256
1257                 default:
1258                         if (*vm != '\0')
1259                                 vm++;
1260                 }
1261         }
1262         if (p->xres == 0 || p->yres == 0) {
1263                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1264                 lcd_enabled = 0;
1265                 printf("Supported video modes are:");
1266                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1267                         printf(" %s", p->name);
1268                 }
1269                 printf("\n");
1270                 goto disable;
1271         }
1272         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1273                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1274                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1275                 lcd_enabled = 0;
1276                 goto disable;
1277         }
1278         panel_info.vl_col = p->xres;
1279         panel_info.vl_row = p->yres;
1280
1281         switch (color_depth) {
1282         case 8:
1283                 panel_info.vl_bpix = LCD_COLOR8;
1284                 break;
1285         case 16:
1286                 panel_info.vl_bpix = LCD_COLOR16;
1287                 break;
1288         default:
1289                 panel_info.vl_bpix = LCD_COLOR32;
1290         }
1291
1292         p->pixclock = KHZ2PICOS(refresh *
1293                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1294                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1295                                 1000);
1296         debug("Pixel clock set to %lu.%03lu MHz\n",
1297                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1298
1299         if (p != &fb_mode) {
1300                 int ret;
1301
1302                 debug("Creating new display-timing node from '%s'\n",
1303                         video_mode);
1304                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1305                 if (ret)
1306                         printf("Failed to create new display-timing node from '%s': %d\n",
1307                                 video_mode, ret);
1308         }
1309
1310         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1311         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1312                                         ARRAY_SIZE(stk5_lcd_pads));
1313
1314         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1315         switch (lcd_bus_width) {
1316         case 24:
1317                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1318                 break;
1319
1320         case 18:
1321                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1322                 break;
1323
1324         case 16:
1325                 if (!is_lvds()) {
1326                         pix_fmt = IPU_PIX_FMT_RGB565;
1327                         break;
1328                 }
1329                 /* fallthru */
1330         default:
1331                 lcd_enabled = 0;
1332                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1333                         lcd_bus_width);
1334                 goto disable;
1335         }
1336         if (is_lvds()) {
1337                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1338                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1339                 uint32_t gpr2;
1340                 uint32_t gpr3;
1341
1342                 if (lvds_chan_mask == 0) {
1343                         printf("No LVDS channel active\n");
1344                         lcd_enabled = 0;
1345                         goto disable;
1346                 }
1347
1348                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1349                 if (lcd_bus_width == 24)
1350                         gpr2 |= (1 << 5) | (1 << 7);
1351                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1352                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1353                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1354                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1355
1356                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1357                 gpr3 &= ~((3 << 8) | (3 << 6));
1358                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1359         }
1360         if (karo_load_splashimage(0) == 0) {
1361                 int ret;
1362
1363                 debug("Initializing LCD controller\n");
1364                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1365                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1366                                 di_clk_rate, -1);
1367                 if (ret) {
1368                         printf("Failed to initialize FB driver: %d\n", ret);
1369                         lcd_enabled = 0;
1370                 }
1371         } else {
1372                 debug("Skipping initialization of LCD controller\n");
1373         }
1374         return;
1375
1376 disable:
1377         lcd_enabled = 0;
1378         panel_info.vl_col = 0;
1379         panel_info.vl_row = 0;
1380
1381 }
1382 #else
1383 #define lcd_enabled 0
1384 #endif /* CONFIG_LCD */
1385
1386 static void stk5_board_init(void)
1387 {
1388         int ret;
1389
1390         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1391         if (ret < 0) {
1392                 printf("Failed to request stk5_gpios: %d\n", ret);
1393                 return;
1394         }
1395         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1396 }
1397
1398 static void stk5v3_board_init(void)
1399 {
1400         stk5_board_init();
1401 }
1402
1403 static void stk5v5_board_init(void)
1404 {
1405         int ret;
1406
1407         stk5_board_init();
1408
1409         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1410                         "Flexcan Transceiver");
1411         if (ret) {
1412                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1413                 return;
1414         }
1415
1416         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
1417                         TX6_GPIO_PAD_CTRL);
1418 }
1419
1420 static void tx6qdl_set_cpu_clock(void)
1421 {
1422         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1423
1424         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1425                 return;
1426
1427         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1428                 printf("%s detected; skipping cpu clock change\n",
1429                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1430                 return;
1431         }
1432         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1433                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1434                 printf("CPU clock set to %lu.%03lu MHz\n",
1435                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1436         } else {
1437                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1438         }
1439 }
1440
1441 int board_late_init(void)
1442 {
1443         const char *baseboard;
1444
1445         debug("%s@%d: \n", __func__, __LINE__);
1446
1447         env_cleanup();
1448
1449         if (tx6_temp_check_enabled)
1450                 check_cpu_temperature(1);
1451
1452         tx6qdl_set_cpu_clock();
1453
1454         if (had_ctrlc())
1455                 setenv_ulong("safeboot", 1);
1456         else if (wrsr & WRSR_TOUT)
1457                 setenv_ulong("wdreset", 1);
1458         else
1459                 karo_fdt_move_fdt();
1460
1461         baseboard = getenv("baseboard");
1462         if (!baseboard)
1463                 goto exit;
1464
1465         printf("Baseboard: %s\n", baseboard);
1466
1467         if (strncmp(baseboard, "stk5", 4) == 0) {
1468                 if ((strlen(baseboard) == 4) ||
1469                         strcmp(baseboard, "stk5-v3") == 0) {
1470                         stk5v3_board_init();
1471                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1472                         const char *otg_mode = getenv("otg_mode");
1473
1474                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1475                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1476                                         otg_mode, baseboard);
1477                                 setenv("otg_mode", "none");
1478                         }
1479                         stk5v5_board_init();
1480                 } else {
1481                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1482                                 baseboard + 4);
1483                 }
1484         } else {
1485                 printf("WARNING: Unsupported baseboard: '%s'\n",
1486                         baseboard);
1487                 if (!had_ctrlc())
1488                         return -EINVAL;
1489         }
1490
1491 exit:
1492         tx6_init_mac();
1493
1494         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1495         clear_ctrlc();
1496         return 0;
1497 }
1498
1499 #ifdef CONFIG_SERIAL_TAG
1500 void get_board_serial(struct tag_serialnr *serialnr)
1501 {
1502         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1503         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1504
1505         serialnr->low = readl(&fuse->cfg0);
1506         serialnr->high = readl(&fuse->cfg1);
1507 }
1508 #endif
1509
1510 #if defined(CONFIG_OF_BOARD_SETUP)
1511 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1512 #include <jffs2/jffs2.h>
1513 #include <mtd_node.h>
1514 static struct node_info nodes[] = {
1515         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1516 };
1517 #else
1518 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1519 #endif
1520
1521 static const char *tx6_touchpanels[] = {
1522         "ti,tsc2007",
1523         "edt,edt-ft5x06",
1524         "eeti,egalax_ts",
1525 };
1526
1527 int ft_board_setup(void *blob, bd_t *bd)
1528 {
1529         const char *baseboard = getenv("baseboard");
1530         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1531         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1532         int ret;
1533
1534         ret = fdt_increase_size(blob, 4096);
1535         if (ret) {
1536                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1537                 return ret;
1538         }
1539         if (stk5_v5)
1540                 karo_fdt_enable_node(blob, "stk5led", 0);
1541
1542         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1543
1544         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1545                                 ARRAY_SIZE(tx6_touchpanels));
1546         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1547         karo_fdt_fixup_flexcan(blob, stk5_v5);
1548
1549 #ifdef CONFIG_SYS_LVDS_IF
1550         karo_fdt_update_fb_mode(blob, video_mode, "/lvds0-panel");
1551         karo_fdt_update_fb_mode(blob, video_mode, "/lvds1-panel");
1552 #else
1553         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1554 #endif
1555         return 0;
1556 }
1557 #endif /* CONFIG_OF_BOARD_SETUP */