karo: tx6: indentation cleanup
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012-2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
35 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
36 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
37 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
38
39 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
40 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
41 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
42
43 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
44 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
45 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
46
47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
48 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
49 #else
50 #define TEMPERATURE_MIN                 (-40)
51 #endif
52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
53 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
54 #else
55 #define TEMPERATURE_HOT                 80
56 #endif
57
58 DECLARE_GLOBAL_DATA_PTR;
59
60 #define MUX_CFG_SION            IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
61
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 #ifdef CONFIG_SECURE_BOOT
64 char __csf_data[0] __attribute__((section(".__csf_data")));
65 #endif
66
67 #define TX6_DEFAULT_PAD_CTRL    MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
68                                              PAD_CTL_SPEED_MED |        \
69                                              PAD_CTL_DSE_40ohm |        \
70                                              PAD_CTL_SRE_FAST)
71 #define TX6_FEC_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
72                                              PAD_CTL_SPEED_MED |        \
73                                              PAD_CTL_DSE_40ohm |        \
74                                              PAD_CTL_SRE_FAST)
75 #define TX6_GPIO_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
76                                              PAD_CTL_SPEED_MED |        \
77                                              PAD_CTL_DSE_34ohm |        \
78                                              PAD_CTL_SRE_FAST)
79 #define TX6_I2C_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
80                                              PAD_CTL_HYS |              \
81                                              PAD_CTL_SPEED_LOW |        \
82                                              PAD_CTL_DSE_40ohm |        \
83                                              PAD_CTL_SRE_SLOW)
84
85 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
86         /* RESET_OUT */
87         MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
88
89         /* UART pads */
90 #if CONFIG_MXC_UART_BASE == UART1_BASE
91         MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
92         MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
93         MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
94         MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
95 #endif
96 #if CONFIG_MXC_UART_BASE == UART2_BASE
97         MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
98         MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
99         MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
100         MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
101 #endif
102 #if CONFIG_MXC_UART_BASE == UART3_BASE
103         MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
104         MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
105         MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
106         MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
107 #endif
108         /* internal I2C */
109         MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
110         MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
111
112         /* FEC PHY GPIO functions */
113         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
114         TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
115         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
116         TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
117         MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
118 };
119
120 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
121         /* FEC functions */
122         MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
123         MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
124         MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL,
125         MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
126         MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
127         MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
128         MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
129         MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
130         MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
131         MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
132 };
133
134 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
135         /* internal I2C */
136         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
137         TX6_GPIO_PAD_CTRL,
138         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
139         TX6_GPIO_PAD_CTRL,
140 };
141
142 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
143         /* internal I2C */
144         MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
145         MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
146 };
147
148 static const struct gpio const tx6qdl_gpios[] = {
149         /* These two entries are used to forcefully reinitialize the I2C bus */
150         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
151         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
152
153         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
154         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
155         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
156         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
157 };
158
159 static int pmic_addr __data;
160
161 #if defined(TX6_I2C1_SCL_GPIO) && defined(TX6_I2C1_SDA_GPIO)
162 #define SCL_BANK        (TX6_I2C1_SCL_GPIO / 32)
163 #define SDA_BANK        (TX6_I2C1_SDA_GPIO / 32)
164 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
165 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
166
167 static void * const gpio_ports[] = {
168         (void *)GPIO1_BASE_ADDR,
169         (void *)GPIO2_BASE_ADDR,
170         (void *)GPIO3_BASE_ADDR,
171         (void *)GPIO4_BASE_ADDR,
172         (void *)GPIO5_BASE_ADDR,
173         (void *)GPIO6_BASE_ADDR,
174         (void *)GPIO7_BASE_ADDR,
175 };
176
177 static void tx6_i2c_recover(void)
178 {
179         int i;
180         int bad = 0;
181         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
182         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
183
184         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
185             (readl(&sda_regs->gpio_psr) & SDA_BIT))
186                 return;
187
188         debug("Clearing I2C bus\n");
189         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
190                 printf("I2C SCL stuck LOW\n");
191                 bad++;
192
193                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
194                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
195
196                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
197                                                  ARRAY_SIZE(tx6_i2c_gpio_pads));
198         }
199         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
200                 printf("I2C SDA stuck LOW\n");
201
202                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
203                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
204                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
205
206                 if (!bad++)
207                         imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
208                                                          ARRAY_SIZE(tx6_i2c_gpio_pads));
209
210                 udelay(10);
211
212                 for (i = 0; i < 18; i++) {
213                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
214
215                         debug("%sing SCL\n",
216                               (reg & SCL_BIT) ? "Sett" : "Clear");
217                         writel(reg, &scl_regs->gpio_dr);
218                         udelay(5);
219                         if (reg & SCL_BIT) {
220                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
221                                         break;
222                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
223                                         break;
224                                 break;
225                         }
226                 }
227         }
228         if (bad) {
229                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
230                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
231
232                 if (scl && sda) {
233                         printf("I2C bus recovery succeeded\n");
234                 } else {
235                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
236                                scl, sda);
237                 }
238                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
239                                                  ARRAY_SIZE(tx6_i2c_pads));
240         }
241 }
242 #endif
243
244 /* placed in section '.data' to prevent overwriting relocation info
245  * overlayed with bss
246  */
247 static u32 wrsr __data;
248
249 #define WRSR_POR                        (1 << 4)
250 #define WRSR_TOUT                       (1 << 1)
251 #define WRSR_SFTW                       (1 << 0)
252
253 static void print_reset_cause(void)
254 {
255         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
256         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
257         u32 srsr;
258         char *dlm = "";
259
260         printf("Reset cause: ");
261
262         srsr = readl(&src_regs->srsr);
263         wrsr = readw(wdt_base + 4);
264
265         if (wrsr & WRSR_POR) {
266                 printf("%sPOR", dlm);
267                 dlm = " | ";
268         }
269         if (srsr & 0x00004) {
270                 printf("%sCSU", dlm);
271                 dlm = " | ";
272         }
273         if (srsr & 0x00008) {
274                 printf("%sIPP USER", dlm);
275                 dlm = " | ";
276         }
277         if (srsr & 0x00010) {
278                 if (wrsr & WRSR_SFTW) {
279                         printf("%sSOFT", dlm);
280                         dlm = " | ";
281                 }
282                 if (wrsr & WRSR_TOUT) {
283                         printf("%sWDOG", dlm);
284                         dlm = " | ";
285                 }
286         }
287         if (srsr & 0x00020) {
288                 printf("%sJTAG HIGH-Z", dlm);
289                 dlm = " | ";
290         }
291         if (srsr & 0x00040) {
292                 printf("%sJTAG SW", dlm);
293                 dlm = " | ";
294         }
295         if (srsr & 0x10000) {
296                 printf("%sWARM BOOT", dlm);
297                 dlm = " | ";
298         }
299         if (dlm[0] == '\0')
300                 printf("unknown");
301
302         printf("\n");
303 }
304
305 static const char __data *tx6_mod_suffix;
306
307 #ifdef CONFIG_IMX6_THERMAL
308 #include <thermal.h>
309 #include <imx_thermal.h>
310 #include <fuse.h>
311
312 static void print_temperature(void)
313 {
314         struct udevice *thermal_dev;
315         int cpu_tmp, minc, maxc, ret;
316         char const *grade_str;
317         static u32 __data thermal_calib;
318
319         puts("Temperature: ");
320         switch (get_cpu_temp_grade(&minc, &maxc)) {
321         case TEMP_AUTOMOTIVE:
322                 grade_str = "Automotive";
323                 break;
324         case TEMP_INDUSTRIAL:
325                 grade_str = "Industrial";
326                 break;
327         case TEMP_EXTCOMMERCIAL:
328                 grade_str = "Extended Commercial";
329                 break;
330         default:
331                 grade_str = "Commercial";
332         }
333         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
334         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
335         if (ret == 0) {
336                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
337
338                 if (ret == 0)
339                         printf(" at %dC", cpu_tmp);
340                 else
341                         puts(" - failed to read sensor data");
342         } else {
343                 puts(" - no sensor device found");
344         }
345
346         if (fuse_read(1, 6, &thermal_calib) == 0) {
347                 printf(" - calibration data 0x%08x\n", thermal_calib);
348         } else {
349                 puts(" - Failed to read thermal calib fuse\n");
350         }
351 }
352 #else
353 static inline void print_temperature(void)
354 {
355 }
356 #endif
357
358 int checkboard(void)
359 {
360         u32 cpurev = get_cpu_rev();
361         char *cpu_str = "?";
362
363         if (is_cpu_type(MXC_CPU_MX6SL)) {
364                 cpu_str = "SL";
365                 tx6_mod_suffix = "?";
366         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
367                 cpu_str = "DL";
368                 tx6_mod_suffix = "U";
369         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
370                 cpu_str = "SOLO";
371                 tx6_mod_suffix = "S";
372         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
373                 cpu_str = "Q";
374                 tx6_mod_suffix = "Q";
375         } else if (is_cpu_type(MXC_CPU_MX6QP)) {
376                 cpu_str = "QP";
377                 tx6_mod_suffix = "QP";
378         }
379
380         printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
381                cpu_str,
382                (cpurev & 0x000F0) >> 4,
383                (cpurev & 0x0000F) >> 0,
384                mxc_get_clock(MXC_ARM_CLK) / 1000000);
385
386         print_temperature();
387         print_reset_cause();
388 #ifdef CONFIG_MX6_TEMPERATURE_HOT
389         check_cpu_temperature(1);
390 #endif
391         tx6_i2c_recover();
392         return 0;
393 }
394
395 /* serial port not initialized at this point */
396 int board_early_init_f(void)
397 {
398         return 0;
399 }
400
401 #ifndef CONFIG_MX6_TEMPERATURE_HOT
402 static bool tx6_temp_check_enabled = true;
403 #else
404 #define tx6_temp_check_enabled  0
405 #endif
406
407 #ifdef CONFIG_TX6_NAND
408 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
409 #else
410 #ifdef CONFIG_MMC_BOOT_SIZE
411 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
412 #else
413 #define TX6_FLASH_SZ    2
414 #endif
415 #endif /* CONFIG_TX6_NAND */
416
417 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
418
419 static char tx6_mem_table[] = {
420         '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
421         '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
422         '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
423         '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
424         '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
425         '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
426         '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
427         '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
428         '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
429         '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
430         '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
431         '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
432 };
433
434 #ifdef CONFIG_RN5T567
435 /* PMIC settings */
436 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
437 #define VDD_CORE_VAL            rn5t_mV_to_regval(1400)         /* DCDC1 */
438 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
439 #define VDD_SOC_VAL             rn5t_mV_to_regval(1400)         /* DCDC2 */
440 #define VDD_SOC_VAL_LP          rn5t_mV_to_regval(1400)
441 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
442 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
443 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3000)         /* DCDC4 */
444 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3000)
445 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
446 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
447 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval2(3300)        /* LDO2 */
448 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval2(3300)
449
450 static struct pmic_regs rn5t567_regs[] = {
451         { RN5T567_NOETIMSET, 0x5, },
452         { RN5T567_DC1DAC, VDD_CORE_VAL, },
453         { RN5T567_DC2DAC, VDD_SOC_VAL, },
454         { RN5T567_DC3DAC, VDD_DDR_VAL, },
455         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
456         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
457         { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
458         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
459         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
460         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
461         { RN5T567_DC2CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
462         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
463         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
464         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
465         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
466         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
467         { RN5T567_LDO2DAC, VDD_IO_EXT_VAL, },
468         { RN5T567_LDOEN1, 0x03, ~0x1f, },
469         { RN5T567_LDOEN2, 0x10, ~0x30, },
470         { RN5T567_LDODIS, 0x1c, ~0x1f, },
471         { RN5T567_INTPOL, 0, },
472         { RN5T567_INTEN, 0x3, },
473         { RN5T567_IREN, 0xf, },
474         { RN5T567_EN_GPIR, 0, },
475 };
476 #endif
477
478 static struct {
479         uchar addr;
480         uchar rev;
481         struct pmic_regs *regs;
482         size_t num_regs;
483 } tx6_mod_revs[] = {
484 #ifdef CONFIG_LTC3676
485         { 0x3c, 1, NULL, 0, },
486 #endif
487 #ifdef CONFIG_RN5T567
488         { 0x33, 3, rn5t567_regs, ARRAY_SIZE(rn5t567_regs), },
489 #endif
490 };
491
492 static inline char tx6_mem_suffix(void)
493 {
494         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
495
496         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
497               TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
498
499         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
500                 return '?';
501         if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
502                 return '7';
503         if (mem_idx == 8)
504                 return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
505         return tx6_mem_table[mem_idx];
506 };
507
508 static int tx6_get_mod_rev(unsigned int pmic_id)
509 {
510         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
511                 return tx6_mod_revs[pmic_id].rev;
512
513         return 0;
514 }
515
516 static int tx6_pmic_probe(void)
517 {
518         int i;
519
520         debug("%s@%d: \n", __func__, __LINE__);
521
522         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
523                 u8 i2c_addr = tx6_mod_revs[i].addr;
524                 int ret = i2c_probe(i2c_addr);
525
526                 if (ret == 0) {
527                         debug("I2C probe succeeded for addr 0x%02x\n",
528                               i2c_addr);
529                         return i;
530                 }
531                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
532         }
533         return -EINVAL;
534 }
535
536 static int tx6_mipi(void)
537 {
538         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
539         struct fuse_bank4_regs *fuse = (void *)ocotp->bank[4].fuse_regs;
540         u32 gp1 = readl(&fuse->gp1);
541
542         debug("Fuse gp1 @ %p = %08x\n", &fuse->gp1, gp1);
543         return gp1 & 1;
544 }
545
546 int board_init(void)
547 {
548         int ret;
549         int pmic_id;
550
551         debug("%s@%d: \n", __func__, __LINE__);
552
553         pmic_id = tx6_pmic_probe();
554         if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
555                 pmic_addr = tx6_mod_revs[pmic_id].addr;
556
557         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
558                tx6_mod_suffix,
559                is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
560                tx6_mipi() ? 2 : is_lvds(), tx6_get_mod_rev(pmic_id),
561                tx6_mem_suffix());
562
563         get_hab_status();
564
565         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
566         if (ret < 0) {
567                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
568         }
569         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
570
571         /* Address of boot parameters */
572         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
573         gd->bd->bi_arch_number = -1;
574
575         if (ctrlc() || (wrsr & WRSR_TOUT)) {
576                 if (wrsr & WRSR_TOUT)
577                         printf("WDOG RESET detected; Skipping PMIC setup\n");
578                 else
579                         printf("<CTRL-C> detected; safeboot enabled\n");
580 #ifndef CONFIG_MX6_TEMPERATURE_HOT
581                 tx6_temp_check_enabled = false;
582 #endif
583                 return 0;
584         }
585
586         ret = tx6_pmic_init(pmic_addr, tx6_mod_revs[pmic_id].regs,
587                             tx6_mod_revs[pmic_id].num_regs);
588         if (ret) {
589                 printf("Failed to setup PMIC voltages: %d\n", ret);
590                 hang();
591         }
592         return 0;
593 }
594
595 int dram_init(void)
596 {
597         debug("%s@%d: \n", __func__, __LINE__);
598
599         /* dram_init must store complete ramsize in gd->ram_size */
600         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
601                                     PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
602         return 0;
603 }
604
605 void dram_init_banksize(void)
606 {
607         debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
608               CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
609         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
610         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
611                                                PHYS_SDRAM_1_SIZE);
612 #if CONFIG_NR_DRAM_BANKS > 1
613         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
614         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
615                                                PHYS_SDRAM_2_SIZE);
616 #endif
617 }
618
619 #ifdef  CONFIG_FSL_ESDHC
620 #define SD_PAD_CTRL             MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
621                                              PAD_CTL_SPEED_MED |        \
622                                              PAD_CTL_DSE_40ohm |        \
623                                              PAD_CTL_SRE_FAST)
624
625 static const iomux_v3_cfg_t mmc0_pads[] = {
626         MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
627         MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
628         MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
629         MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
630         MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
631         MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
632         /* SD1 CD */
633         MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
634 };
635
636 static const iomux_v3_cfg_t mmc1_pads[] = {
637         MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
638         MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
639         MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
640         MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
641         MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
642         MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
643         /* SD2 CD */
644         MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
645 };
646
647 #ifdef CONFIG_TX6_EMMC
648 static const iomux_v3_cfg_t mmc3_pads[] = {
649         MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
650         MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
651         MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
652         MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
653         MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
654         MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
655         /* eMMC RESET */
656         MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
657 };
658 #endif
659
660 static struct tx6_esdhc_cfg {
661         const iomux_v3_cfg_t *pads;
662         int num_pads;
663         enum mxc_clock clkid;
664         struct fsl_esdhc_cfg cfg;
665         int cd_gpio;
666 } tx6qdl_esdhc_cfg[] = {
667 #ifdef CONFIG_TX6_EMMC
668         {
669                 .pads = mmc3_pads,
670                 .num_pads = ARRAY_SIZE(mmc3_pads),
671                 .clkid = MXC_ESDHC4_CLK,
672                 .cfg = {
673                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
674                         .max_bus_width = 4,
675                 },
676                 .cd_gpio = -EINVAL,
677         },
678 #endif
679         {
680                 .pads = mmc0_pads,
681                 .num_pads = ARRAY_SIZE(mmc0_pads),
682                 .clkid = MXC_ESDHC_CLK,
683                 .cfg = {
684                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
685                         .max_bus_width = 4,
686                 },
687                 .cd_gpio = IMX_GPIO_NR(7, 2),
688         },
689         {
690                 .pads = mmc1_pads,
691                 .num_pads = ARRAY_SIZE(mmc1_pads),
692                 .clkid = MXC_ESDHC2_CLK,
693                 .cfg = {
694                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
695                         .max_bus_width = 4,
696                 },
697                 .cd_gpio = IMX_GPIO_NR(7, 3),
698         },
699 };
700
701 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
702 {
703         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
704 }
705
706 int board_mmc_getcd(struct mmc *mmc)
707 {
708         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
709
710         if (cfg->cd_gpio < 0)
711                 return 1;
712
713         debug("SD card %d is %spresent (GPIO %d)\n",
714               cfg - tx6qdl_esdhc_cfg,
715               gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
716               cfg->cd_gpio);
717         return !gpio_get_value(cfg->cd_gpio);
718 }
719
720 int board_mmc_init(bd_t *bis)
721 {
722         int i;
723
724         debug("%s@%d: \n", __func__, __LINE__);
725
726         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
727                 struct mmc *mmc;
728                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
729                 int ret;
730
731                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
732                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
733
734                 if (cfg->cd_gpio >= 0) {
735                         ret = gpio_request_one(cfg->cd_gpio,
736                                                GPIOFLAG_INPUT, "MMC CD");
737                         if (ret) {
738                                 printf("Error %d requesting GPIO%d_%d\n",
739                                        ret, cfg->cd_gpio / 32,
740                                        cfg->cd_gpio % 32);
741                                 continue;
742                         }
743                 }
744
745                 debug("%s: Initializing MMC slot %d\n", __func__, i);
746                 fsl_esdhc_initialize(bis, &cfg->cfg);
747
748                 mmc = find_mmc_device(i);
749                 if (mmc == NULL)
750                         continue;
751                 if (board_mmc_getcd(mmc))
752                         mmc_init(mmc);
753         }
754         return 0;
755 }
756 #endif /* CONFIG_CMD_MMC */
757
758 #ifdef CONFIG_FEC_MXC
759
760 #ifndef ETH_ALEN
761 #define ETH_ALEN 6
762 #endif
763
764 int board_eth_init(bd_t *bis)
765 {
766         int ret;
767
768         debug("%s@%d: \n", __func__, __LINE__);
769
770         /* delay at least 21ms for the PHY internal POR signal to deassert */
771         udelay(22000);
772
773         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
774                                          ARRAY_SIZE(tx6qdl_fec_pads));
775
776         /* Deassert RESET to the external phy */
777         gpio_set_value(TX6_FEC_RST_GPIO, 1);
778
779         ret = cpu_eth_init(bis);
780         if (ret)
781                 printf("cpu_eth_init() failed: %d\n", ret);
782
783         return ret;
784 }
785
786 static void tx6_init_mac(void)
787 {
788         u8 mac[ETH_ALEN];
789
790         imx_get_mac_from_fuse(0, mac);
791         if (!is_valid_ethaddr(mac)) {
792                 printf("No valid MAC address programmed\n");
793                 return;
794         }
795
796         printf("MAC addr from fuse: %pM\n", mac);
797         eth_setenv_enetaddr("ethaddr", mac);
798 }
799 #else
800 static inline void tx6_init_mac(void)
801 {
802 }
803 #endif /* CONFIG_FEC_MXC */
804
805 enum {
806         LED_STATE_INIT = -1,
807         LED_STATE_OFF,
808         LED_STATE_ON,
809 };
810
811 static inline int calc_blink_rate(void)
812 {
813         if (!tx6_temp_check_enabled)
814                 return CONFIG_SYS_HZ;
815
816         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
817                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
818                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
819 }
820
821 void show_activity(int arg)
822 {
823         static int led_state = LED_STATE_INIT;
824         static int blink_rate;
825         static ulong last;
826
827         if (led_state == LED_STATE_INIT) {
828                 last = get_timer(0);
829                 gpio_set_value(TX6_LED_GPIO, 1);
830                 led_state = LED_STATE_ON;
831                 blink_rate = calc_blink_rate();
832         } else {
833                 if (get_timer(last) > blink_rate) {
834                         blink_rate = calc_blink_rate();
835                         last = get_timer_masked();
836                         if (led_state == LED_STATE_ON) {
837                                 gpio_set_value(TX6_LED_GPIO, 0);
838                         } else {
839                                 gpio_set_value(TX6_LED_GPIO, 1);
840                         }
841                         led_state = 1 - led_state;
842                 }
843         }
844 }
845
846 static const iomux_v3_cfg_t stk5_pads[] = {
847         /* SW controlled LED on STK5 baseboard */
848         MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
849
850         /* I2C bus on DIMM pins 40/41 */
851         MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
852         MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
853
854         /* TSC200x PEN IRQ */
855         MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
856
857         /* EDT-FT5x06 Polytouch panel */
858         MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
859         MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
860         MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
861
862         /* USBH1 */
863         MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
864         MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
865         /* USBOTG */
866         MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
867         MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
868         MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
869 };
870
871 static const struct gpio stk5_gpios[] = {
872         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
873
874         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
875         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
876         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
877         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
878         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
879 };
880
881 #ifdef CONFIG_LCD
882 vidinfo_t panel_info = {
883         /* set to max. size supported by SoC */
884         .vl_col = 1920,
885         .vl_row = 1080,
886
887         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
888 };
889
890 static struct fb_videomode tx6_fb_modes[] = {
891         {
892                 /* Standard VGA timing */
893                 .name           = "VGA",
894                 .refresh        = 60,
895                 .xres           = 640,
896                 .yres           = 480,
897                 .pixclock       = KHZ2PICOS(25175),
898                 .left_margin    = 48,
899                 .hsync_len      = 96,
900                 .right_margin   = 16,
901                 .upper_margin   = 31,
902                 .vsync_len      = 2,
903                 .lower_margin   = 12,
904                 .sync           = FB_SYNC_CLK_LAT_FALL,
905         },
906         {
907                 /* Emerging ETV570 640 x 480 display. Syncs low active,
908                  * DE high active, 115.2 mm x 86.4 mm display area
909                  * VGA compatible timing
910                  */
911                 .name           = "ETV570",
912                 .refresh        = 60,
913                 .xres           = 640,
914                 .yres           = 480,
915                 .pixclock       = KHZ2PICOS(25175),
916                 .left_margin    = 114,
917                 .hsync_len      = 30,
918                 .right_margin   = 16,
919                 .upper_margin   = 32,
920                 .vsync_len      = 3,
921                 .lower_margin   = 10,
922                 .sync           = FB_SYNC_CLK_LAT_FALL,
923         },
924         {
925                 /* Emerging ETM0700G0DH6 800 x 480 display.
926                  * 152.4 mm x 91.44 mm display area.
927                  */
928                 .name           = "ET0700",
929                 .refresh        = 60,
930                 .xres           = 800,
931                 .yres           = 480,
932                 .pixclock       = KHZ2PICOS(33260),
933                 .left_margin    = 88,
934                 .hsync_len      = 128,
935                 .right_margin   = 40,
936                 .upper_margin   = 33,
937                 .vsync_len      = 2,
938                 .lower_margin   = 10,
939                 .sync           = FB_SYNC_CLK_LAT_FALL,
940         },
941 #ifndef CONFIG_SYS_LVDS_IF
942         {
943                 /* Emerging ET0350G0DH6 320 x 240 display.
944                  * 70.08 mm x 52.56 mm display area.
945                  */
946                 .name           = "ET0350",
947                 .refresh        = 60,
948                 .xres           = 320,
949                 .yres           = 240,
950                 .pixclock       = KHZ2PICOS(6500),
951                 .left_margin    = 34,
952                 .hsync_len      = 34,
953                 .right_margin   = 20,
954                 .upper_margin   = 15,
955                 .vsync_len      = 3,
956                 .lower_margin   = 4,
957                 .sync           = FB_SYNC_CLK_LAT_FALL,
958         },
959         {
960                 /* Emerging ET0430G0DH6 480 x 272 display.
961                  * 95.04 mm x 53.856 mm display area.
962                  */
963                 .name           = "ET0430",
964                 .refresh        = 60,
965                 .xres           = 480,
966                 .yres           = 272,
967                 .pixclock       = KHZ2PICOS(9000),
968                 .left_margin    = 2,
969                 .hsync_len      = 41,
970                 .right_margin   = 2,
971                 .upper_margin   = 2,
972                 .vsync_len      = 10,
973                 .lower_margin   = 2,
974         },
975         {
976                 /* Emerging ET0500G0DH6 800 x 480 display.
977                  * 109.6 mm x 66.4 mm display area.
978                  */
979                 .name           = "ET0500",
980                 .refresh        = 60,
981                 .xres           = 800,
982                 .yres           = 480,
983                 .pixclock       = KHZ2PICOS(33260),
984                 .left_margin    = 88,
985                 .hsync_len      = 128,
986                 .right_margin   = 40,
987                 .upper_margin   = 33,
988                 .vsync_len      = 2,
989                 .lower_margin   = 10,
990                 .sync           = FB_SYNC_CLK_LAT_FALL,
991         },
992         {
993                 /* Emerging ETQ570G0DH6 320 x 240 display.
994                  * 115.2 mm x 86.4 mm display area.
995                  */
996                 .name           = "ETQ570",
997                 .refresh        = 60,
998                 .xres           = 320,
999                 .yres           = 240,
1000                 .pixclock       = KHZ2PICOS(6400),
1001                 .left_margin    = 38,
1002                 .hsync_len      = 30,
1003                 .right_margin   = 30,
1004                 .upper_margin   = 16, /* 15 according to datasheet */
1005                 .vsync_len      = 3, /* TVP -> 1>x>5 */
1006                 .lower_margin   = 4, /* 4.5 according to datasheet */
1007                 .sync           = FB_SYNC_CLK_LAT_FALL,
1008         },
1009 #else
1010         {
1011                 /* HannStar HSD100PXN1
1012                  * 202.7m mm x 152.06 mm display area.
1013                  */
1014                 .name           = "HSD100PXN1",
1015                 .refresh        = 60,
1016                 .xres           = 1024,
1017                 .yres           = 768,
1018                 .pixclock       = KHZ2PICOS(65000),
1019                 .left_margin    = 0,
1020                 .hsync_len      = 0,
1021                 .right_margin   = 320,
1022                 .upper_margin   = 0,
1023                 .vsync_len      = 0,
1024                 .lower_margin   = 38,
1025                 .sync           = FB_SYNC_CLK_LAT_FALL,
1026         },
1027 #endif
1028         {
1029                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1030                 .refresh        = 60,
1031                 .left_margin    = 48,
1032                 .hsync_len      = 96,
1033                 .right_margin   = 16,
1034                 .upper_margin   = 31,
1035                 .vsync_len      = 2,
1036                 .lower_margin   = 12,
1037                 .sync           = FB_SYNC_CLK_LAT_FALL,
1038         },
1039 };
1040
1041 static int lcd_enabled = 1;
1042 static int lcd_bl_polarity;
1043
1044 static int lcd_backlight_polarity(void)
1045 {
1046         return lcd_bl_polarity;
1047 }
1048
1049 void lcd_enable(void)
1050 {
1051         /* HACK ALERT:
1052          * global variable from common/lcd.c
1053          * Set to 0 here to prevent messages from going to LCD
1054          * rather than serial console
1055          */
1056         lcd_is_enabled = 0;
1057
1058         if (lcd_enabled) {
1059                 karo_load_splashimage(1);
1060
1061                 debug("Switching LCD on\n");
1062                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1063                 udelay(100);
1064                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1065                 udelay(300000);
1066                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1067                                lcd_backlight_polarity());
1068         }
1069 }
1070
1071 void lcd_disable(void)
1072 {
1073         if (lcd_enabled) {
1074                 printf("Disabling LCD\n");
1075                 ipuv3_fb_shutdown();
1076         }
1077 }
1078
1079 void lcd_panel_disable(void)
1080 {
1081         if (lcd_enabled) {
1082                 debug("Switching LCD off\n");
1083                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1084                                !lcd_backlight_polarity());
1085                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1086                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1087         }
1088 }
1089
1090 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1091         /* LCD RESET */
1092         MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
1093         /* LCD POWER_ENABLE */
1094         MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
1095         /* LCD Backlight (PWM) */
1096         MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
1097
1098 #ifndef CONFIG_SYS_LVDS_IF
1099         /* Display */
1100         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
1101         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
1102         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
1103         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
1104         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
1105         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
1106         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
1107         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
1108         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
1109         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
1110         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
1111         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
1112         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
1113         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
1114         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
1115         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
1116         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
1117         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
1118         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
1119         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
1120         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
1121         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
1122         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
1123         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
1124         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
1125         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
1126         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
1127         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
1128 #endif
1129 };
1130
1131 static const struct gpio stk5_lcd_gpios[] = {
1132         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1133         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1134         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1135 };
1136
1137 void lcd_ctrl_init(void *lcdbase)
1138 {
1139         int color_depth = 24;
1140         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1141         const char *vm;
1142         unsigned long val;
1143         int refresh = 60;
1144         struct fb_videomode *p = &tx6_fb_modes[0];
1145         struct fb_videomode fb_mode;
1146         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1147         int pix_fmt;
1148         int lcd_bus_width;
1149         unsigned long di_clk_rate = 65000000;
1150
1151         if (!lcd_enabled) {
1152                 debug("LCD disabled\n");
1153                 goto disable;
1154         }
1155
1156         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1157                 debug("Disabling LCD\n");
1158                 lcd_enabled = 0;
1159                 setenv("splashimage", NULL);
1160                 goto disable;
1161         }
1162
1163         karo_fdt_move_fdt();
1164         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1165
1166         if (video_mode == NULL) {
1167                 debug("Disabling LCD\n");
1168                 lcd_enabled = 0;
1169                 goto disable;
1170         }
1171         vm = video_mode;
1172         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1173                 p = &fb_mode;
1174                 debug("Using video mode from FDT\n");
1175                 vm += strlen(vm);
1176                 if (fb_mode.xres > panel_info.vl_col ||
1177                     fb_mode.yres > panel_info.vl_row) {
1178                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1179                                fb_mode.xres, fb_mode.yres,
1180                                panel_info.vl_col, panel_info.vl_row);
1181                         lcd_enabled = 0;
1182                         goto disable;
1183                 }
1184         }
1185         if (p->name != NULL)
1186                 debug("Trying compiled-in video modes\n");
1187         while (p->name != NULL) {
1188                 if (strcmp(p->name, vm) == 0) {
1189                         debug("Using video mode: '%s'\n", p->name);
1190                         vm += strlen(vm);
1191                         break;
1192                 }
1193                 p++;
1194         }
1195         if (*vm != '\0')
1196                 debug("Trying to decode video_mode: '%s'\n", vm);
1197         while (*vm != '\0') {
1198                 if (*vm >= '0' && *vm <= '9') {
1199                         char *end;
1200
1201                         val = simple_strtoul(vm, &end, 0);
1202                         if (end > vm) {
1203                                 if (!xres_set) {
1204                                         if (val > panel_info.vl_col)
1205                                                 val = panel_info.vl_col;
1206                                         p->xres = val;
1207                                         panel_info.vl_col = val;
1208                                         xres_set = 1;
1209                                 } else if (!yres_set) {
1210                                         if (val > panel_info.vl_row)
1211                                                 val = panel_info.vl_row;
1212                                         p->yres = val;
1213                                         panel_info.vl_row = val;
1214                                         yres_set = 1;
1215                                 } else if (!bpp_set) {
1216                                         switch (val) {
1217                                         case 32:
1218                                         case 24:
1219                                                 if (is_lvds())
1220                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1221                                                 /* fallthru */
1222                                         case 16:
1223                                         case 8:
1224                                                 color_depth = val;
1225                                                 break;
1226
1227                                         case 18:
1228                                                 if (is_lvds()) {
1229                                                         color_depth = val;
1230                                                         break;
1231                                                 }
1232                                                 /* fallthru */
1233                                         default:
1234                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1235                                                        end - vm, vm,
1236                                                        color_depth);
1237                                         }
1238                                         bpp_set = 1;
1239                                 } else if (!refresh_set) {
1240                                         refresh = val;
1241                                         refresh_set = 1;
1242                                 }
1243                         }
1244                         vm = end;
1245                 }
1246                 switch (*vm) {
1247                 case '@':
1248                         bpp_set = 1;
1249                         /* fallthru */
1250                 case '-':
1251                         yres_set = 1;
1252                         /* fallthru */
1253                 case 'x':
1254                         xres_set = 1;
1255                         /* fallthru */
1256                 case 'M':
1257                 case 'R':
1258                         vm++;
1259                         break;
1260
1261                 default:
1262                         if (*vm != '\0')
1263                                 vm++;
1264                 }
1265         }
1266         if (p->xres == 0 || p->yres == 0) {
1267                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1268                 lcd_enabled = 0;
1269                 printf("Supported video modes are:");
1270                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1271                         printf(" %s", p->name);
1272                 }
1273                 printf("\n");
1274                 goto disable;
1275         }
1276         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1277                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1278                        p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1279                 lcd_enabled = 0;
1280                 goto disable;
1281         }
1282         panel_info.vl_col = p->xres;
1283         panel_info.vl_row = p->yres;
1284
1285         switch (color_depth) {
1286         case 8:
1287                 panel_info.vl_bpix = LCD_COLOR8;
1288                 break;
1289         case 16:
1290                 panel_info.vl_bpix = LCD_COLOR16;
1291                 break;
1292         default:
1293                 panel_info.vl_bpix = LCD_COLOR32;
1294         }
1295
1296         p->pixclock = KHZ2PICOS(refresh *
1297                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1298                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1299                                 1000);
1300         debug("Pixel clock set to %lu.%03lu MHz\n",
1301               PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1302
1303         if (p != &fb_mode) {
1304                 int ret;
1305
1306                 debug("Creating new display-timing node from '%s'\n",
1307                       video_mode);
1308                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1309                 if (ret)
1310                         printf("Failed to create new display-timing node from '%s': %d\n",
1311                                video_mode, ret);
1312         }
1313
1314         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1315         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1316                                          ARRAY_SIZE(stk5_lcd_pads));
1317
1318         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1319         switch (lcd_bus_width) {
1320         case 24:
1321                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1322                 break;
1323
1324         case 18:
1325                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1326                 break;
1327
1328         case 16:
1329                 if (!is_lvds()) {
1330                         pix_fmt = IPU_PIX_FMT_RGB565;
1331                         break;
1332                 }
1333                 /* fallthru */
1334         default:
1335                 lcd_enabled = 0;
1336                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1337                        lcd_bus_width);
1338                 goto disable;
1339         }
1340         if (is_lvds()) {
1341                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1342                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1343                 uint32_t gpr2;
1344                 uint32_t gpr3;
1345
1346                 if (lvds_chan_mask == 0) {
1347                         printf("No LVDS channel active\n");
1348                         lcd_enabled = 0;
1349                         goto disable;
1350                 }
1351
1352                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1353                 if (lcd_bus_width == 24)
1354                         gpr2 |= (1 << 5) | (1 << 7);
1355                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1356                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1357                 debug("writing %08x to GPR2[%08x]\n", gpr2,
1358                       IOMUXC_BASE_ADDR + 8);
1359                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1360
1361                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1362                 gpr3 &= ~((3 << 8) | (3 << 6));
1363                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1364         }
1365         if (karo_load_splashimage(0) == 0) {
1366                 int ret;
1367
1368                 debug("Initializing LCD controller\n");
1369                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1370                                     is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1371                                     di_clk_rate, -1);
1372                 if (ret) {
1373                         printf("Failed to initialize FB driver: %d\n", ret);
1374                         lcd_enabled = 0;
1375                 }
1376         } else {
1377                 debug("Skipping initialization of LCD controller\n");
1378         }
1379         return;
1380
1381  disable:
1382         lcd_enabled = 0;
1383         panel_info.vl_col = 0;
1384         panel_info.vl_row = 0;
1385 }
1386 #else
1387 #define lcd_enabled 0
1388 #endif /* CONFIG_LCD */
1389
1390 static void stk5_board_init(void)
1391 {
1392         int ret;
1393
1394         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1395         if (ret < 0) {
1396                 printf("Failed to request stk5_gpios: %d\n", ret);
1397                 return;
1398         }
1399         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1400 }
1401
1402 static void stk5v3_board_init(void)
1403 {
1404         stk5_board_init();
1405 }
1406
1407 static void stk5v5_board_init(void)
1408 {
1409         int ret;
1410
1411         stk5_board_init();
1412
1413         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1414                                "Flexcan Transceiver");
1415         if (ret) {
1416                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1417                 return;
1418         }
1419
1420         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
1421                                TX6_GPIO_PAD_CTRL);
1422 }
1423
1424 static void tx6qdl_set_cpu_clock(void)
1425 {
1426         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1427
1428         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1429                 return;
1430
1431         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1432                 printf("%s detected; skipping cpu clock change\n",
1433                        (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1434                 return;
1435         }
1436         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1437                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1438                 printf("CPU clock set to %lu.%03lu MHz\n",
1439                        cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1440         } else {
1441                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1442         }
1443 }
1444
1445 int board_late_init(void)
1446 {
1447         const char *baseboard;
1448
1449         debug("%s@%d: \n", __func__, __LINE__);
1450
1451         env_cleanup();
1452
1453         if (tx6_temp_check_enabled)
1454                 check_cpu_temperature(1);
1455
1456         tx6qdl_set_cpu_clock();
1457
1458         if (had_ctrlc())
1459                 setenv_ulong("safeboot", 1);
1460         else if (wrsr & WRSR_TOUT)
1461                 setenv_ulong("wdreset", 1);
1462         else
1463                 karo_fdt_move_fdt();
1464
1465         baseboard = getenv("baseboard");
1466         if (!baseboard)
1467                 goto exit;
1468
1469         printf("Baseboard: %s\n", baseboard);
1470
1471         if (strncmp(baseboard, "stk5", 4) == 0) {
1472                 if ((strlen(baseboard) == 4) ||
1473                     strcmp(baseboard, "stk5-v3") == 0) {
1474                         stk5v3_board_init();
1475                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1476                         const char *otg_mode = getenv("otg_mode");
1477
1478                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1479                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1480                                        otg_mode, baseboard);
1481                                 setenv("otg_mode", "none");
1482                         }
1483                         stk5v5_board_init();
1484                 } else {
1485                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1486                                baseboard + 4);
1487                 }
1488         } else {
1489                 printf("WARNING: Unsupported baseboard: '%s'\n",
1490                        baseboard);
1491                 if (!had_ctrlc())
1492                         return -EINVAL;
1493         }
1494
1495 exit:
1496         tx6_init_mac();
1497
1498         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1499         clear_ctrlc();
1500         return 0;
1501 }
1502
1503 #ifdef CONFIG_SERIAL_TAG
1504 void get_board_serial(struct tag_serialnr *serialnr)
1505 {
1506         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1507         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1508
1509         serialnr->low = readl(&fuse->cfg0);
1510         serialnr->high = readl(&fuse->cfg1);
1511 }
1512 #endif
1513
1514 #if defined(CONFIG_OF_BOARD_SETUP)
1515 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1516 #include <jffs2/jffs2.h>
1517 #include <mtd_node.h>
1518 static struct node_info nodes[] = {
1519         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1520 };
1521 #else
1522 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1523 #endif
1524
1525 static const char *tx6_touchpanels[] = {
1526         "ti,tsc2007",
1527         "edt,edt-ft5x06",
1528         "eeti,egalax_ts",
1529 };
1530
1531 int ft_board_setup(void *blob, bd_t *bd)
1532 {
1533         const char *baseboard = getenv("baseboard");
1534         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1535         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1536         int ret;
1537
1538         ret = fdt_increase_size(blob, 4096);
1539         if (ret) {
1540                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1541                 return ret;
1542         }
1543         if (stk5_v5)
1544                 karo_fdt_enable_node(blob, "stk5led", 0);
1545
1546         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1547
1548         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1549                                   ARRAY_SIZE(tx6_touchpanels));
1550         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1551         karo_fdt_fixup_flexcan(blob, stk5_v5);
1552
1553 #ifdef CONFIG_SYS_LVDS_IF
1554         karo_fdt_update_fb_mode(blob, video_mode, "/lvds0-panel");
1555         karo_fdt_update_fb_mode(blob, video_mode, "/lvds1-panel");
1556 #else
1557         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1558 #endif
1559         return 0;
1560 }
1561 #endif /* CONFIG_OF_BOARD_SETUP */