karo: tx6: use GP1 fuse for MIPI variant detection
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012-2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
35 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
36 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
37 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
38
39 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
40 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
41 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
42
43 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
44 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
45 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
46
47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
48 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
49 #else
50 #define TEMPERATURE_MIN                 (-40)
51 #endif
52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
53 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
54 #else
55 #define TEMPERATURE_HOT                 80
56 #endif
57
58 DECLARE_GLOBAL_DATA_PTR;
59
60 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
61
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 #ifdef CONFIG_SECURE_BOOT
64 char __csf_data[0] __attribute__((section(".__csf_data")));
65 #endif
66
67 #define TX6_DEFAULT_PAD_CTRL    MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
68                                         PAD_CTL_SPEED_MED |             \
69                                         PAD_CTL_DSE_40ohm |             \
70                                         PAD_CTL_SRE_FAST)
71 #define TX6_FEC_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
72                                         PAD_CTL_SPEED_MED |             \
73                                         PAD_CTL_DSE_40ohm |             \
74                                         PAD_CTL_SRE_FAST)
75 #define TX6_GPIO_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
76                                         PAD_CTL_SPEED_MED |             \
77                                         PAD_CTL_DSE_34ohm |             \
78                                         PAD_CTL_SRE_FAST)
79 #define TX6_I2C_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
80                                         PAD_CTL_HYS |                   \
81                                         PAD_CTL_SPEED_LOW |             \
82                                         PAD_CTL_DSE_40ohm |             \
83                                         PAD_CTL_SRE_SLOW)
84
85 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
86         /* RESET_OUT */
87         MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
88
89         /* UART pads */
90 #if CONFIG_MXC_UART_BASE == UART1_BASE
91         MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
92         MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
93         MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
94         MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
95 #endif
96 #if CONFIG_MXC_UART_BASE == UART2_BASE
97         MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
98         MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
99         MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
100         MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
101 #endif
102 #if CONFIG_MXC_UART_BASE == UART3_BASE
103         MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
104         MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
105         MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
106         MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
107 #endif
108         /* internal I2C */
109         MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
110         MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
111
112         /* FEC PHY GPIO functions */
113         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
114                         TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
115         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
116                         TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
117         MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
118 };
119
120 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
121         /* FEC functions */
122         MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
123         MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
124         MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL,
125         MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
126         MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
127         MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
128         MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
129         MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
130         MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
131         MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
132 };
133
134 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
135         /* internal I2C */
136         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
137                         TX6_GPIO_PAD_CTRL,
138         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
139                         TX6_GPIO_PAD_CTRL,
140 };
141
142 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
143         /* internal I2C */
144         MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
145         MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
146 };
147
148 static const struct gpio const tx6qdl_gpios[] = {
149         /* These two entries are used to forcefully reinitialize the I2C bus */
150         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
151         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
152
153         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
154         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
155         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
156         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
157 };
158
159 static int pmic_addr __data;
160
161 #if defined(CONFIG_SOC_MX6Q)
162 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
163 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
164 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
165 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
166 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
167 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
168 #define I2C1_SEL_INPUT_VAL                      0
169 #endif
170 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
171 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
172 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
173 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
174 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
175 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
176 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
177 #define I2C1_SEL_INPUT_VAL                      1
178 #endif
179
180 #define GPIO_DR 0
181 #define GPIO_DIR 4
182 #define GPIO_PSR 8
183
184 static void tx6_i2c_recover(void)
185 {
186         int i;
187         int bad = 0;
188 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
189 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
190
191         if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
192                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
193                 return;
194
195         debug("Clearing I2C bus\n");
196         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
197                 printf("I2C SCL stuck LOW\n");
198                 bad++;
199
200                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
201                         GPIO3_BASE_ADDR + GPIO_DR);
202                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
203                         GPIO3_BASE_ADDR + GPIO_DIR);
204         }
205         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
206                 printf("I2C SDA stuck LOW\n");
207                 bad++;
208
209                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
210                         GPIO3_BASE_ADDR + GPIO_DIR);
211                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
212                         GPIO3_BASE_ADDR + GPIO_DR);
213                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
214                         GPIO3_BASE_ADDR + GPIO_DIR);
215
216                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
217                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
218                 udelay(10);
219
220                 for (i = 0; i < 18; i++) {
221                         u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
222
223                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
224                         writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
225                         udelay(10);
226                         if (reg & SCL_BIT &&
227                                 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
228                                 break;
229                 }
230         }
231         if (bad) {
232                 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
233
234                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
235                         printf("I2C bus recovery succeeded\n");
236                 } else {
237                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
238                                 SCL_BIT | SDA_BIT);
239                 }
240         }
241         debug("Setting up I2C Pads\n");
242         imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
243                                         ARRAY_SIZE(tx6_i2c_pads));
244 }
245
246 /* placed in section '.data' to prevent overwriting relocation info
247  * overlayed with bss
248  */
249 static u32 wrsr __data;
250
251 #define WRSR_POR                        (1 << 4)
252 #define WRSR_TOUT                       (1 << 1)
253 #define WRSR_SFTW                       (1 << 0)
254
255 static void print_reset_cause(void)
256 {
257         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
258         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
259         u32 srsr;
260         char *dlm = "";
261
262         printf("Reset cause: ");
263
264         srsr = readl(&src_regs->srsr);
265         wrsr = readw(wdt_base + 4);
266
267         if (wrsr & WRSR_POR) {
268                 printf("%sPOR", dlm);
269                 dlm = " | ";
270         }
271         if (srsr & 0x00004) {
272                 printf("%sCSU", dlm);
273                 dlm = " | ";
274         }
275         if (srsr & 0x00008) {
276                 printf("%sIPP USER", dlm);
277                 dlm = " | ";
278         }
279         if (srsr & 0x00010) {
280                 if (wrsr & WRSR_SFTW) {
281                         printf("%sSOFT", dlm);
282                         dlm = " | ";
283                 }
284                 if (wrsr & WRSR_TOUT) {
285                         printf("%sWDOG", dlm);
286                         dlm = " | ";
287                 }
288         }
289         if (srsr & 0x00020) {
290                 printf("%sJTAG HIGH-Z", dlm);
291                 dlm = " | ";
292         }
293         if (srsr & 0x00040) {
294                 printf("%sJTAG SW", dlm);
295                 dlm = " | ";
296         }
297         if (srsr & 0x10000) {
298                 printf("%sWARM BOOT", dlm);
299                 dlm = " | ";
300         }
301         if (dlm[0] == '\0')
302                 printf("unknown");
303
304         printf("\n");
305 }
306
307 static const char __data *tx6_mod_suffix;
308
309 #ifdef CONFIG_IMX6_THERMAL
310 #include <thermal.h>
311 #include <imx_thermal.h>
312 #include <fuse.h>
313
314 static void print_temperature(void)
315 {
316         struct udevice *thermal_dev;
317         int cpu_tmp, minc, maxc, ret;
318         char const *grade_str;
319         static u32 __data thermal_calib;
320
321         puts("Temperature: ");
322         switch (get_cpu_temp_grade(&minc, &maxc)) {
323         case TEMP_AUTOMOTIVE:
324                 grade_str = "Automotive";
325                 break;
326         case TEMP_INDUSTRIAL:
327                 grade_str = "Industrial";
328                 break;
329         case TEMP_EXTCOMMERCIAL:
330                 grade_str = "Extended Commercial";
331                 break;
332         default:
333                 grade_str = "Commercial";
334         }
335         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
336         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
337         if (ret == 0) {
338                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
339
340                 if (ret == 0)
341                         printf(" at %dC", cpu_tmp);
342                 else
343                         puts(" - failed to read sensor data");
344         } else {
345                 puts(" - no sensor device found");
346         }
347
348         if (fuse_read(1, 6, &thermal_calib) == 0) {
349                 printf(" - calibration data 0x%08x\n", thermal_calib);
350         } else {
351                 puts(" - Failed to read thermal calib fuse\n");
352         }
353 }
354 #else
355 static inline void print_temperature(void)
356 {
357 }
358 #endif
359
360 int checkboard(void)
361 {
362         u32 cpurev = get_cpu_rev();
363         char *cpu_str = "?";
364
365         if (is_cpu_type(MXC_CPU_MX6SL)) {
366                 cpu_str = "SL";
367                 tx6_mod_suffix = "?";
368         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
369                 cpu_str = "DL";
370                 tx6_mod_suffix = "U";
371         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
372                 cpu_str = "SOLO";
373                 tx6_mod_suffix = "S";
374         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
375                 cpu_str = "Q";
376                 tx6_mod_suffix = "Q";
377         } else if (is_cpu_type(MXC_CPU_MX6QP)) {
378                 cpu_str = "QP";
379                 tx6_mod_suffix = "QP";
380         }
381
382         printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
383                 cpu_str,
384                 (cpurev & 0x000F0) >> 4,
385                 (cpurev & 0x0000F) >> 0,
386                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
387
388         print_temperature();
389         print_reset_cause();
390 #ifdef CONFIG_MX6_TEMPERATURE_HOT
391         check_cpu_temperature(1);
392 #endif
393         tx6_i2c_recover();
394         return 0;
395 }
396
397 /* serial port not initialized at this point */
398 int board_early_init_f(void)
399 {
400         return 0;
401 }
402
403 #ifndef CONFIG_MX6_TEMPERATURE_HOT
404 static bool tx6_temp_check_enabled = true;
405 #else
406 #define tx6_temp_check_enabled  0
407 #endif
408
409 #ifdef CONFIG_TX6_NAND
410 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
411 #else
412 #ifdef CONFIG_MMC_BOOT_SIZE
413 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
414 #else
415 #define TX6_FLASH_SZ    2
416 #endif
417 #endif /* CONFIG_TX6_NAND */
418
419 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
420
421 static char tx6_mem_table[] = {
422         '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
423         '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
424         '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
425         '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
426         '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
427         '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
428         '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
429         '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
430         '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
431         '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
432         '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
433         '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
434 };
435
436 #ifdef CONFIG_RN5T567
437 /* PMIC settings */
438 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
439 #define VDD_CORE_VAL            rn5t_mV_to_regval(1400)         /* DCDC1 */
440 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
441 #define VDD_SOC_VAL             rn5t_mV_to_regval(1400)         /* DCDC2 */
442 #define VDD_SOC_VAL_LP          rn5t_mV_to_regval(1400)
443 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
444 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
445 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3000)         /* DCDC4 */
446 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3000)
447 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
448 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
449 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval2(3300)        /* LDO2 */
450 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval2(3300)
451
452 static struct pmic_regs rn5t567_regs[] = {
453         { RN5T567_NOETIMSET, 0x5, },
454         { RN5T567_DC1DAC, VDD_CORE_VAL, },
455         { RN5T567_DC2DAC, VDD_SOC_VAL, },
456         { RN5T567_DC3DAC, VDD_DDR_VAL, },
457         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
458         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
459         { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
460         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
461         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
462         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
463         { RN5T567_DC2CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
464         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
465         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
466         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
467         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
468         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
469         { RN5T567_LDO2DAC, VDD_IO_EXT_VAL, },
470         { RN5T567_LDOEN1, 0x03, ~0x1f, },
471         { RN5T567_LDOEN2, 0x10, ~0x30, },
472         { RN5T567_LDODIS, 0x1c, ~0x1f, },
473         { RN5T567_INTPOL, 0, },
474         { RN5T567_INTEN, 0x3, },
475         { RN5T567_IREN, 0xf, },
476         { RN5T567_EN_GPIR, 0, },
477 };
478 #endif
479
480 static struct {
481         uchar addr;
482         uchar rev;
483         struct pmic_regs *regs;
484         size_t num_regs;
485 } tx6_mod_revs[] = {
486 #ifdef CONFIG_LTC3676
487         { 0x3c, 1, NULL, 0, },
488 #endif
489 #ifdef CONFIG_RN5T567
490         { 0x33, 3, rn5t567_regs, ARRAY_SIZE(rn5t567_regs), },
491 #endif
492 };
493
494 static inline char tx6_mem_suffix(void)
495 {
496         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
497
498         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
499                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
500
501         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
502                 return '?';
503         if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
504                 return '7';
505         if (mem_idx == 8)
506                 return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
507         return tx6_mem_table[mem_idx];
508 };
509
510 static int tx6_get_mod_rev(unsigned int pmic_id)
511 {
512         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
513                 return tx6_mod_revs[pmic_id].rev;
514
515         return 0;
516 }
517
518 static int tx6_pmic_probe(void)
519 {
520         int i;
521
522         debug("%s@%d: \n", __func__, __LINE__);
523
524         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
525                 u8 i2c_addr = tx6_mod_revs[i].addr;
526                 int ret = i2c_probe(i2c_addr);
527
528                 if (ret == 0) {
529                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
530                         return i;
531                 }
532                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
533         }
534         return -EINVAL;
535 }
536
537 static int tx6_mipi(void)
538 {
539         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
540         struct fuse_bank4_regs *fuse = (void *)ocotp->bank[4].fuse_regs;
541         u32 gp1 = readl(&fuse->gp1);
542
543         debug("Fuse gp1 @ %p = %08x\n", &fuse->gp1, gp1);
544         return gp1 & 1;
545 }
546
547 int board_init(void)
548 {
549         int ret;
550         int pmic_id;
551
552         debug("%s@%d: \n", __func__, __LINE__);
553
554         pmic_id = tx6_pmic_probe();
555         if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
556                 pmic_addr = tx6_mod_revs[pmic_id].addr;
557
558         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
559                 tx6_mod_suffix,
560                 is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
561                 tx6_mipi() ? 2 : is_lvds(), tx6_get_mod_rev(pmic_id),
562                 tx6_mem_suffix());
563
564         get_hab_status();
565
566         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
567         if (ret < 0) {
568                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
569         }
570         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
571
572         /* Address of boot parameters */
573         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
574         gd->bd->bi_arch_number = -1;
575
576         if (ctrlc() || (wrsr & WRSR_TOUT)) {
577                 if (wrsr & WRSR_TOUT)
578                         printf("WDOG RESET detected; Skipping PMIC setup\n");
579                 else
580                         printf("<CTRL-C> detected; safeboot enabled\n");
581 #ifndef CONFIG_MX6_TEMPERATURE_HOT
582                 tx6_temp_check_enabled = false;
583 #endif
584                 return 0;
585         }
586
587         ret = tx6_pmic_init(pmic_addr, tx6_mod_revs[pmic_id].regs,
588                         tx6_mod_revs[pmic_id].num_regs);
589         if (ret) {
590                 printf("Failed to setup PMIC voltages: %d\n", ret);
591                 hang();
592         }
593         return 0;
594 }
595
596 int dram_init(void)
597 {
598         debug("%s@%d: \n", __func__, __LINE__);
599
600         /* dram_init must store complete ramsize in gd->ram_size */
601         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
602                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
603         return 0;
604 }
605
606 void dram_init_banksize(void)
607 {
608         debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
609                 CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
610         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
611         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
612                         PHYS_SDRAM_1_SIZE);
613 #if CONFIG_NR_DRAM_BANKS > 1
614         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
615         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
616                         PHYS_SDRAM_2_SIZE);
617 #endif
618 }
619
620 #ifdef  CONFIG_FSL_ESDHC
621 #define SD_PAD_CTRL             MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
622                                 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
623                                 PAD_CTL_SRE_FAST)
624
625 static const iomux_v3_cfg_t mmc0_pads[] = {
626         MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
627         MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
628         MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
629         MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
630         MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
631         MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
632         /* SD1 CD */
633         MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
634 };
635
636 static const iomux_v3_cfg_t mmc1_pads[] = {
637         MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
638         MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
639         MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
640         MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
641         MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
642         MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
643         /* SD2 CD */
644         MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
645 };
646
647 #ifdef CONFIG_TX6_EMMC
648 static const iomux_v3_cfg_t mmc3_pads[] = {
649         MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
650         MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
651         MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
652         MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
653         MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
654         MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
655         /* eMMC RESET */
656         MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
657 };
658 #endif
659
660 static struct tx6_esdhc_cfg {
661         const iomux_v3_cfg_t *pads;
662         int num_pads;
663         enum mxc_clock clkid;
664         struct fsl_esdhc_cfg cfg;
665         int cd_gpio;
666 } tx6qdl_esdhc_cfg[] = {
667 #ifdef CONFIG_TX6_EMMC
668         {
669                 .pads = mmc3_pads,
670                 .num_pads = ARRAY_SIZE(mmc3_pads),
671                 .clkid = MXC_ESDHC4_CLK,
672                 .cfg = {
673                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
674                         .max_bus_width = 4,
675                 },
676                 .cd_gpio = -EINVAL,
677         },
678 #endif
679         {
680                 .pads = mmc0_pads,
681                 .num_pads = ARRAY_SIZE(mmc0_pads),
682                 .clkid = MXC_ESDHC_CLK,
683                 .cfg = {
684                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
685                         .max_bus_width = 4,
686                 },
687                 .cd_gpio = IMX_GPIO_NR(7, 2),
688         },
689         {
690                 .pads = mmc1_pads,
691                 .num_pads = ARRAY_SIZE(mmc1_pads),
692                 .clkid = MXC_ESDHC2_CLK,
693                 .cfg = {
694                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
695                         .max_bus_width = 4,
696                 },
697                 .cd_gpio = IMX_GPIO_NR(7, 3),
698         },
699 };
700
701 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
702 {
703         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
704 }
705
706 int board_mmc_getcd(struct mmc *mmc)
707 {
708         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
709
710         if (cfg->cd_gpio < 0)
711                 return 1;
712
713         debug("SD card %d is %spresent (GPIO %d)\n",
714                 cfg - tx6qdl_esdhc_cfg,
715                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
716                 cfg->cd_gpio);
717         return !gpio_get_value(cfg->cd_gpio);
718 }
719
720 int board_mmc_init(bd_t *bis)
721 {
722         int i;
723
724         debug("%s@%d: \n", __func__, __LINE__);
725
726         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
727                 struct mmc *mmc;
728                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
729                 int ret;
730
731                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
732                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
733
734                 if (cfg->cd_gpio >= 0) {
735                         ret = gpio_request_one(cfg->cd_gpio,
736                                         GPIOFLAG_INPUT, "MMC CD");
737                         if (ret) {
738                                 printf("Error %d requesting GPIO%d_%d\n",
739                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
740                                 continue;
741                         }
742                 }
743
744                 debug("%s: Initializing MMC slot %d\n", __func__, i);
745                 fsl_esdhc_initialize(bis, &cfg->cfg);
746
747                 mmc = find_mmc_device(i);
748                 if (mmc == NULL)
749                         continue;
750                 if (board_mmc_getcd(mmc))
751                         mmc_init(mmc);
752         }
753         return 0;
754 }
755 #endif /* CONFIG_CMD_MMC */
756
757 #ifdef CONFIG_FEC_MXC
758
759 #ifndef ETH_ALEN
760 #define ETH_ALEN 6
761 #endif
762
763 int board_eth_init(bd_t *bis)
764 {
765         int ret;
766
767         debug("%s@%d: \n", __func__, __LINE__);
768
769         /* delay at least 21ms for the PHY internal POR signal to deassert */
770         udelay(22000);
771
772         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
773                                         ARRAY_SIZE(tx6qdl_fec_pads));
774
775         /* Deassert RESET to the external phy */
776         gpio_set_value(TX6_FEC_RST_GPIO, 1);
777
778         ret = cpu_eth_init(bis);
779         if (ret)
780                 printf("cpu_eth_init() failed: %d\n", ret);
781
782         return ret;
783 }
784
785 static void tx6_init_mac(void)
786 {
787         u8 mac[ETH_ALEN];
788
789         imx_get_mac_from_fuse(0, mac);
790         if (!is_valid_ethaddr(mac)) {
791                 printf("No valid MAC address programmed\n");
792                 return;
793         }
794
795         printf("MAC addr from fuse: %pM\n", mac);
796         eth_setenv_enetaddr("ethaddr", mac);
797 }
798 #else
799 static inline void tx6_init_mac(void)
800 {
801 }
802 #endif /* CONFIG_FEC_MXC */
803
804 enum {
805         LED_STATE_INIT = -1,
806         LED_STATE_OFF,
807         LED_STATE_ON,
808 };
809
810 static inline int calc_blink_rate(void)
811 {
812         if (!tx6_temp_check_enabled)
813                 return CONFIG_SYS_HZ;
814
815         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
816                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
817                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
818 }
819
820 void show_activity(int arg)
821 {
822         static int led_state = LED_STATE_INIT;
823         static int blink_rate;
824         static ulong last;
825
826         if (led_state == LED_STATE_INIT) {
827                 last = get_timer(0);
828                 gpio_set_value(TX6_LED_GPIO, 1);
829                 led_state = LED_STATE_ON;
830                 blink_rate = calc_blink_rate();
831         } else {
832                 if (get_timer(last) > blink_rate) {
833                         blink_rate = calc_blink_rate();
834                         last = get_timer_masked();
835                         if (led_state == LED_STATE_ON) {
836                                 gpio_set_value(TX6_LED_GPIO, 0);
837                         } else {
838                                 gpio_set_value(TX6_LED_GPIO, 1);
839                         }
840                         led_state = 1 - led_state;
841                 }
842         }
843 }
844
845 static const iomux_v3_cfg_t stk5_pads[] = {
846         /* SW controlled LED on STK5 baseboard */
847         MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
848
849         /* I2C bus on DIMM pins 40/41 */
850         MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
851         MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
852
853         /* TSC200x PEN IRQ */
854         MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
855
856         /* EDT-FT5x06 Polytouch panel */
857         MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
858         MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
859         MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
860
861         /* USBH1 */
862         MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
863         MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
864         /* USBOTG */
865         MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
866         MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
867         MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
868 };
869
870 static const struct gpio stk5_gpios[] = {
871         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
872
873         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
874         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
875         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
876         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
877         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
878 };
879
880 #ifdef CONFIG_LCD
881 vidinfo_t panel_info = {
882         /* set to max. size supported by SoC */
883         .vl_col = 1920,
884         .vl_row = 1080,
885
886         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
887 };
888
889 static struct fb_videomode tx6_fb_modes[] = {
890 #ifndef CONFIG_SYS_LVDS_IF
891         {
892                 /* Standard VGA timing */
893                 .name           = "VGA",
894                 .refresh        = 60,
895                 .xres           = 640,
896                 .yres           = 480,
897                 .pixclock       = KHZ2PICOS(25175),
898                 .left_margin    = 48,
899                 .hsync_len      = 96,
900                 .right_margin   = 16,
901                 .upper_margin   = 31,
902                 .vsync_len      = 2,
903                 .lower_margin   = 12,
904                 .sync           = FB_SYNC_CLK_LAT_FALL,
905         },
906         {
907                 /* Emerging ETV570 640 x 480 display. Syncs low active,
908                  * DE high active, 115.2 mm x 86.4 mm display area
909                  * VGA compatible timing
910                  */
911                 .name           = "ETV570",
912                 .refresh        = 60,
913                 .xres           = 640,
914                 .yres           = 480,
915                 .pixclock       = KHZ2PICOS(25175),
916                 .left_margin    = 114,
917                 .hsync_len      = 30,
918                 .right_margin   = 16,
919                 .upper_margin   = 32,
920                 .vsync_len      = 3,
921                 .lower_margin   = 10,
922                 .sync           = FB_SYNC_CLK_LAT_FALL,
923         },
924         {
925                 /* Emerging ET0350G0DH6 320 x 240 display.
926                  * 70.08 mm x 52.56 mm display area.
927                  */
928                 .name           = "ET0350",
929                 .refresh        = 60,
930                 .xres           = 320,
931                 .yres           = 240,
932                 .pixclock       = KHZ2PICOS(6500),
933                 .left_margin    = 68 - 34,
934                 .hsync_len      = 34,
935                 .right_margin   = 20,
936                 .upper_margin   = 18 - 3,
937                 .vsync_len      = 3,
938                 .lower_margin   = 4,
939                 .sync           = FB_SYNC_CLK_LAT_FALL,
940         },
941         {
942                 /* Emerging ET0430G0DH6 480 x 272 display.
943                  * 95.04 mm x 53.856 mm display area.
944                  */
945                 .name           = "ET0430",
946                 .refresh        = 60,
947                 .xres           = 480,
948                 .yres           = 272,
949                 .pixclock       = KHZ2PICOS(9000),
950                 .left_margin    = 2,
951                 .hsync_len      = 41,
952                 .right_margin   = 2,
953                 .upper_margin   = 2,
954                 .vsync_len      = 10,
955                 .lower_margin   = 2,
956         },
957         {
958                 /* Emerging ET0500G0DH6 800 x 480 display.
959                  * 109.6 mm x 66.4 mm display area.
960                  */
961                 .name           = "ET0500",
962                 .refresh        = 60,
963                 .xres           = 800,
964                 .yres           = 480,
965                 .pixclock       = KHZ2PICOS(33260),
966                 .left_margin    = 216 - 128,
967                 .hsync_len      = 128,
968                 .right_margin   = 1056 - 800 - 216,
969                 .upper_margin   = 35 - 2,
970                 .vsync_len      = 2,
971                 .lower_margin   = 525 - 480 - 35,
972                 .sync           = FB_SYNC_CLK_LAT_FALL,
973         },
974         {
975                 /* Emerging ETQ570G0DH6 320 x 240 display.
976                  * 115.2 mm x 86.4 mm display area.
977                  */
978                 .name           = "ETQ570",
979                 .refresh        = 60,
980                 .xres           = 320,
981                 .yres           = 240,
982                 .pixclock       = KHZ2PICOS(6400),
983                 .left_margin    = 38,
984                 .hsync_len      = 30,
985                 .right_margin   = 30,
986                 .upper_margin   = 16, /* 15 according to datasheet */
987                 .vsync_len      = 3, /* TVP -> 1>x>5 */
988                 .lower_margin   = 4, /* 4.5 according to datasheet */
989                 .sync           = FB_SYNC_CLK_LAT_FALL,
990         },
991         {
992                 /* Emerging ET0700G0DH6 800 x 480 display.
993                  * 152.4 mm x 91.44 mm display area.
994                  */
995                 .name           = "ET0700",
996                 .refresh        = 60,
997                 .xres           = 800,
998                 .yres           = 480,
999                 .pixclock       = KHZ2PICOS(33260),
1000                 .left_margin    = 216 - 128,
1001                 .hsync_len      = 128,
1002                 .right_margin   = 1056 - 800 - 216,
1003                 .upper_margin   = 35 - 2,
1004                 .vsync_len      = 2,
1005                 .lower_margin   = 525 - 480 - 35,
1006                 .sync           = FB_SYNC_CLK_LAT_FALL,
1007         },
1008         {
1009                 /* Emerging ET070001DM6 800 x 480 display.
1010                  * 152.4 mm x 91.44 mm display area.
1011                  */
1012                 .name           = "ET070001DM6",
1013                 .refresh        = 60,
1014                 .xres           = 800,
1015                 .yres           = 480,
1016                 .pixclock       = KHZ2PICOS(33260),
1017                 .left_margin    = 216 - 128,
1018                 .hsync_len      = 128,
1019                 .right_margin   = 1056 - 800 - 216,
1020                 .upper_margin   = 35 - 2,
1021                 .vsync_len      = 2,
1022                 .lower_margin   = 525 - 480 - 35,
1023                 .sync           = 0,
1024         },
1025 #else
1026         {
1027                 /* HannStar HSD100PXN1
1028                  * 202.7m mm x 152.06 mm display area.
1029                  */
1030                 .name           = "HSD100PXN1",
1031                 .refresh        = 60,
1032                 .xres           = 1024,
1033                 .yres           = 768,
1034                 .pixclock       = KHZ2PICOS(65000),
1035                 .left_margin    = 0,
1036                 .hsync_len      = 0,
1037                 .right_margin   = 320,
1038                 .upper_margin   = 0,
1039                 .vsync_len      = 0,
1040                 .lower_margin   = 38,
1041                 .sync           = FB_SYNC_CLK_LAT_FALL,
1042         },
1043 #endif
1044         {
1045                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1046                 .refresh        = 60,
1047                 .left_margin    = 48,
1048                 .hsync_len      = 96,
1049                 .right_margin   = 16,
1050                 .upper_margin   = 31,
1051                 .vsync_len      = 2,
1052                 .lower_margin   = 12,
1053                 .sync           = FB_SYNC_CLK_LAT_FALL,
1054         },
1055 };
1056
1057 static int lcd_enabled = 1;
1058 static int lcd_bl_polarity;
1059
1060 static int lcd_backlight_polarity(void)
1061 {
1062         return lcd_bl_polarity;
1063 }
1064
1065 void lcd_enable(void)
1066 {
1067         /* HACK ALERT:
1068          * global variable from common/lcd.c
1069          * Set to 0 here to prevent messages from going to LCD
1070          * rather than serial console
1071          */
1072         lcd_is_enabled = 0;
1073
1074         if (lcd_enabled) {
1075                 karo_load_splashimage(1);
1076
1077                 debug("Switching LCD on\n");
1078                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1079                 udelay(100);
1080                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1081                 udelay(300000);
1082                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1083                         lcd_backlight_polarity());
1084         }
1085 }
1086
1087 void lcd_disable(void)
1088 {
1089         if (lcd_enabled) {
1090                 printf("Disabling LCD\n");
1091                 ipuv3_fb_shutdown();
1092         }
1093 }
1094
1095 void lcd_panel_disable(void)
1096 {
1097         if (lcd_enabled) {
1098                 debug("Switching LCD off\n");
1099                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1100                         !lcd_backlight_polarity());
1101                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1102                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1103         }
1104 }
1105
1106 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1107         /* LCD RESET */
1108         MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
1109         /* LCD POWER_ENABLE */
1110         MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
1111         /* LCD Backlight (PWM) */
1112         MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
1113
1114 #ifndef CONFIG_SYS_LVDS_IF
1115         /* Display */
1116         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
1117         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
1118         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
1119         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
1120         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
1121         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
1122         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
1123         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
1124         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
1125         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
1126         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
1127         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
1128         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
1129         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
1130         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
1131         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
1132         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
1133         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
1134         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
1135         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
1136         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
1137         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
1138         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
1139         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
1140         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
1141         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
1142         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
1143         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
1144 #endif
1145 };
1146
1147 static const struct gpio stk5_lcd_gpios[] = {
1148         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1149         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1150         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1151 };
1152
1153 void lcd_ctrl_init(void *lcdbase)
1154 {
1155         int color_depth = 24;
1156         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1157         const char *vm;
1158         unsigned long val;
1159         int refresh = 60;
1160         struct fb_videomode *p = &tx6_fb_modes[0];
1161         struct fb_videomode fb_mode;
1162         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1163         int pix_fmt;
1164         int lcd_bus_width;
1165         unsigned long di_clk_rate = 65000000;
1166
1167         if (!lcd_enabled) {
1168                 debug("LCD disabled\n");
1169                 goto disable;
1170         }
1171
1172         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1173                 debug("Disabling LCD\n");
1174                 lcd_enabled = 0;
1175                 setenv("splashimage", NULL);
1176                 goto disable;
1177         }
1178
1179         karo_fdt_move_fdt();
1180         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1181
1182         if (video_mode == NULL) {
1183                 debug("Disabling LCD\n");
1184                 lcd_enabled = 0;
1185                 goto disable;
1186         }
1187         vm = video_mode;
1188         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1189                 p = &fb_mode;
1190                 debug("Using video mode from FDT\n");
1191                 vm += strlen(vm);
1192                 if (fb_mode.xres > panel_info.vl_col ||
1193                         fb_mode.yres > panel_info.vl_row) {
1194                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1195                                 fb_mode.xres, fb_mode.yres,
1196                                 panel_info.vl_col, panel_info.vl_row);
1197                         lcd_enabled = 0;
1198                         goto disable;
1199                 }
1200         }
1201         if (p->name != NULL)
1202                 debug("Trying compiled-in video modes\n");
1203         while (p->name != NULL) {
1204                 if (strcmp(p->name, vm) == 0) {
1205                         debug("Using video mode: '%s'\n", p->name);
1206                         vm += strlen(vm);
1207                         break;
1208                 }
1209                 p++;
1210         }
1211         if (*vm != '\0')
1212                 debug("Trying to decode video_mode: '%s'\n", vm);
1213         while (*vm != '\0') {
1214                 if (*vm >= '0' && *vm <= '9') {
1215                         char *end;
1216
1217                         val = simple_strtoul(vm, &end, 0);
1218                         if (end > vm) {
1219                                 if (!xres_set) {
1220                                         if (val > panel_info.vl_col)
1221                                                 val = panel_info.vl_col;
1222                                         p->xres = val;
1223                                         panel_info.vl_col = val;
1224                                         xres_set = 1;
1225                                 } else if (!yres_set) {
1226                                         if (val > panel_info.vl_row)
1227                                                 val = panel_info.vl_row;
1228                                         p->yres = val;
1229                                         panel_info.vl_row = val;
1230                                         yres_set = 1;
1231                                 } else if (!bpp_set) {
1232                                         switch (val) {
1233                                         case 32:
1234                                         case 24:
1235                                                 if (is_lvds())
1236                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1237                                                 /* fallthru */
1238                                         case 16:
1239                                         case 8:
1240                                                 color_depth = val;
1241                                                 break;
1242
1243                                         case 18:
1244                                                 if (is_lvds()) {
1245                                                         color_depth = val;
1246                                                         break;
1247                                                 }
1248                                                 /* fallthru */
1249                                         default:
1250                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1251                                                         end - vm, vm, color_depth);
1252                                         }
1253                                         bpp_set = 1;
1254                                 } else if (!refresh_set) {
1255                                         refresh = val;
1256                                         refresh_set = 1;
1257                                 }
1258                         }
1259                         vm = end;
1260                 }
1261                 switch (*vm) {
1262                 case '@':
1263                         bpp_set = 1;
1264                         /* fallthru */
1265                 case '-':
1266                         yres_set = 1;
1267                         /* fallthru */
1268                 case 'x':
1269                         xres_set = 1;
1270                         /* fallthru */
1271                 case 'M':
1272                 case 'R':
1273                         vm++;
1274                         break;
1275
1276                 default:
1277                         if (*vm != '\0')
1278                                 vm++;
1279                 }
1280         }
1281         if (p->xres == 0 || p->yres == 0) {
1282                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1283                 lcd_enabled = 0;
1284                 printf("Supported video modes are:");
1285                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1286                         printf(" %s", p->name);
1287                 }
1288                 printf("\n");
1289                 goto disable;
1290         }
1291         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1292                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1293                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1294                 lcd_enabled = 0;
1295                 goto disable;
1296         }
1297         panel_info.vl_col = p->xres;
1298         panel_info.vl_row = p->yres;
1299
1300         switch (color_depth) {
1301         case 8:
1302                 panel_info.vl_bpix = LCD_COLOR8;
1303                 break;
1304         case 16:
1305                 panel_info.vl_bpix = LCD_COLOR16;
1306                 break;
1307         default:
1308                 panel_info.vl_bpix = LCD_COLOR32;
1309         }
1310
1311         p->pixclock = KHZ2PICOS(refresh *
1312                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1313                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1314                                 1000);
1315         debug("Pixel clock set to %lu.%03lu MHz\n",
1316                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1317
1318         if (p != &fb_mode) {
1319                 int ret;
1320
1321                 debug("Creating new display-timing node from '%s'\n",
1322                         video_mode);
1323                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1324                 if (ret)
1325                         printf("Failed to create new display-timing node from '%s': %d\n",
1326                                 video_mode, ret);
1327         }
1328
1329         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1330         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1331                                         ARRAY_SIZE(stk5_lcd_pads));
1332
1333         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1334         switch (lcd_bus_width) {
1335         case 24:
1336                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1337                 break;
1338
1339         case 18:
1340                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1341                 break;
1342
1343         case 16:
1344                 if (!is_lvds()) {
1345                         pix_fmt = IPU_PIX_FMT_RGB565;
1346                         break;
1347                 }
1348                 /* fallthru */
1349         default:
1350                 lcd_enabled = 0;
1351                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1352                         lcd_bus_width);
1353                 goto disable;
1354         }
1355         if (is_lvds()) {
1356                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1357                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1358                 uint32_t gpr2;
1359                 uint32_t gpr3;
1360
1361                 if (lvds_chan_mask == 0) {
1362                         printf("No LVDS channel active\n");
1363                         lcd_enabled = 0;
1364                         goto disable;
1365                 }
1366
1367                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1368                 if (lcd_bus_width == 24)
1369                         gpr2 |= (1 << 5) | (1 << 7);
1370                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1371                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1372                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1373                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1374
1375                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1376                 gpr3 &= ~((3 << 8) | (3 << 6));
1377                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1378         }
1379         if (karo_load_splashimage(0) == 0) {
1380                 int ret;
1381
1382                 debug("Initializing LCD controller\n");
1383                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1384                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1385                                 di_clk_rate, -1);
1386                 if (ret) {
1387                         printf("Failed to initialize FB driver: %d\n", ret);
1388                         lcd_enabled = 0;
1389                 }
1390         } else {
1391                 debug("Skipping initialization of LCD controller\n");
1392         }
1393         return;
1394
1395 disable:
1396         lcd_enabled = 0;
1397         panel_info.vl_col = 0;
1398         panel_info.vl_row = 0;
1399
1400 }
1401 #else
1402 #define lcd_enabled 0
1403 #endif /* CONFIG_LCD */
1404
1405 static void stk5_board_init(void)
1406 {
1407         int ret;
1408
1409         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1410         if (ret < 0) {
1411                 printf("Failed to request stk5_gpios: %d\n", ret);
1412                 return;
1413         }
1414         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1415 }
1416
1417 static void stk5v3_board_init(void)
1418 {
1419         stk5_board_init();
1420 }
1421
1422 static void stk5v5_board_init(void)
1423 {
1424         int ret;
1425
1426         stk5_board_init();
1427
1428         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1429                         "Flexcan Transceiver");
1430         if (ret) {
1431                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1432                 return;
1433         }
1434
1435         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
1436                         TX6_GPIO_PAD_CTRL);
1437 }
1438
1439 static void tx6qdl_set_cpu_clock(void)
1440 {
1441         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1442
1443         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1444                 return;
1445
1446         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1447                 printf("%s detected; skipping cpu clock change\n",
1448                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1449                 return;
1450         }
1451         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1452                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1453                 printf("CPU clock set to %lu.%03lu MHz\n",
1454                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1455         } else {
1456                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1457         }
1458 }
1459
1460 int board_late_init(void)
1461 {
1462         const char *baseboard;
1463
1464         debug("%s@%d: \n", __func__, __LINE__);
1465
1466         env_cleanup();
1467
1468         if (tx6_temp_check_enabled)
1469                 check_cpu_temperature(1);
1470
1471         tx6qdl_set_cpu_clock();
1472
1473         if (had_ctrlc())
1474                 setenv_ulong("safeboot", 1);
1475         else if (wrsr & WRSR_TOUT)
1476                 setenv_ulong("wdreset", 1);
1477         else
1478                 karo_fdt_move_fdt();
1479
1480         baseboard = getenv("baseboard");
1481         if (!baseboard)
1482                 goto exit;
1483
1484         printf("Baseboard: %s\n", baseboard);
1485
1486         if (strncmp(baseboard, "stk5", 4) == 0) {
1487                 if ((strlen(baseboard) == 4) ||
1488                         strcmp(baseboard, "stk5-v3") == 0) {
1489                         stk5v3_board_init();
1490                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1491                         const char *otg_mode = getenv("otg_mode");
1492
1493                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1494                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1495                                         otg_mode, baseboard);
1496                                 setenv("otg_mode", "none");
1497                         }
1498                         stk5v5_board_init();
1499                 } else {
1500                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1501                                 baseboard + 4);
1502                 }
1503         } else {
1504                 printf("WARNING: Unsupported baseboard: '%s'\n",
1505                         baseboard);
1506                 if (!had_ctrlc())
1507                         return -EINVAL;
1508         }
1509
1510 exit:
1511         tx6_init_mac();
1512
1513         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1514         clear_ctrlc();
1515         return 0;
1516 }
1517
1518 #ifdef CONFIG_SERIAL_TAG
1519 void get_board_serial(struct tag_serialnr *serialnr)
1520 {
1521         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1522         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1523
1524         serialnr->low = readl(&fuse->cfg0);
1525         serialnr->high = readl(&fuse->cfg1);
1526 }
1527 #endif
1528
1529 #if defined(CONFIG_OF_BOARD_SETUP)
1530 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1531 #include <jffs2/jffs2.h>
1532 #include <mtd_node.h>
1533 static struct node_info nodes[] = {
1534         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1535 };
1536 #else
1537 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1538 #endif
1539
1540 static const char *tx6_touchpanels[] = {
1541         "ti,tsc2007",
1542         "edt,edt-ft5x06",
1543         "eeti,egalax_ts",
1544 };
1545
1546 int ft_board_setup(void *blob, bd_t *bd)
1547 {
1548         const char *baseboard = getenv("baseboard");
1549         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1550         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1551         int ret;
1552
1553         ret = fdt_increase_size(blob, 4096);
1554         if (ret) {
1555                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1556                 return ret;
1557         }
1558         if (stk5_v5)
1559                 karo_fdt_enable_node(blob, "stk5led", 0);
1560
1561         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1562
1563         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1564                                 ARRAY_SIZE(tx6_touchpanels));
1565         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1566         karo_fdt_fixup_flexcan(blob, stk5_v5);
1567
1568         karo_fdt_update_fb_mode(blob, video_mode);
1569
1570         return 0;
1571 }
1572 #endif /* CONFIG_OF_BOARD_SETUP */