board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <errno.h>
  25 #include <libfdt.h>
  26 #include <fdt_support.h>
  27 #include <lcd.h>
  28 #include <netdev.h>
  29 #include <mmc.h>
  30 #include <fsl_esdhc.h>
  31 #include <video_fb.h>
  32 #include <ipu.h>
  33 #include <mxcfb.h>
  34 #include <i2c.h>
  35 #include <linux/fb.h>
  36 #include <asm/io.h>
  37 #include <asm/gpio.h>
  38 #include <asm/arch/mx6-pins.h>
  39 #include <asm/arch/clock.h>
  40 #include <asm/arch/imx-regs.h>
  41 #include <asm/arch/crm_regs.h>
  42 #include <asm/arch/sys_proto.h>
  43
  44 #include "../common/karo.h"
  45
  46 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  47 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  48 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(2, 4)
  49 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  50
  51 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  52 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  53 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  54
  55 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  56
  57 #define TEMPERATURE_MIN                 -40
  58 #define TEMPERATURE_HOT                 80
  59 #define TEMPERATURE_MAX                 125
  60
  61 DECLARE_GLOBAL_DATA_PTR;
  62
  63 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  64
  65 static const iomux_v3_cfg_t tx6qdl_pads[] = {
  66         /* NAND flash pads */
  67         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
  68         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
  69         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
  70         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
  71         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
  72         MX6_PAD_SD4_CMD__RAWNAND_RDN,
  73         MX6_PAD_SD4_CLK__RAWNAND_WRN,
  74         MX6_PAD_NANDF_D0__RAWNAND_D0,
  75         MX6_PAD_NANDF_D1__RAWNAND_D1,
  76         MX6_PAD_NANDF_D2__RAWNAND_D2,
  77         MX6_PAD_NANDF_D3__RAWNAND_D3,
  78         MX6_PAD_NANDF_D4__RAWNAND_D4,
  79         MX6_PAD_NANDF_D5__RAWNAND_D5,
  80         MX6_PAD_NANDF_D6__RAWNAND_D6,
  81         MX6_PAD_NANDF_D7__RAWNAND_D7,
  82
  83         /* RESET_OUT */
  84         MX6_PAD_GPIO_17__GPIO_7_12,
  85
  86         /* UART pads */
  87 #if CONFIG_MXC_UART_BASE == UART1_BASE
  88         MX6_PAD_SD3_DAT7__UART1_TXD,
  89         MX6_PAD_SD3_DAT6__UART1_RXD,
  90         MX6_PAD_SD3_DAT1__UART1_RTS,
  91         MX6_PAD_SD3_DAT0__UART1_CTS,
  92 #endif
  93 #if CONFIG_MXC_UART_BASE == UART2_BASE
  94         MX6_PAD_SD4_DAT4__UART2_RXD,
  95         MX6_PAD_SD4_DAT7__UART2_TXD,
  96         MX6_PAD_SD4_DAT5__UART2_RTS,
  97         MX6_PAD_SD4_DAT6__UART2_CTS,
  98 #endif
  99 #if CONFIG_MXC_UART_BASE == UART3_BASE
 100         MX6_PAD_EIM_D24__UART3_TXD,
 101         MX6_PAD_EIM_D25__UART3_RXD,
 102         MX6_PAD_SD3_RST__UART3_RTS,
 103         MX6_PAD_SD3_DAT3__UART3_CTS,
 104 #endif
 105         /* internal I2C */
 106         MX6_PAD_EIM_D28__I2C1_SDA,
 107         MX6_PAD_EIM_D21__I2C1_SCL,
 108
 109         /* FEC PHY GPIO functions */
 110         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
 111         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
 112         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
 113 };
 114
 115 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
 116         /* FEC functions */
 117         MX6_PAD_ENET_MDC__ENET_MDC,
 118         MX6_PAD_ENET_MDIO__ENET_MDIO,
 119         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
 120         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 121         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 122         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
 123         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
 124         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 125         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
 126         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
 127 };
 128
 129 static const struct gpio tx6qdl_gpios[] = {
 130         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 131         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 132         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 133         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 134 };
 135
 136 /*
 137  * Functions
 138  */
 139 /* placed in section '.data' to prevent overwriting relocation info
 140  * overlayed with bss
 141  */
 142 static u32 wrsr __attribute__((section(".data")));
 143
 144 #define WRSR_POR                        (1 << 4)
 145 #define WRSR_TOUT                       (1 << 1)
 146 #define WRSR_SFTW                       (1 << 0)
 147
 148 static void print_reset_cause(void)
 149 {
 150         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 151         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 152         u32 srsr;
 153         char *dlm = "";
 154
 155         printf("Reset cause: ");
 156
 157         srsr = readl(&src_regs->srsr);
 158         wrsr = readw(wdt_base + 4);
 159
 160         if (wrsr & WRSR_POR) {
 161                 printf("%sPOR", dlm);
 162                 dlm = " | ";
 163         }
 164         if (srsr & 0x00004) {
 165                 printf("%sCSU", dlm);
 166                 dlm = " | ";
 167         }
 168         if (srsr & 0x00008) {
 169                 printf("%sIPP USER", dlm);
 170                 dlm = " | ";
 171         }
 172         if (srsr & 0x00010) {
 173                 if (wrsr & WRSR_SFTW) {
 174                         printf("%sSOFT", dlm);
 175                         dlm = " | ";
 176                 }
 177                 if (wrsr & WRSR_TOUT) {
 178                         printf("%sWDOG", dlm);
 179                         dlm = " | ";
 180                 }
 181         }
 182         if (srsr & 0x00020) {
 183                 printf("%sJTAG HIGH-Z", dlm);
 184                 dlm = " | ";
 185         }
 186         if (srsr & 0x00040) {
 187                 printf("%sJTAG SW", dlm);
 188                 dlm = " | ";
 189         }
 190         if (srsr & 0x10000) {
 191                 printf("%sWARM BOOT", dlm);
 192                 dlm = " | ";
 193         }
 194         if (dlm[0] == '\0')
 195                 printf("unknown");
 196
 197         printf("\n");
 198 }
 199
 200 int read_cpu_temperature(void);
 201 int check_cpu_temperature(int boot);
 202
 203 static void tx6qdl_print_cpuinfo(void)
 204 {
 205         u32 cpurev = get_cpu_rev();
 206         char *cpu_str = "?";
 207
 208         switch ((cpurev >> 12) & 0xff) {
 209         case MXC_CPU_MX6SL:
 210                 cpu_str = "SL";
 211                 break;
 212         case MXC_CPU_MX6DL:
 213                 cpu_str = "DL";
 214                 break;
 215         case MXC_CPU_MX6SOLO:
 216                 cpu_str = "SOLO";
 217                 break;
 218         case MXC_CPU_MX6Q:
 219                 cpu_str = "Q";
 220                 break;
 221         }
 222
 223         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 224                 cpu_str,
 225                 (cpurev & 0x000F0) >> 4,
 226                 (cpurev & 0x0000F) >> 0,
 227                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 228
 229         print_reset_cause();
 230         check_cpu_temperature(1);
 231 }
 232
 233 #define LTC3676_DVB2A           0x0C
 234 #define LTC3676_DVB2B           0x0D
 235 #define LTC3676_DVB4A           0x10
 236 #define LTC3676_DVB4B           0x11
 237
 238 #define VDD_SOC_mV              (1375 + 50)
 239 #define VDD_CORE_mV             (1375 + 50)
 240
 241 #define mV_to_regval(mV)        (((mV) * 360 / 330 - 825 + 1) / 25)
 242 #define regval_to_mV(v)         (((v) * 25 + 825) * 330 / 360)
 243
 244 static int setup_pmic_voltages(void)
 245 {
 246         int ret;
 247         unsigned char value;
 248
 249         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 250
 251         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 252         if (ret != 0) {
 253                 printf("Failed to initialize I2C\n");
 254                 return ret;
 255         }
 256
 257         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 258         if (ret) {
 259                 printf("%s: i2c_read error: %d\n", __func__, ret);
 260                 return ret;
 261         }
 262
 263         /* VDDCORE/VDDSOC default 1.375V is not enough, considering
 264            pfuze tolerance and IR drop and ripple, need increase
 265            to 1.425V for SabreSD */
 266
 267         value = 0x39; /* VB default value & PGOOD not forced when slewing */
 268         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
 269         if (ret) {
 270                 printf("%s: failed to write PMIC DVB2B register: %d\n",
 271                         __func__, ret);
 272                 return ret;
 273         }
 274         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
 275         if (ret) {
 276                 printf("%s: failed to write PMIC DVB4B register: %d\n",
 277                         __func__, ret);
 278                 return ret;
 279         }
 280
 281         value = mV_to_regval(VDD_SOC_mV);
 282         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
 283         if (ret) {
 284                 printf("%s: failed to write PMIC DVB2A register: %d\n",
 285                         __func__, ret);
 286                 return ret;
 287         }
 288         printf("VDDSOC  set to %dmV\n", regval_to_mV(value));
 289
 290         value = mV_to_regval(VDD_CORE_mV);
 291         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
 292         if (ret) {
 293                 printf("%s: failed to write PMIC DVB4A register: %d\n",
 294                         __func__, ret);
 295                 return ret;
 296         }
 297         printf("VDDCORE set to %dmV\n", regval_to_mV(value));
 298         return 0;
 299 }
 300
 301 int board_early_init_f(void)
 302 {
 303         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 304         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 305
 306         return 0;
 307 }
 308
 309 int board_init(void)
 310 {
 311         int ret;
 312
 313         /* Address of boot parameters */
 314         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 315 #ifdef CONFIG_OF_LIBFDT
 316         gd->bd->bi_arch_number = -1;
 317 #else
 318         gd->bd->bi_arch_number = 4429;
 319 #endif
 320         ret = setup_pmic_voltages();
 321         if (ret) {
 322                 printf("Failed to setup PMIC voltages\n");
 323                 hang();
 324         }
 325         return 0;
 326 }
 327
 328 int dram_init(void)
 329 {
 330         /* dram_init must store complete ramsize in gd->ram_size */
 331         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 332                                 PHYS_SDRAM_1_SIZE);
 333         return 0;
 334 }
 335
 336 void dram_init_banksize(void)
 337 {
 338         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 339         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 340                         PHYS_SDRAM_1_SIZE);
 341 #if CONFIG_NR_DRAM_BANKS > 1
 342         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 343         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 344                         PHYS_SDRAM_2_SIZE);
 345 #endif
 346 }
 347
 348 #ifdef  CONFIG_CMD_MMC
 349 static const iomux_v3_cfg_t mmc0_pads[] = {
 350         MX6_PAD_SD1_CMD__USDHC1_CMD,
 351         MX6_PAD_SD1_CLK__USDHC1_CLK,
 352         MX6_PAD_SD1_DAT0__USDHC1_DAT0,
 353         MX6_PAD_SD1_DAT1__USDHC1_DAT1,
 354         MX6_PAD_SD1_DAT2__USDHC1_DAT2,
 355         MX6_PAD_SD1_DAT3__USDHC1_DAT3,
 356         /* SD1 CD */
 357         MX6_PAD_SD3_CMD__GPIO_7_2,
 358 };
 359
 360 static const iomux_v3_cfg_t mmc1_pads[] = {
 361         MX6_PAD_SD2_CMD__USDHC2_CMD,
 362         MX6_PAD_SD2_CLK__USDHC2_CLK,
 363         MX6_PAD_SD2_DAT0__USDHC2_DAT0,
 364         MX6_PAD_SD2_DAT1__USDHC2_DAT1,
 365         MX6_PAD_SD2_DAT2__USDHC2_DAT2,
 366         MX6_PAD_SD2_DAT3__USDHC2_DAT3,
 367         /* SD2 CD */
 368         MX6_PAD_SD3_CLK__GPIO_7_3,
 369 };
 370
 371 static struct tx6_esdhc_cfg {
 372         const iomux_v3_cfg_t *pads;
 373         int num_pads;
 374         enum mxc_clock clkid;
 375         struct fsl_esdhc_cfg cfg;
 376         int cd_gpio;
 377 } tx6qdl_esdhc_cfg[] = {
 378         {
 379                 .pads = mmc0_pads,
 380                 .num_pads = ARRAY_SIZE(mmc0_pads),
 381                 .clkid = MXC_ESDHC_CLK,
 382                 .cfg = {
 383                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 384                         .max_bus_width = 4,
 385                 },
 386                 .cd_gpio = IMX_GPIO_NR(7, 2),
 387         },
 388         {
 389                 .pads = mmc1_pads,
 390                 .num_pads = ARRAY_SIZE(mmc1_pads),
 391                 .clkid = MXC_ESDHC2_CLK,
 392                 .cfg = {
 393                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 394                         .max_bus_width = 4,
 395                 },
 396                 .cd_gpio = IMX_GPIO_NR(7, 3),
 397         },
 398 };
 399
 400 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 401 {
 402         void *p = cfg;
 403
 404         return p - offsetof(struct tx6_esdhc_cfg, cfg);
 405 }
 406
 407 int board_mmc_getcd(struct mmc *mmc)
 408 {
 409         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 410
 411         if (cfg->cd_gpio < 0)
 412                 return cfg->cd_gpio;
 413
 414         debug("SD card %d is %spresent\n",
 415                 cfg - tx6qdl_esdhc_cfg,
 416                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 417         return !gpio_get_value(cfg->cd_gpio);
 418 }
 419
 420 int board_mmc_init(bd_t *bis)
 421 {
 422         int i;
 423
 424         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 425                 struct mmc *mmc;
 426                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 427                 int ret;
 428
 429                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 430                         break;
 431
 432                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 433                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 434
 435                 ret = gpio_request_one(cfg->cd_gpio,
 436                                 GPIOF_INPUT, "MMC CD");
 437                 if (ret) {
 438                         printf("Error %d requesting GPIO%d_%d\n",
 439                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 440                         continue;
 441                 }
 442
 443                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 444                 fsl_esdhc_initialize(bis, &cfg->cfg);
 445
 446                 mmc = find_mmc_device(i);
 447                 if (mmc == NULL)
 448                         continue;
 449                 if (board_mmc_getcd(mmc) > 0)
 450                         mmc_init(mmc);
 451         }
 452         return 0;
 453 }
 454 #endif /* CONFIG_CMD_MMC */
 455
 456 #ifdef CONFIG_FEC_MXC
 457
 458 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 459                         PAD_CTL_SRE_FAST)
 460 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 461 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 462
 463 #ifndef ETH_ALEN
 464 #define ETH_ALEN 6
 465 #endif
 466
 467 int board_eth_init(bd_t *bis)
 468 {
 469         int ret;
 470
 471         /* delay at least 21ms for the PHY internal POR signal to deassert */
 472         udelay(22000);
 473
 474         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
 475
 476         /* Deassert RESET to the external phy */
 477         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 478
 479         ret = cpu_eth_init(bis);
 480         if (ret)
 481                 printf("cpu_eth_init() failed: %d\n", ret);
 482
 483         return ret;
 484 }
 485 #endif /* CONFIG_FEC_MXC */
 486
 487 enum {
 488         LED_STATE_INIT = -1,
 489         LED_STATE_OFF,
 490         LED_STATE_ON,
 491 };
 492
 493 static inline int calc_blink_rate(int tmp)
 494 {
 495         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 496                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 497                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 498 }
 499
 500 void show_activity(int arg)
 501 {
 502         static int led_state = LED_STATE_INIT;
 503         static int blink_rate;
 504         static ulong last;
 505
 506         if (led_state == LED_STATE_INIT) {
 507                 last = get_timer(0);
 508                 gpio_set_value(TX6_LED_GPIO, 1);
 509                 led_state = LED_STATE_ON;
 510                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
 511         } else {
 512                 if (get_timer(last) > blink_rate) {
 513                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
 514                         last = get_timer_masked();
 515                         if (led_state == LED_STATE_ON) {
 516                                 gpio_set_value(TX6_LED_GPIO, 0);
 517                         } else {
 518                                 gpio_set_value(TX6_LED_GPIO, 1);
 519                         }
 520                         led_state = 1 - led_state;
 521                 }
 522         }
 523 }
 524
 525 static const iomux_v3_cfg_t stk5_pads[] = {
 526         /* SW controlled LED on STK5 baseboard */
 527         MX6_PAD_EIM_A18__GPIO_2_20,
 528
 529         /* LCD data pins */
 530         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 531         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 532         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 533         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 534         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 535         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 536         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 537         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 538         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 539         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 540         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 541         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 542         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 543         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 544         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 545         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 546         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 547         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 548         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 549         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 550         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 551         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 552         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 553         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 554         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
 555         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
 556         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 557         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 558
 559         /* I2C bus on DIMM pins 40/41 */
 560         MX6_PAD_GPIO_6__I2C3_SDA,
 561         MX6_PAD_GPIO_3__I2C3_SCL,
 562
 563         /* TSC200x PEN IRQ */
 564         MX6_PAD_EIM_D26__GPIO_3_26,
 565
 566         /* EDT-FT5x06 Polytouch panel */
 567         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
 568         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
 569         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
 570
 571         /* USBH1 */
 572         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
 573         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
 574         /* USBOTG */
 575         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
 576         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
 577         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
 578 };
 579
 580 static const struct gpio stk5_gpios[] = {
 581         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 582
 583         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
 584         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 585         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 586         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 587         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 588 };
 589
 590 #ifdef CONFIG_LCD
 591 vidinfo_t panel_info = {
 592         /* set to max. size supported by SoC */
 593         .vl_col = 1920,
 594         .vl_row = 1080,
 595
 596         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 597 };
 598
 599 static struct fb_videomode tx6_fb_modes[] = {
 600         {
 601                 /* Standard VGA timing */
 602                 .name           = "VGA",
 603                 .refresh        = 60,
 604                 .xres           = 640,
 605                 .yres           = 480,
 606                 .pixclock       = KHZ2PICOS(25175),
 607                 .left_margin    = 48,
 608                 .hsync_len      = 96,
 609                 .right_margin   = 16,
 610                 .upper_margin   = 31,
 611                 .vsync_len      = 2,
 612                 .lower_margin   = 12,
 613                 .sync           = FB_SYNC_CLK_LAT_FALL,
 614         },
 615         {
 616                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 617                  * DE high active, 115.2 mm x 86.4 mm display area
 618                  * VGA compatible timing
 619                  */
 620                 .name           = "ETV570",
 621                 .refresh        = 60,
 622                 .xres           = 640,
 623                 .yres           = 480,
 624                 .pixclock       = KHZ2PICOS(25175),
 625                 .left_margin    = 114,
 626                 .hsync_len      = 30,
 627                 .right_margin   = 16,
 628                 .upper_margin   = 32,
 629                 .vsync_len      = 3,
 630                 .lower_margin   = 10,
 631                 .sync           = FB_SYNC_CLK_LAT_FALL,
 632         },
 633         {
 634                 /* Emerging ET0350G0DH6 320 x 240 display.
 635                  * 70.08 mm x 52.56 mm display area.
 636                  */
 637                 .name           = "ET0350",
 638                 .refresh        = 60,
 639                 .xres           = 320,
 640                 .yres           = 240,
 641                 .pixclock       = KHZ2PICOS(6500),
 642                 .left_margin    = 68 - 34,
 643                 .hsync_len      = 34,
 644                 .right_margin   = 20,
 645                 .upper_margin   = 18 - 3,
 646                 .vsync_len      = 3,
 647                 .lower_margin   = 4,
 648                 .sync           = FB_SYNC_CLK_LAT_FALL,
 649         },
 650         {
 651                 /* Emerging ET0430G0DH6 480 x 272 display.
 652                  * 95.04 mm x 53.856 mm display area.
 653                  */
 654                 .name           = "ET0430",
 655                 .refresh        = 60,
 656                 .xres           = 480,
 657                 .yres           = 272,
 658                 .pixclock       = KHZ2PICOS(9000),
 659                 .left_margin    = 2,
 660                 .hsync_len      = 41,
 661                 .right_margin   = 2,
 662                 .upper_margin   = 2,
 663                 .vsync_len      = 10,
 664                 .lower_margin   = 2,
 665                 .sync           = FB_SYNC_CLK_LAT_FALL,
 666         },
 667         {
 668                 /* Emerging ET0500G0DH6 800 x 480 display.
 669                  * 109.6 mm x 66.4 mm display area.
 670                  */
 671                 .name           = "ET0500",
 672                 .refresh        = 60,
 673                 .xres           = 800,
 674                 .yres           = 480,
 675                 .pixclock       = KHZ2PICOS(33260),
 676                 .left_margin    = 216 - 128,
 677                 .hsync_len      = 128,
 678                 .right_margin   = 1056 - 800 - 216,
 679                 .upper_margin   = 35 - 2,
 680                 .vsync_len      = 2,
 681                 .lower_margin   = 525 - 480 - 35,
 682                 .sync           = FB_SYNC_CLK_LAT_FALL,
 683         },
 684         {
 685                 /* Emerging ETQ570G0DH6 320 x 240 display.
 686                  * 115.2 mm x 86.4 mm display area.
 687                  */
 688                 .name           = "ETQ570",
 689                 .refresh        = 60,
 690                 .xres           = 320,
 691                 .yres           = 240,
 692                 .pixclock       = KHZ2PICOS(6400),
 693                 .left_margin    = 38,
 694                 .hsync_len      = 30,
 695                 .right_margin   = 30,
 696                 .upper_margin   = 16, /* 15 according to datasheet */
 697                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 698                 .lower_margin   = 4, /* 4.5 according to datasheet */
 699                 .sync           = FB_SYNC_CLK_LAT_FALL,
 700         },
 701         {
 702                 /* Emerging ET0700G0DH6 800 x 480 display.
 703                  * 152.4 mm x 91.44 mm display area.
 704                  */
 705                 .name           = "ET0700",
 706                 .refresh        = 60,
 707                 .xres           = 800,
 708                 .yres           = 480,
 709                 .pixclock       = KHZ2PICOS(33260),
 710                 .left_margin    = 216 - 128,
 711                 .hsync_len      = 128,
 712                 .right_margin   = 1056 - 800 - 216,
 713                 .upper_margin   = 35 - 2,
 714                 .vsync_len      = 2,
 715                 .lower_margin   = 525 - 480 - 35,
 716                 .sync           = FB_SYNC_CLK_LAT_FALL,
 717         },
 718         {
 719                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 720                 .refresh        = 60,
 721                 .left_margin    = 48,
 722                 .hsync_len      = 96,
 723                 .right_margin   = 16,
 724                 .upper_margin   = 31,
 725                 .vsync_len      = 2,
 726                 .lower_margin   = 12,
 727                 .sync           = FB_SYNC_CLK_LAT_FALL,
 728         },
 729 };
 730
 731 static int lcd_enabled = 1;
 732
 733 void lcd_enable(void)
 734 {
 735         /* HACK ALERT:
 736          * global variable from common/lcd.c
 737          * Set to 0 here to prevent messages from going to LCD
 738          * rather than serial console
 739          */
 740         lcd_is_enabled = 0;
 741
 742         karo_load_splashimage(1);
 743
 744         if (lcd_enabled) {
 745                 debug("Switching LCD on\n");
 746                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 747                 udelay(100);
 748                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 749                 udelay(300000);
 750                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
 751         }
 752 }
 753
 754 void lcd_disable(void)
 755 {
 756         printf("Disabling LCD\n");
 757 }
 758
 759 void lcd_panel_disable(void)
 760 {
 761         if (lcd_enabled) {
 762                 debug("Switching LCD off\n");
 763                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 1);
 764                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
 765                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 766         }
 767 }
 768
 769 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 770         /* LCD RESET */
 771         MX6_PAD_EIM_D29__GPIO_3_29,
 772         /* LCD POWER_ENABLE */
 773         MX6_PAD_EIM_EB3__GPIO_2_31,
 774         /* LCD Backlight (PWM) */
 775         MX6_PAD_GPIO_1__GPIO_1_1,
 776
 777         /* Display */
 778         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 779         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 780         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 781         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 782         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 783         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 784         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 785         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 786         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 787         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 788         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 789         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 790         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 791         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 792         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 793         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 794         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 795         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 796         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 797         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 798         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 799         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 800         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 801         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 802         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 803         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 804         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 805         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 806 };
 807
 808 static const struct gpio stk5_lcd_gpios[] = {
 809         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 810         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 811         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 812 };
 813
 814 void lcd_ctrl_init(void *lcdbase)
 815 {
 816         int color_depth = 24;
 817         char *vm;
 818         unsigned long val;
 819         int refresh = 60;
 820         struct fb_videomode *p = &tx6_fb_modes[0];
 821         struct fb_videomode fb_mode;
 822         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 823         int pix_fmt = 0;
 824         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 825         unsigned long di_clk_rate = 65000000;
 826
 827         if (!lcd_enabled) {
 828                 debug("LCD disabled\n");
 829                 return;
 830         }
 831
 832         if (tstc() || (wrsr & WRSR_TOUT)) {
 833                 debug("Disabling LCD\n");
 834                 lcd_enabled = 0;
 835                 return;
 836         }
 837
 838         karo_fdt_move_fdt();
 839
 840         vm = getenv("video_mode");
 841         if (vm == NULL) {
 842                 debug("Disabling LCD\n");
 843                 lcd_enabled = 0;
 844                 return;
 845         }
 846         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 847                 p = &fb_mode;
 848                 debug("Using video mode from FDT\n");
 849                 vm += strlen(vm);
 850                 if (fb_mode.xres < panel_info.vl_col)
 851                         panel_info.vl_col = fb_mode.xres;
 852                 if (fb_mode.yres < panel_info.vl_row)
 853                         panel_info.vl_row = fb_mode.yres;
 854         }
 855         if (p->name != NULL)
 856                 debug("Trying compiled-in video modes\n");
 857         while (p->name != NULL) {
 858                 if (strcmp(p->name, vm) == 0) {
 859                         debug("Using video mode: '%s'\n", p->name);
 860                         vm += strlen(vm);
 861                         break;
 862                 }
 863                 p++;
 864         }
 865         if (*vm != '\0')
 866                 debug("Trying to decode video_mode: '%s'\n", vm);
 867         while (*vm != '\0') {
 868                 if (*vm >= '0' && *vm <= '9') {
 869                         char *end;
 870
 871                         val = simple_strtoul(vm, &end, 0);
 872                         if (end > vm) {
 873                                 if (!xres_set) {
 874                                         if (val > panel_info.vl_col)
 875                                                 val = panel_info.vl_col;
 876                                         p->xres = val;
 877                                         panel_info.vl_col = val;
 878                                         xres_set = 1;
 879                                 } else if (!yres_set) {
 880                                         if (val > panel_info.vl_row)
 881                                                 val = panel_info.vl_row;
 882                                         p->yres = val;
 883                                         panel_info.vl_row = val;
 884                                         yres_set = 1;
 885                                 } else if (!bpp_set) {
 886                                         switch (val) {
 887                                         case 32:
 888                                         case 24:
 889                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 890                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 891                                                 /* fallthru */
 892                                         case 16:
 893                                         case 8:
 894                                                 color_depth = val;
 895                                                 break;
 896
 897                                         case 18:
 898                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 899                                                         color_depth = val;
 900                                                         break;
 901                                                 }
 902                                                 /* fallthru */
 903                                         default:
 904                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 905                                                         end - vm, vm, color_depth);
 906                                         }
 907                                         bpp_set = 1;
 908                                 } else if (!refresh_set) {
 909                                         refresh = val;
 910                                         refresh_set = 1;
 911                                 }
 912                         }
 913                         vm = end;
 914                 }
 915                 switch (*vm) {
 916                 case '@':
 917                         bpp_set = 1;
 918                         /* fallthru */
 919                 case '-':
 920                         yres_set = 1;
 921                         /* fallthru */
 922                 case 'x':
 923                         xres_set = 1;
 924                         /* fallthru */
 925                 case 'M':
 926                 case 'R':
 927                         vm++;
 928                         break;
 929
 930                 default:
 931                         if (!pix_fmt) {
 932                                 char *tmp;
 933
 934                                 if (strncmp(vm, "LVDS", 4) == 0) {
 935                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 936                                         di_clk_parent = DI_PCLK_LDB;
 937                                 } else {
 938                                         pix_fmt = IPU_PIX_FMT_RGB24;
 939                                 }
 940                                 tmp = strchr(vm, ':');
 941                                 if (tmp)
 942                                         vm = tmp;
 943                         }
 944                         if (*vm != '\0')
 945                                 vm++;
 946                 }
 947         }
 948         if (p->xres == 0 || p->yres == 0) {
 949                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 950                 lcd_enabled = 0;
 951                 printf("Supported video modes are:");
 952                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
 953                         printf(" %s", p->name);
 954                 }
 955                 printf("\n");
 956                 return;
 957         }
 958
 959         p->pixclock = KHZ2PICOS(refresh *
 960                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 961                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 962                 / 1000);
 963         debug("Pixel clock set to %lu.%03lu MHz\n",
 964                 PICOS2KHZ(p->pixclock) / 1000,
 965                 PICOS2KHZ(p->pixclock) % 1000);
 966
 967         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 968         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 969                                         ARRAY_SIZE(stk5_lcd_pads));
 970
 971         debug("Initializing FB driver\n");
 972         if (!pix_fmt)
 973                 pix_fmt = IPU_PIX_FMT_RGB24;
 974         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 975                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 976         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 977                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 978         }
 979         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 980                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 981                 /* enable LDB & DI0 clock */
 982                 writel(readl(&ccm_regs->CCGR3) | MXC_CCM_CCGR3_LDB_DI0_MASK |
 983                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK,
 984                         &ccm_regs->CCGR3);
 985         }
 986
 987         if (karo_load_splashimage(0) == 0) {
 988                 debug("Initializing LCD controller\n");
 989                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 990         } else {
 991                 debug("Skipping initialization of LCD controller\n");
 992         }
 993 }
 994 #else
 995 #define lcd_enabled 0
 996 #endif /* CONFIG_LCD */
 997
 998 static void stk5_board_init(void)
 999 {
1000         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1001         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1002 }
1003
1004 static void stk5v3_board_init(void)
1005 {
1006         stk5_board_init();
1007 }
1008
1009 static void stk5v5_board_init(void)
1010 {
1011         stk5_board_init();
1012
1013         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1014                         "Flexcan Transceiver");
1015         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1016 }
1017
1018 static void tx6qdl_set_cpu_clock(void)
1019 {
1020         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1021
1022         if (tstc() || (wrsr & WRSR_TOUT))
1023                 return;
1024
1025         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1026                 return;
1027
1028         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1029                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1030                 printf("CPU clock set to %lu.%03lu MHz\n",
1031                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1032         } else {
1033                 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
1034         }
1035 }
1036
1037 static void tx6_init_mac(void)
1038 {
1039         u8 mac[ETH_ALEN];
1040
1041         imx_get_mac_from_fuse(-1, mac);
1042         if (!is_valid_ether_addr(mac)) {
1043                 printf("No valid MAC address programmed\n");
1044                 return;
1045         }
1046
1047         eth_setenv_enetaddr("ethaddr", mac);
1048         printf("MAC addr from fuse: %pM\n", mac);
1049 }
1050
1051 int board_late_init(void)
1052 {
1053         int ret = 0;
1054         const char *baseboard;
1055
1056         tx6qdl_set_cpu_clock();
1057         karo_fdt_move_fdt();
1058
1059         baseboard = getenv("baseboard");
1060         if (!baseboard)
1061                 goto exit;
1062
1063         printf("Baseboard: %s\n", baseboard);
1064
1065         if (strncmp(baseboard, "stk5", 4) == 0) {
1066                 if ((strlen(baseboard) == 4) ||
1067                         strcmp(baseboard, "stk5-v3") == 0) {
1068                         stk5v3_board_init();
1069                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1070                         stk5v5_board_init();
1071                 } else {
1072                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1073                                 baseboard + 4);
1074                 }
1075         } else {
1076                 printf("WARNING: Unsupported baseboard: '%s'\n",
1077                         baseboard);
1078                 ret = -EINVAL;
1079         }
1080
1081 exit:
1082         tx6_init_mac();
1083
1084         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1085         return ret;
1086 }
1087
1088 int checkboard(void)
1089 {
1090         u32 cpurev = get_cpu_rev();
1091         int cpu_variant = (cpurev >> 12) & 0xff;
1092
1093         tx6qdl_print_cpuinfo();
1094
1095         printf("Board: Ka-Ro TX6%c-%dxx%d\n",
1096                 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1097                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1098                 1 - PHYS_SDRAM_1_WIDTH / 64);
1099
1100         return 0;
1101 }
1102
1103 #ifdef CONFIG_SERIAL_TAG
1104 void get_board_serial(struct tag_serialnr *serialnr)
1105 {
1106         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1107         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1108
1109         serialnr->low = readl(&fuse->cfg0);
1110         serialnr->high = readl(&fuse->cfg1);
1111 }
1112 #endif
1113
1114 #if defined(CONFIG_OF_BOARD_SETUP)
1115 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1116 #include <jffs2/jffs2.h>
1117 #include <mtd_node.h>
1118 struct node_info nodes[] = {
1119         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1120 };
1121
1122 #else
1123 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1124 #endif
1125
1126 static void tx6qdl_fixup_flexcan(void *blob)
1127 {
1128         const char *baseboard = getenv("baseboard");
1129
1130         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1131                 return;
1132
1133         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch");
1134         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch");
1135 }
1136
1137 void ft_board_setup(void *blob, bd_t *bd)
1138 {
1139         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1140         fdt_fixup_ethernet(blob);
1141
1142         karo_fdt_fixup_touchpanel(blob);
1143         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1144         tx6qdl_fixup_flexcan(blob);
1145         karo_fdt_update_fb_mode(blob, getenv("video_mode"));
1146 }
1147 #endif