karo: tx6: remove unreachable 'return' statements
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
1 /*
2  * Copyright (C) 2012-2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
35 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
36 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
37 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
38
39 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
40 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
41 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
42
43 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
44 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
45 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
46
47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
48 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
49 #else
50 #define TEMPERATURE_MIN                 (-40)
51 #endif
52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
53 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
54 #else
55 #define TEMPERATURE_HOT                 80
56 #endif
57
58 DECLARE_GLOBAL_DATA_PTR;
59
60 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
61
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 #ifdef CONFIG_SECURE_BOOT
64 char __csf_data[0] __attribute__((section(".__csf_data")));
65 #endif
66
67 #define TX6_DEFAULT_PAD_CTRL    MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
68                                         PAD_CTL_SPEED_MED |             \
69                                         PAD_CTL_DSE_40ohm |             \
70                                         PAD_CTL_SRE_FAST)
71 #define TX6_FEC_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
72                                         PAD_CTL_SPEED_MED |             \
73                                         PAD_CTL_DSE_40ohm |             \
74                                         PAD_CTL_SRE_FAST)
75 #define TX6_GPIO_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
76                                         PAD_CTL_SPEED_MED |             \
77                                         PAD_CTL_DSE_34ohm |             \
78                                         PAD_CTL_SRE_FAST)
79 #define TX6_I2C_PAD_CTRL        MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
80                                         PAD_CTL_HYS |                   \
81                                         PAD_CTL_SPEED_LOW |             \
82                                         PAD_CTL_DSE_40ohm |             \
83                                         PAD_CTL_SRE_SLOW)
84
85 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
86         /* RESET_OUT */
87         MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
88
89         /* UART pads */
90 #if CONFIG_MXC_UART_BASE == UART1_BASE
91         MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
92         MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
93         MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
94         MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
95 #endif
96 #if CONFIG_MXC_UART_BASE == UART2_BASE
97         MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
98         MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
99         MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
100         MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
101 #endif
102 #if CONFIG_MXC_UART_BASE == UART3_BASE
103         MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
104         MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
105         MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
106         MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
107 #endif
108         /* internal I2C */
109         MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
110         MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
111
112         /* FEC PHY GPIO functions */
113         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
114                         TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
115         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
116                         TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
117         MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
118 };
119
120 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
121         /* FEC functions */
122         MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
123         MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
124         MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL,
125         MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
126         MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
127         MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
128         MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
129         MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
130         MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
131         MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
132 };
133
134 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
135         /* internal I2C */
136         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
137                         TX6_GPIO_PAD_CTRL,
138         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
139                         TX6_GPIO_PAD_CTRL,
140 };
141
142 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
143         /* internal I2C */
144         MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
145         MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
146 };
147
148 static const struct gpio const tx6qdl_gpios[] = {
149         /* These two entries are used to forcefully reinitialize the I2C bus */
150         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
151         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
152
153         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
154         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
155         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
156         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
157 };
158
159 static int pmic_addr __data;
160
161 #if defined(CONFIG_SOC_MX6Q)
162 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
163 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
164 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
165 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
166 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
167 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
168 #define I2C1_SEL_INPUT_VAL                      0
169 #endif
170 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
171 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
172 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
173 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
174 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
175 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
176 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
177 #define I2C1_SEL_INPUT_VAL                      1
178 #endif
179
180 #define GPIO_DR 0
181 #define GPIO_DIR 4
182 #define GPIO_PSR 8
183
184 static void tx6_i2c_recover(void)
185 {
186         int i;
187         int bad = 0;
188 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
189 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
190
191         if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
192                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
193                 return;
194
195         debug("Clearing I2C bus\n");
196         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
197                 printf("I2C SCL stuck LOW\n");
198                 bad++;
199
200                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
201                         GPIO3_BASE_ADDR + GPIO_DR);
202                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
203                         GPIO3_BASE_ADDR + GPIO_DIR);
204         }
205         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
206                 printf("I2C SDA stuck LOW\n");
207                 bad++;
208
209                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
210                         GPIO3_BASE_ADDR + GPIO_DIR);
211                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
212                         GPIO3_BASE_ADDR + GPIO_DR);
213                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
214                         GPIO3_BASE_ADDR + GPIO_DIR);
215
216                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
217                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
218                 udelay(10);
219
220                 for (i = 0; i < 18; i++) {
221                         u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
222
223                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
224                         writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
225                         udelay(10);
226                         if (reg & SCL_BIT &&
227                                 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
228                                 break;
229                 }
230         }
231         if (bad) {
232                 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
233
234                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
235                         printf("I2C bus recovery succeeded\n");
236                 } else {
237                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
238                                 SCL_BIT | SDA_BIT);
239                 }
240         }
241         debug("Setting up I2C Pads\n");
242         imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
243                                         ARRAY_SIZE(tx6_i2c_pads));
244 }
245
246 /* placed in section '.data' to prevent overwriting relocation info
247  * overlayed with bss
248  */
249 static u32 wrsr __data;
250
251 #define WRSR_POR                        (1 << 4)
252 #define WRSR_TOUT                       (1 << 1)
253 #define WRSR_SFTW                       (1 << 0)
254
255 static void print_reset_cause(void)
256 {
257         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
258         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
259         u32 srsr;
260         char *dlm = "";
261
262         printf("Reset cause: ");
263
264         srsr = readl(&src_regs->srsr);
265         wrsr = readw(wdt_base + 4);
266
267         if (wrsr & WRSR_POR) {
268                 printf("%sPOR", dlm);
269                 dlm = " | ";
270         }
271         if (srsr & 0x00004) {
272                 printf("%sCSU", dlm);
273                 dlm = " | ";
274         }
275         if (srsr & 0x00008) {
276                 printf("%sIPP USER", dlm);
277                 dlm = " | ";
278         }
279         if (srsr & 0x00010) {
280                 if (wrsr & WRSR_SFTW) {
281                         printf("%sSOFT", dlm);
282                         dlm = " | ";
283                 }
284                 if (wrsr & WRSR_TOUT) {
285                         printf("%sWDOG", dlm);
286                         dlm = " | ";
287                 }
288         }
289         if (srsr & 0x00020) {
290                 printf("%sJTAG HIGH-Z", dlm);
291                 dlm = " | ";
292         }
293         if (srsr & 0x00040) {
294                 printf("%sJTAG SW", dlm);
295                 dlm = " | ";
296         }
297         if (srsr & 0x10000) {
298                 printf("%sWARM BOOT", dlm);
299                 dlm = " | ";
300         }
301         if (dlm[0] == '\0')
302                 printf("unknown");
303
304         printf("\n");
305 }
306
307 static const char __data *tx6_mod_suffix;
308
309 #ifdef CONFIG_IMX6_THERMAL
310 #include <thermal.h>
311 #include <imx_thermal.h>
312 #include <fuse.h>
313
314 static void print_temperature(void)
315 {
316         struct udevice *thermal_dev;
317         int cpu_tmp, minc, maxc, ret;
318         char const *grade_str;
319         static u32 __data thermal_calib;
320
321         puts("Temperature: ");
322         switch (get_cpu_temp_grade(&minc, &maxc)) {
323         case TEMP_AUTOMOTIVE:
324                 grade_str = "Automotive";
325                 break;
326         case TEMP_INDUSTRIAL:
327                 grade_str = "Industrial";
328                 break;
329         case TEMP_EXTCOMMERCIAL:
330                 grade_str = "Extended Commercial";
331                 break;
332         default:
333                 grade_str = "Commercial";
334         }
335         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
336         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
337         if (ret == 0) {
338                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
339
340                 if (ret == 0)
341                         printf(" at %dC", cpu_tmp);
342                 else
343                         puts(" - failed to read sensor data");
344         } else {
345                 puts(" - no sensor device found");
346         }
347
348         if (fuse_read(1, 6, &thermal_calib) == 0) {
349                 printf(" - calibration data 0x%08x\n", thermal_calib);
350         } else {
351                 puts(" - Failed to read thermal calib fuse\n");
352         }
353 }
354 #else
355 static inline void print_temperature(void)
356 {
357 }
358 #endif
359
360 int checkboard(void)
361 {
362         u32 cpurev = get_cpu_rev();
363         char *cpu_str = "?";
364
365         if (is_cpu_type(MXC_CPU_MX6SL)) {
366                 cpu_str = "SL";
367                 tx6_mod_suffix = "?";
368         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
369                 cpu_str = "DL";
370                 tx6_mod_suffix = "U";
371         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
372                 cpu_str = "SOLO";
373                 tx6_mod_suffix = "S";
374         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
375                 cpu_str = "Q";
376                 tx6_mod_suffix = "Q";
377         } else if (is_cpu_type(MXC_CPU_MX6QP)) {
378                 cpu_str = "QP";
379                 tx6_mod_suffix = "QP";
380         }
381
382         printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
383                 cpu_str,
384                 (cpurev & 0x000F0) >> 4,
385                 (cpurev & 0x0000F) >> 0,
386                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
387
388         print_temperature();
389         print_reset_cause();
390 #ifdef CONFIG_MX6_TEMPERATURE_HOT
391         check_cpu_temperature(1);
392 #endif
393         tx6_i2c_recover();
394         return 0;
395 }
396
397 /* serial port not initialized at this point */
398 int board_early_init_f(void)
399 {
400         return 0;
401 }
402
403 #ifndef CONFIG_MX6_TEMPERATURE_HOT
404 static bool tx6_temp_check_enabled = true;
405 #else
406 #define tx6_temp_check_enabled  0
407 #endif
408
409 #ifdef CONFIG_TX6_NAND
410 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
411 #else
412 #ifdef CONFIG_MMC_BOOT_SIZE
413 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
414 #else
415 #define TX6_FLASH_SZ    2
416 #endif
417 #endif /* CONFIG_TX6_NAND */
418
419 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
420
421 static char tx6_mem_table[] = {
422         '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
423         '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
424         '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
425         '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
426         '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
427         '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
428         '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
429         '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
430         '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
431         '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
432         '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
433 #if defined(CONFIG_TX6_REV) && CONFIG_TX6_REV == 2
434         '0', /* TX6Q-1020 (legacy) 1GiB SDRAM 64bit; 8GiB eMMC */
435 #else
436         '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
437 #endif
438 };
439
440 static struct {
441         uchar addr;
442         uchar rev;
443 } tx6_mod_revs[] = {
444         { 0x3c, 1, },
445         { 0x32, 2, },
446         { 0x33, 3, },
447 };
448
449 static inline char tx6_mem_suffix(void)
450 {
451         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
452
453         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
454                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
455
456         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
457                 return '?';
458         if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
459                 return '7';
460         if (mem_idx == 8)
461                 return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
462         return tx6_mem_table[mem_idx];
463 };
464
465 static int tx6_get_mod_rev(unsigned int pmic_id)
466 {
467         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
468                 return tx6_mod_revs[pmic_id].rev;
469
470         return 0;
471 }
472
473 static int tx6_pmic_probe(void)
474 {
475         int i;
476
477         debug("%s@%d: \n", __func__, __LINE__);
478
479         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
480                 u8 i2c_addr = tx6_mod_revs[i].addr;
481                 int ret = i2c_probe(i2c_addr);
482
483                 if (ret == 0) {
484                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
485                         return i;
486                 }
487                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
488         }
489         return -EINVAL;
490 }
491
492 int board_init(void)
493 {
494         int ret;
495         int pmic_id;
496
497         debug("%s@%d: \n", __func__, __LINE__);
498
499         pmic_id = tx6_pmic_probe();
500         if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
501                 pmic_addr = tx6_mod_revs[pmic_id].addr;
502
503         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
504                 tx6_mod_suffix,
505                 is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
506                 is_lvds(), tx6_get_mod_rev(pmic_id),
507                 tx6_mem_suffix());
508
509         get_hab_status();
510
511         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
512         if (ret < 0) {
513                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
514         }
515         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
516
517         /* Address of boot parameters */
518         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
519         gd->bd->bi_arch_number = -1;
520
521         if (ctrlc() || (wrsr & WRSR_TOUT)) {
522                 if (wrsr & WRSR_TOUT)
523                         printf("WDOG RESET detected; Skipping PMIC setup\n");
524                 else
525                         printf("<CTRL-C> detected; safeboot enabled\n");
526 #ifndef CONFIG_MX6_TEMPERATURE_HOT
527                 tx6_temp_check_enabled = false;
528 #endif
529                 return 0;
530         }
531
532         ret = tx6_pmic_init(pmic_addr, NULL, 0);
533         if (ret) {
534                 printf("Failed to setup PMIC voltages: %d\n", ret);
535                 hang();
536         }
537         return 0;
538 }
539
540 int dram_init(void)
541 {
542         debug("%s@%d: \n", __func__, __LINE__);
543
544         /* dram_init must store complete ramsize in gd->ram_size */
545         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
546                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
547         return 0;
548 }
549
550 void dram_init_banksize(void)
551 {
552         debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
553                 CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
554         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
555         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
556                         PHYS_SDRAM_1_SIZE);
557 #if CONFIG_NR_DRAM_BANKS > 1
558         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
559         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
560                         PHYS_SDRAM_2_SIZE);
561 #endif
562 }
563
564 #ifdef  CONFIG_FSL_ESDHC
565 #define SD_PAD_CTRL             MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
566                                 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
567                                 PAD_CTL_SRE_FAST)
568
569 static const iomux_v3_cfg_t mmc0_pads[] = {
570         MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
571         MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
572         MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
573         MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
574         MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
575         MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
576         /* SD1 CD */
577         MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
578 };
579
580 static const iomux_v3_cfg_t mmc1_pads[] = {
581         MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
582         MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
583         MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
584         MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
585         MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
586         MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
587         /* SD2 CD */
588         MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
589 };
590
591 #ifdef CONFIG_TX6_EMMC
592 static const iomux_v3_cfg_t mmc3_pads[] = {
593         MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
594         MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
595         MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
596         MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
597         MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
598         MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
599         /* eMMC RESET */
600         MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
601 };
602 #endif
603
604 static struct tx6_esdhc_cfg {
605         const iomux_v3_cfg_t *pads;
606         int num_pads;
607         enum mxc_clock clkid;
608         struct fsl_esdhc_cfg cfg;
609         int cd_gpio;
610 } tx6qdl_esdhc_cfg[] = {
611 #ifdef CONFIG_TX6_EMMC
612         {
613                 .pads = mmc3_pads,
614                 .num_pads = ARRAY_SIZE(mmc3_pads),
615                 .clkid = MXC_ESDHC4_CLK,
616                 .cfg = {
617                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
618                         .max_bus_width = 4,
619                 },
620                 .cd_gpio = -EINVAL,
621         },
622 #endif
623         {
624                 .pads = mmc0_pads,
625                 .num_pads = ARRAY_SIZE(mmc0_pads),
626                 .clkid = MXC_ESDHC_CLK,
627                 .cfg = {
628                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
629                         .max_bus_width = 4,
630                 },
631                 .cd_gpio = IMX_GPIO_NR(7, 2),
632         },
633         {
634                 .pads = mmc1_pads,
635                 .num_pads = ARRAY_SIZE(mmc1_pads),
636                 .clkid = MXC_ESDHC2_CLK,
637                 .cfg = {
638                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
639                         .max_bus_width = 4,
640                 },
641                 .cd_gpio = IMX_GPIO_NR(7, 3),
642         },
643 };
644
645 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
646 {
647         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
648 }
649
650 int board_mmc_getcd(struct mmc *mmc)
651 {
652         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
653
654         if (cfg->cd_gpio < 0)
655                 return 1;
656
657         debug("SD card %d is %spresent (GPIO %d)\n",
658                 cfg - tx6qdl_esdhc_cfg,
659                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
660                 cfg->cd_gpio);
661         return !gpio_get_value(cfg->cd_gpio);
662 }
663
664 int board_mmc_init(bd_t *bis)
665 {
666         int i;
667
668         debug("%s@%d: \n", __func__, __LINE__);
669
670         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
671                 struct mmc *mmc;
672                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
673                 int ret;
674
675                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
676                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
677
678                 if (cfg->cd_gpio >= 0) {
679                         ret = gpio_request_one(cfg->cd_gpio,
680                                         GPIOFLAG_INPUT, "MMC CD");
681                         if (ret) {
682                                 printf("Error %d requesting GPIO%d_%d\n",
683                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
684                                 continue;
685                         }
686                 }
687
688                 debug("%s: Initializing MMC slot %d\n", __func__, i);
689                 fsl_esdhc_initialize(bis, &cfg->cfg);
690
691                 mmc = find_mmc_device(i);
692                 if (mmc == NULL)
693                         continue;
694                 if (board_mmc_getcd(mmc))
695                         mmc_init(mmc);
696         }
697         return 0;
698 }
699 #endif /* CONFIG_CMD_MMC */
700
701 #ifdef CONFIG_FEC_MXC
702
703 #ifndef ETH_ALEN
704 #define ETH_ALEN 6
705 #endif
706
707 int board_eth_init(bd_t *bis)
708 {
709         int ret;
710
711         debug("%s@%d: \n", __func__, __LINE__);
712
713         /* delay at least 21ms for the PHY internal POR signal to deassert */
714         udelay(22000);
715
716         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
717                                         ARRAY_SIZE(tx6qdl_fec_pads));
718
719         /* Deassert RESET to the external phy */
720         gpio_set_value(TX6_FEC_RST_GPIO, 1);
721
722         ret = cpu_eth_init(bis);
723         if (ret)
724                 printf("cpu_eth_init() failed: %d\n", ret);
725
726         return ret;
727 }
728
729 static void tx6_init_mac(void)
730 {
731         u8 mac[ETH_ALEN];
732
733         imx_get_mac_from_fuse(0, mac);
734         if (!is_valid_ethaddr(mac)) {
735                 printf("No valid MAC address programmed\n");
736                 return;
737         }
738
739         printf("MAC addr from fuse: %pM\n", mac);
740         eth_setenv_enetaddr("ethaddr", mac);
741 }
742 #else
743 static inline void tx6_init_mac(void)
744 {
745 }
746 #endif /* CONFIG_FEC_MXC */
747
748 enum {
749         LED_STATE_INIT = -1,
750         LED_STATE_OFF,
751         LED_STATE_ON,
752 };
753
754 static inline int calc_blink_rate(void)
755 {
756         if (!tx6_temp_check_enabled)
757                 return CONFIG_SYS_HZ;
758
759         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
760                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
761                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
762 }
763
764 void show_activity(int arg)
765 {
766         static int led_state = LED_STATE_INIT;
767         static int blink_rate;
768         static ulong last;
769
770         if (led_state == LED_STATE_INIT) {
771                 last = get_timer(0);
772                 gpio_set_value(TX6_LED_GPIO, 1);
773                 led_state = LED_STATE_ON;
774                 blink_rate = calc_blink_rate();
775         } else {
776                 if (get_timer(last) > blink_rate) {
777                         blink_rate = calc_blink_rate();
778                         last = get_timer_masked();
779                         if (led_state == LED_STATE_ON) {
780                                 gpio_set_value(TX6_LED_GPIO, 0);
781                         } else {
782                                 gpio_set_value(TX6_LED_GPIO, 1);
783                         }
784                         led_state = 1 - led_state;
785                 }
786         }
787 }
788
789 static const iomux_v3_cfg_t stk5_pads[] = {
790         /* SW controlled LED on STK5 baseboard */
791         MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
792
793         /* I2C bus on DIMM pins 40/41 */
794         MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
795         MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
796
797         /* TSC200x PEN IRQ */
798         MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
799
800         /* EDT-FT5x06 Polytouch panel */
801         MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
802         MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
803         MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
804
805         /* USBH1 */
806         MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
807         MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
808         /* USBOTG */
809         MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
810         MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
811         MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
812 };
813
814 static const struct gpio stk5_gpios[] = {
815         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
816
817         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
818         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
819         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
820         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
821         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
822 };
823
824 #ifdef CONFIG_LCD
825 vidinfo_t panel_info = {
826         /* set to max. size supported by SoC */
827         .vl_col = 1920,
828         .vl_row = 1080,
829
830         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
831 };
832
833 static struct fb_videomode tx6_fb_modes[] = {
834 #ifndef CONFIG_SYS_LVDS_IF
835         {
836                 /* Standard VGA timing */
837                 .name           = "VGA",
838                 .refresh        = 60,
839                 .xres           = 640,
840                 .yres           = 480,
841                 .pixclock       = KHZ2PICOS(25175),
842                 .left_margin    = 48,
843                 .hsync_len      = 96,
844                 .right_margin   = 16,
845                 .upper_margin   = 31,
846                 .vsync_len      = 2,
847                 .lower_margin   = 12,
848                 .sync           = FB_SYNC_CLK_LAT_FALL,
849         },
850         {
851                 /* Emerging ETV570 640 x 480 display. Syncs low active,
852                  * DE high active, 115.2 mm x 86.4 mm display area
853                  * VGA compatible timing
854                  */
855                 .name           = "ETV570",
856                 .refresh        = 60,
857                 .xres           = 640,
858                 .yres           = 480,
859                 .pixclock       = KHZ2PICOS(25175),
860                 .left_margin    = 114,
861                 .hsync_len      = 30,
862                 .right_margin   = 16,
863                 .upper_margin   = 32,
864                 .vsync_len      = 3,
865                 .lower_margin   = 10,
866                 .sync           = FB_SYNC_CLK_LAT_FALL,
867         },
868         {
869                 /* Emerging ET0350G0DH6 320 x 240 display.
870                  * 70.08 mm x 52.56 mm display area.
871                  */
872                 .name           = "ET0350",
873                 .refresh        = 60,
874                 .xres           = 320,
875                 .yres           = 240,
876                 .pixclock       = KHZ2PICOS(6500),
877                 .left_margin    = 68 - 34,
878                 .hsync_len      = 34,
879                 .right_margin   = 20,
880                 .upper_margin   = 18 - 3,
881                 .vsync_len      = 3,
882                 .lower_margin   = 4,
883                 .sync           = FB_SYNC_CLK_LAT_FALL,
884         },
885         {
886                 /* Emerging ET0430G0DH6 480 x 272 display.
887                  * 95.04 mm x 53.856 mm display area.
888                  */
889                 .name           = "ET0430",
890                 .refresh        = 60,
891                 .xres           = 480,
892                 .yres           = 272,
893                 .pixclock       = KHZ2PICOS(9000),
894                 .left_margin    = 2,
895                 .hsync_len      = 41,
896                 .right_margin   = 2,
897                 .upper_margin   = 2,
898                 .vsync_len      = 10,
899                 .lower_margin   = 2,
900         },
901         {
902                 /* Emerging ET0500G0DH6 800 x 480 display.
903                  * 109.6 mm x 66.4 mm display area.
904                  */
905                 .name           = "ET0500",
906                 .refresh        = 60,
907                 .xres           = 800,
908                 .yres           = 480,
909                 .pixclock       = KHZ2PICOS(33260),
910                 .left_margin    = 216 - 128,
911                 .hsync_len      = 128,
912                 .right_margin   = 1056 - 800 - 216,
913                 .upper_margin   = 35 - 2,
914                 .vsync_len      = 2,
915                 .lower_margin   = 525 - 480 - 35,
916                 .sync           = FB_SYNC_CLK_LAT_FALL,
917         },
918         {
919                 /* Emerging ETQ570G0DH6 320 x 240 display.
920                  * 115.2 mm x 86.4 mm display area.
921                  */
922                 .name           = "ETQ570",
923                 .refresh        = 60,
924                 .xres           = 320,
925                 .yres           = 240,
926                 .pixclock       = KHZ2PICOS(6400),
927                 .left_margin    = 38,
928                 .hsync_len      = 30,
929                 .right_margin   = 30,
930                 .upper_margin   = 16, /* 15 according to datasheet */
931                 .vsync_len      = 3, /* TVP -> 1>x>5 */
932                 .lower_margin   = 4, /* 4.5 according to datasheet */
933                 .sync           = FB_SYNC_CLK_LAT_FALL,
934         },
935         {
936                 /* Emerging ET0700G0DH6 800 x 480 display.
937                  * 152.4 mm x 91.44 mm display area.
938                  */
939                 .name           = "ET0700",
940                 .refresh        = 60,
941                 .xres           = 800,
942                 .yres           = 480,
943                 .pixclock       = KHZ2PICOS(33260),
944                 .left_margin    = 216 - 128,
945                 .hsync_len      = 128,
946                 .right_margin   = 1056 - 800 - 216,
947                 .upper_margin   = 35 - 2,
948                 .vsync_len      = 2,
949                 .lower_margin   = 525 - 480 - 35,
950                 .sync           = FB_SYNC_CLK_LAT_FALL,
951         },
952         {
953                 /* Emerging ET070001DM6 800 x 480 display.
954                  * 152.4 mm x 91.44 mm display area.
955                  */
956                 .name           = "ET070001DM6",
957                 .refresh        = 60,
958                 .xres           = 800,
959                 .yres           = 480,
960                 .pixclock       = KHZ2PICOS(33260),
961                 .left_margin    = 216 - 128,
962                 .hsync_len      = 128,
963                 .right_margin   = 1056 - 800 - 216,
964                 .upper_margin   = 35 - 2,
965                 .vsync_len      = 2,
966                 .lower_margin   = 525 - 480 - 35,
967                 .sync           = 0,
968         },
969 #else
970         {
971                 /* HannStar HSD100PXN1
972                  * 202.7m mm x 152.06 mm display area.
973                  */
974                 .name           = "HSD100PXN1",
975                 .refresh        = 60,
976                 .xres           = 1024,
977                 .yres           = 768,
978                 .pixclock       = KHZ2PICOS(65000),
979                 .left_margin    = 0,
980                 .hsync_len      = 0,
981                 .right_margin   = 320,
982                 .upper_margin   = 0,
983                 .vsync_len      = 0,
984                 .lower_margin   = 38,
985                 .sync           = FB_SYNC_CLK_LAT_FALL,
986         },
987 #endif
988         {
989                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
990                 .refresh        = 60,
991                 .left_margin    = 48,
992                 .hsync_len      = 96,
993                 .right_margin   = 16,
994                 .upper_margin   = 31,
995                 .vsync_len      = 2,
996                 .lower_margin   = 12,
997                 .sync           = FB_SYNC_CLK_LAT_FALL,
998         },
999 };
1000
1001 static int lcd_enabled = 1;
1002 static int lcd_bl_polarity;
1003
1004 static int lcd_backlight_polarity(void)
1005 {
1006         return lcd_bl_polarity;
1007 }
1008
1009 void lcd_enable(void)
1010 {
1011         /* HACK ALERT:
1012          * global variable from common/lcd.c
1013          * Set to 0 here to prevent messages from going to LCD
1014          * rather than serial console
1015          */
1016         lcd_is_enabled = 0;
1017
1018         if (lcd_enabled) {
1019                 karo_load_splashimage(1);
1020
1021                 debug("Switching LCD on\n");
1022                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1023                 udelay(100);
1024                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1025                 udelay(300000);
1026                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1027                         lcd_backlight_polarity());
1028         }
1029 }
1030
1031 void lcd_disable(void)
1032 {
1033         if (lcd_enabled) {
1034                 printf("Disabling LCD\n");
1035                 ipuv3_fb_shutdown();
1036         }
1037 }
1038
1039 void lcd_panel_disable(void)
1040 {
1041         if (lcd_enabled) {
1042                 debug("Switching LCD off\n");
1043                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1044                         !lcd_backlight_polarity());
1045                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1046                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1047         }
1048 }
1049
1050 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1051         /* LCD RESET */
1052         MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
1053         /* LCD POWER_ENABLE */
1054         MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
1055         /* LCD Backlight (PWM) */
1056         MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
1057
1058 #ifndef CONFIG_SYS_LVDS_IF
1059         /* Display */
1060         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
1061         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
1062         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
1063         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
1064         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
1065         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
1066         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
1067         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
1068         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
1069         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
1070         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
1071         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
1072         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
1073         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
1074         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
1075         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
1076         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
1077         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
1078         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
1079         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
1080         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
1081         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
1082         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
1083         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
1084         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
1085         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
1086         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
1087         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
1088 #endif
1089 };
1090
1091 static const struct gpio stk5_lcd_gpios[] = {
1092         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1093         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1094         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1095 };
1096
1097 void lcd_ctrl_init(void *lcdbase)
1098 {
1099         int color_depth = 24;
1100         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1101         const char *vm;
1102         unsigned long val;
1103         int refresh = 60;
1104         struct fb_videomode *p = &tx6_fb_modes[0];
1105         struct fb_videomode fb_mode;
1106         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1107         int pix_fmt;
1108         int lcd_bus_width;
1109         unsigned long di_clk_rate = 65000000;
1110
1111         if (!lcd_enabled) {
1112                 debug("LCD disabled\n");
1113                 goto disable;
1114         }
1115
1116         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1117                 debug("Disabling LCD\n");
1118                 lcd_enabled = 0;
1119                 setenv("splashimage", NULL);
1120                 goto disable;
1121         }
1122
1123         karo_fdt_move_fdt();
1124         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1125
1126         if (video_mode == NULL) {
1127                 debug("Disabling LCD\n");
1128                 lcd_enabled = 0;
1129                 goto disable;
1130         }
1131         vm = video_mode;
1132         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1133                 p = &fb_mode;
1134                 debug("Using video mode from FDT\n");
1135                 vm += strlen(vm);
1136                 if (fb_mode.xres > panel_info.vl_col ||
1137                         fb_mode.yres > panel_info.vl_row) {
1138                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1139                                 fb_mode.xres, fb_mode.yres,
1140                                 panel_info.vl_col, panel_info.vl_row);
1141                         lcd_enabled = 0;
1142                         goto disable;
1143                 }
1144         }
1145         if (p->name != NULL)
1146                 debug("Trying compiled-in video modes\n");
1147         while (p->name != NULL) {
1148                 if (strcmp(p->name, vm) == 0) {
1149                         debug("Using video mode: '%s'\n", p->name);
1150                         vm += strlen(vm);
1151                         break;
1152                 }
1153                 p++;
1154         }
1155         if (*vm != '\0')
1156                 debug("Trying to decode video_mode: '%s'\n", vm);
1157         while (*vm != '\0') {
1158                 if (*vm >= '0' && *vm <= '9') {
1159                         char *end;
1160
1161                         val = simple_strtoul(vm, &end, 0);
1162                         if (end > vm) {
1163                                 if (!xres_set) {
1164                                         if (val > panel_info.vl_col)
1165                                                 val = panel_info.vl_col;
1166                                         p->xres = val;
1167                                         panel_info.vl_col = val;
1168                                         xres_set = 1;
1169                                 } else if (!yres_set) {
1170                                         if (val > panel_info.vl_row)
1171                                                 val = panel_info.vl_row;
1172                                         p->yres = val;
1173                                         panel_info.vl_row = val;
1174                                         yres_set = 1;
1175                                 } else if (!bpp_set) {
1176                                         switch (val) {
1177                                         case 32:
1178                                         case 24:
1179                                                 if (is_lvds())
1180                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1181                                                 /* fallthru */
1182                                         case 16:
1183                                         case 8:
1184                                                 color_depth = val;
1185                                                 break;
1186
1187                                         case 18:
1188                                                 if (is_lvds()) {
1189                                                         color_depth = val;
1190                                                         break;
1191                                                 }
1192                                                 /* fallthru */
1193                                         default:
1194                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1195                                                         end - vm, vm, color_depth);
1196                                         }
1197                                         bpp_set = 1;
1198                                 } else if (!refresh_set) {
1199                                         refresh = val;
1200                                         refresh_set = 1;
1201                                 }
1202                         }
1203                         vm = end;
1204                 }
1205                 switch (*vm) {
1206                 case '@':
1207                         bpp_set = 1;
1208                         /* fallthru */
1209                 case '-':
1210                         yres_set = 1;
1211                         /* fallthru */
1212                 case 'x':
1213                         xres_set = 1;
1214                         /* fallthru */
1215                 case 'M':
1216                 case 'R':
1217                         vm++;
1218                         break;
1219
1220                 default:
1221                         if (*vm != '\0')
1222                                 vm++;
1223                 }
1224         }
1225         if (p->xres == 0 || p->yres == 0) {
1226                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1227                 lcd_enabled = 0;
1228                 printf("Supported video modes are:");
1229                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1230                         printf(" %s", p->name);
1231                 }
1232                 printf("\n");
1233                 goto disable;
1234         }
1235         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1236                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1237                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1238                 lcd_enabled = 0;
1239                 goto disable;
1240         }
1241         panel_info.vl_col = p->xres;
1242         panel_info.vl_row = p->yres;
1243
1244         switch (color_depth) {
1245         case 8:
1246                 panel_info.vl_bpix = LCD_COLOR8;
1247                 break;
1248         case 16:
1249                 panel_info.vl_bpix = LCD_COLOR16;
1250                 break;
1251         default:
1252                 panel_info.vl_bpix = LCD_COLOR32;
1253         }
1254
1255         p->pixclock = KHZ2PICOS(refresh *
1256                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1257                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1258                                 1000);
1259         debug("Pixel clock set to %lu.%03lu MHz\n",
1260                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1261
1262         if (p != &fb_mode) {
1263                 int ret;
1264
1265                 debug("Creating new display-timing node from '%s'\n",
1266                         video_mode);
1267                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1268                 if (ret)
1269                         printf("Failed to create new display-timing node from '%s': %d\n",
1270                                 video_mode, ret);
1271         }
1272
1273         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1274         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1275                                         ARRAY_SIZE(stk5_lcd_pads));
1276
1277         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1278         switch (lcd_bus_width) {
1279         case 24:
1280                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1281                 break;
1282
1283         case 18:
1284                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1285                 break;
1286
1287         case 16:
1288                 if (!is_lvds()) {
1289                         pix_fmt = IPU_PIX_FMT_RGB565;
1290                         break;
1291                 }
1292                 /* fallthru */
1293         default:
1294                 lcd_enabled = 0;
1295                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1296                         lcd_bus_width);
1297                 goto disable;
1298         }
1299         if (is_lvds()) {
1300                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1301                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1302                 uint32_t gpr2;
1303                 uint32_t gpr3;
1304
1305                 if (lvds_chan_mask == 0) {
1306                         printf("No LVDS channel active\n");
1307                         lcd_enabled = 0;
1308                         goto disable;
1309                 }
1310
1311                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1312                 if (lcd_bus_width == 24)
1313                         gpr2 |= (1 << 5) | (1 << 7);
1314                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1315                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1316                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1317                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1318
1319                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1320                 gpr3 &= ~((3 << 8) | (3 << 6));
1321                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1322         }
1323         if (karo_load_splashimage(0) == 0) {
1324                 int ret;
1325
1326                 debug("Initializing LCD controller\n");
1327                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1328                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1329                                 di_clk_rate, -1);
1330                 if (ret) {
1331                         printf("Failed to initialize FB driver: %d\n", ret);
1332                         lcd_enabled = 0;
1333                 }
1334         } else {
1335                 debug("Skipping initialization of LCD controller\n");
1336         }
1337         return;
1338
1339 disable:
1340         lcd_enabled = 0;
1341         panel_info.vl_col = 0;
1342         panel_info.vl_row = 0;
1343
1344 }
1345 #else
1346 #define lcd_enabled 0
1347 #endif /* CONFIG_LCD */
1348
1349 static void stk5_board_init(void)
1350 {
1351         int ret;
1352
1353         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1354         if (ret < 0) {
1355                 printf("Failed to request stk5_gpios: %d\n", ret);
1356                 return;
1357         }
1358         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1359 }
1360
1361 static void stk5v3_board_init(void)
1362 {
1363         stk5_board_init();
1364 }
1365
1366 static void stk5v5_board_init(void)
1367 {
1368         int ret;
1369
1370         stk5_board_init();
1371
1372         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1373                         "Flexcan Transceiver");
1374         if (ret) {
1375                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1376                 return;
1377         }
1378
1379         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
1380                         TX6_GPIO_PAD_CTRL);
1381 }
1382
1383 static void tx6qdl_set_cpu_clock(void)
1384 {
1385         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1386
1387         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1388                 return;
1389
1390         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1391                 printf("%s detected; skipping cpu clock change\n",
1392                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1393                 return;
1394         }
1395         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1396                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1397                 printf("CPU clock set to %lu.%03lu MHz\n",
1398                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1399         } else {
1400                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1401         }
1402 }
1403
1404 int board_late_init(void)
1405 {
1406         const char *baseboard;
1407
1408         debug("%s@%d: \n", __func__, __LINE__);
1409
1410         env_cleanup();
1411
1412         if (tx6_temp_check_enabled)
1413                 check_cpu_temperature(1);
1414
1415         tx6qdl_set_cpu_clock();
1416
1417         if (had_ctrlc())
1418                 setenv_ulong("safeboot", 1);
1419         else if (wrsr & WRSR_TOUT)
1420                 setenv_ulong("wdreset", 1);
1421         else
1422                 karo_fdt_move_fdt();
1423
1424         baseboard = getenv("baseboard");
1425         if (!baseboard)
1426                 goto exit;
1427
1428         printf("Baseboard: %s\n", baseboard);
1429
1430         if (strncmp(baseboard, "stk5", 4) == 0) {
1431                 if ((strlen(baseboard) == 4) ||
1432                         strcmp(baseboard, "stk5-v3") == 0) {
1433                         stk5v3_board_init();
1434                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1435                         const char *otg_mode = getenv("otg_mode");
1436
1437                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1438                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1439                                         otg_mode, baseboard);
1440                                 setenv("otg_mode", "none");
1441                         }
1442                         stk5v5_board_init();
1443                 } else {
1444                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1445                                 baseboard + 4);
1446                 }
1447         } else {
1448                 printf("WARNING: Unsupported baseboard: '%s'\n",
1449                         baseboard);
1450                 if (!had_ctrlc())
1451                         return -EINVAL;
1452         }
1453
1454 exit:
1455         tx6_init_mac();
1456
1457         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1458         clear_ctrlc();
1459         return 0;
1460 }
1461
1462 #ifdef CONFIG_SERIAL_TAG
1463 void get_board_serial(struct tag_serialnr *serialnr)
1464 {
1465         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1466         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1467
1468         serialnr->low = readl(&fuse->cfg0);
1469         serialnr->high = readl(&fuse->cfg1);
1470 }
1471 #endif
1472
1473 #if defined(CONFIG_OF_BOARD_SETUP)
1474 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1475 #include <jffs2/jffs2.h>
1476 #include <mtd_node.h>
1477 static struct node_info nodes[] = {
1478         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1479 };
1480 #else
1481 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1482 #endif
1483
1484 static const char *tx6_touchpanels[] = {
1485         "ti,tsc2007",
1486         "edt,edt-ft5x06",
1487         "eeti,egalax_ts",
1488 };
1489
1490 int ft_board_setup(void *blob, bd_t *bd)
1491 {
1492         const char *baseboard = getenv("baseboard");
1493         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1494         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1495         int ret;
1496
1497         ret = fdt_increase_size(blob, 4096);
1498         if (ret) {
1499                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1500                 return ret;
1501         }
1502         if (stk5_v5)
1503                 karo_fdt_enable_node(blob, "stk5led", 0);
1504
1505         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1506
1507         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1508                                 ARRAY_SIZE(tx6_touchpanels));
1509         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1510         karo_fdt_fixup_flexcan(blob, stk5_v5);
1511
1512         karo_fdt_update_fb_mode(blob, video_mode);
1513
1514         return 0;
1515 }
1516 #endif /* CONFIG_OF_BOARD_SETUP */