board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <errno.h>
  25 #include <libfdt.h>
  26 #include <fdt_support.h>
  27 #include <lcd.h>
  28 #include <netdev.h>
  29 #include <mmc.h>
  30 #include <fsl_esdhc.h>
  31 #include <video_fb.h>
  32 #include <ipu.h>
  33 #include <mx2fb.h>
  34 #include <linux/fb.h>
  35 #include <i2c.h>
  36 #include <asm/io.h>
  37 #include <asm/gpio.h>
  38 #include <asm/arch/iomux-mx6.h>
  39 #include <asm/arch/clock.h>
  40 #include <asm/arch/imx-regs.h>
  41 #include <asm/arch/crm_regs.h>
  42 #include <asm/arch/sys_proto.h>
  43
  44 #include "../common/karo.h"
  45
  46 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  47 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  48 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(2, 4)
  49 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  50
  51 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  52 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  53 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  54
  55 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  56
  57 #define TEMPERATURE_MIN                 -40
  58 #define TEMPERATURE_HOT                 80
  59 #define TEMPERATURE_MAX                 125
  60
  61 DECLARE_GLOBAL_DATA_PTR;
  62
  63 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, MUX_CONFIG_SION, 0, 0, 0)
  64
  65 static const iomux_v3_cfg_t tx6qdl_pads[] = {
  66         /* NAND flash pads */
  67         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
  68         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
  69         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
  70         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
  71         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
  72         MX6_PAD_SD4_CMD__RAWNAND_RDN,
  73         MX6_PAD_SD4_CLK__RAWNAND_WRN,
  74         MX6_PAD_NANDF_D0__RAWNAND_D0,
  75         MX6_PAD_NANDF_D1__RAWNAND_D1,
  76         MX6_PAD_NANDF_D2__RAWNAND_D2,
  77         MX6_PAD_NANDF_D3__RAWNAND_D3,
  78         MX6_PAD_NANDF_D4__RAWNAND_D4,
  79         MX6_PAD_NANDF_D5__RAWNAND_D5,
  80         MX6_PAD_NANDF_D6__RAWNAND_D6,
  81         MX6_PAD_NANDF_D7__RAWNAND_D7,
  82
  83         /* RESET_OUT */
  84         MX6_PAD_GPIO_17__GPIO_7_12,
  85
  86         /* UART pads */
  87 #if CONFIG_MXC_UART_BASE == UART1_BASE
  88         MX6_PAD_SD3_DAT7__UART1_TXD,
  89         MX6_PAD_SD3_DAT6__UART1_RXD,
  90         MX6_PAD_SD3_DAT1__UART1_RTS,
  91         MX6_PAD_SD3_DAT0__UART1_CTS,
  92 #endif
  93 #if CONFIG_MXC_UART_BASE == UART2_BASE
  94         MX6_PAD_SD4_DAT4__UART2_RXD,
  95         MX6_PAD_SD4_DAT7__UART2_TXD,
  96         MX6_PAD_SD4_DAT5__UART2_RTS,
  97         MX6_PAD_SD4_DAT6__UART2_CTS,
  98 #endif
  99 #if CONFIG_MXC_UART_BASE == UART3_BASE
 100         MX6_PAD_EIM_D24__UART3_TXD,
 101         MX6_PAD_EIM_D25__UART3_RXD,
 102         MX6_PAD_SD3_RST__UART3_RTS,
 103         MX6_PAD_SD3_DAT3__UART3_CTS,
 104 #endif
 105         /* internal I2C */
 106         MX6_PAD_EIM_D28__I2C1_SDA,
 107         MX6_PAD_EIM_D21__I2C1_SCL,
 108
 109         /* FEC PHY GPIO functions */
 110         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
 111         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
 112         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
 113 };
 114
 115 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
 116         /* FEC functions */
 117         MX6_PAD_ENET_MDC__ENET_MDC,
 118         MX6_PAD_ENET_MDIO__ENET_MDIO,
 119         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
 120         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 121         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 122         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
 123         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
 124         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 125         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
 126         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
 127 };
 128
 129 static const struct gpio tx6qdl_gpios[] = {
 130         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 131         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 132         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 133         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 134 };
 135
 136 /*
 137  * Functions
 138  */
 139 /* placed in section '.data' to prevent overwriting relocation info
 140  * overlayed with bss
 141  */
 142 static u32 wrsr __attribute__((section(".data")));
 143
 144 #define WRSR_POR                        (1 << 4)
 145 #define WRSR_TOUT                       (1 << 1)
 146 #define WRSR_SFTW                       (1 << 0)
 147
 148 static void print_reset_cause(void)
 149 {
 150         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 151         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 152         u32 srsr;
 153         char *dlm = "";
 154
 155         printf("Reset cause: ");
 156
 157         srsr = readl(&src_regs->srsr);
 158         wrsr = readw(wdt_base + 4);
 159
 160         if (wrsr & WRSR_POR) {
 161                 printf("%sPOR", dlm);
 162                 dlm = " | ";
 163         }
 164         if (srsr & 0x00004) {
 165                 printf("%sCSU", dlm);
 166                 dlm = " | ";
 167         }
 168         if (srsr & 0x00008) {
 169                 printf("%sIPP USER", dlm);
 170                 dlm = " | ";
 171         }
 172         if (srsr & 0x00010) {
 173                 if (wrsr & WRSR_SFTW) {
 174                         printf("%sSOFT", dlm);
 175                         dlm = " | ";
 176                 }
 177                 if (wrsr & WRSR_TOUT) {
 178                         printf("%sWDOG", dlm);
 179                         dlm = " | ";
 180                 }
 181         }
 182         if (srsr & 0x00020) {
 183                 printf("%sJTAG HIGH-Z", dlm);
 184                 dlm = " | ";
 185         }
 186         if (srsr & 0x00040) {
 187                 printf("%sJTAG SW", dlm);
 188                 dlm = " | ";
 189         }
 190         if (srsr & 0x10000) {
 191                 printf("%sWARM BOOT", dlm);
 192                 dlm = " | ";
 193         }
 194         if (dlm[0] == '\0')
 195                 printf("unknown");
 196
 197         printf("\n");
 198 }
 199
 200 int read_cpu_temperature(void);
 201 int check_cpu_temperature(int boot);
 202
 203 static void print_cpuinfo(void)
 204 {
 205         u32 cpurev = get_cpu_rev();
 206         char *cpu_str = "?";
 207
 208         switch ((cpurev >> 12) & 0xff) {
 209         case MXC_CPU_MX6SL:
 210                 cpu_str = "SL";
 211                 break;
 212         case MXC_CPU_MX6DL:
 213                 cpu_str = "DL";
 214                 break;
 215         case MXC_CPU_MX6SOLO:
 216                 cpu_str = "SOLO";
 217                 break;
 218         case MXC_CPU_MX6Q:
 219                 cpu_str = "Q";
 220                 break;
 221         }
 222
 223         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 224                 cpu_str,
 225                 (cpurev & 0x000F0) >> 4,
 226                 (cpurev & 0x0000F) >> 0,
 227                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 228
 229         print_reset_cause();
 230         check_cpu_temperature(1);
 231 }
 232
 233 #define LTC3676_DVB2A           0x0C
 234 #define LTC3676_DVB2B           0x0D
 235 #define LTC3676_DVB4A           0x10
 236 #define LTC3676_DVB4B           0x11
 237
 238 #define VDD_SOC_mV              (1375 + 50)
 239 #define VDD_CORE_mV             (1375 + 50)
 240
 241 #define mV_to_regval(mV)        (((mV) * 360 / 330 - 825 + 1) / 25)
 242 #define regval_to_mV(v)         (((v) * 25 + 825) * 330 / 360)
 243
 244 static int setup_pmic_voltages(void)
 245 {
 246         int ret;
 247         unsigned char value;
 248
 249         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 250
 251         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 252         if (ret != 0) {
 253                 printf("Failed to initialize I2C\n");
 254                 return ret;
 255         }
 256
 257         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 258         if (ret) {
 259                 printf("%s: i2c_read error: %d\n", __func__, ret);
 260                 return ret;
 261         }
 262
 263         /* VDDCORE/VDDSOC default 1.375V is not enough, considering
 264            pfuze tolerance and IR drop and ripple, need increase
 265            to 1.425V for SabreSD */
 266
 267         value = 0x39; /* VB default value & PGOOD not forced when slewing */
 268         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
 269         if (ret) {
 270                 printf("%s: failed to write PMIC DVB2B register: %d\n",
 271                         __func__, ret);
 272                 return ret;
 273         }
 274         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
 275         if (ret) {
 276                 printf("%s: failed to write PMIC DVB4B register: %d\n",
 277                         __func__, ret);
 278                 return ret;
 279         }
 280
 281         value = mV_to_regval(VDD_SOC_mV);
 282         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
 283         if (ret) {
 284                 printf("%s: failed to write PMIC DVB2A register: %d\n",
 285                         __func__, ret);
 286                 return ret;
 287         }
 288         printf("VDDSOC  set to %dmV\n", regval_to_mV(value));
 289
 290         value = mV_to_regval(VDD_CORE_mV);
 291         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
 292         if (ret) {
 293                 printf("%s: failed to write PMIC DVB4A register: %d\n",
 294                         __func__, ret);
 295                 return ret;
 296         }
 297         printf("VDDCORE set to %dmV\n", regval_to_mV(value));
 298         return 0;
 299 }
 300
 301 int board_early_init_f(void)
 302 {
 303         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 304         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 305
 306         return 0;
 307 }
 308
 309 int board_init(void)
 310 {
 311         int ret;
 312
 313         /* Address of boot parameters */
 314         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 315 #ifdef CONFIG_OF_LIBFDT
 316         gd->bd->bi_arch_number = -1;
 317 #else
 318         gd->bd->bi_arch_number = 4429;
 319 #endif
 320         ret = setup_pmic_voltages();
 321         if (ret) {
 322                 printf("Failed to setup PMIC voltages\n");
 323                 hang();
 324         }
 325         return 0;
 326 }
 327
 328 int dram_init(void)
 329 {
 330         /* dram_init must store complete ramsize in gd->ram_size */
 331         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 332                                 PHYS_SDRAM_1_SIZE);
 333         return 0;
 334 }
 335
 336 void dram_init_banksize(void)
 337 {
 338         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 339         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 340                         PHYS_SDRAM_1_SIZE);
 341 #if CONFIG_NR_DRAM_BANKS > 1
 342         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 343         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 344                         PHYS_SDRAM_2_SIZE);
 345 #endif
 346 }
 347
 348 #ifdef  CONFIG_CMD_MMC
 349 static const iomux_v3_cfg_t mmc0_pads[] = {
 350         MX6_PAD_SD1_CMD__USDHC1_CMD,
 351         MX6_PAD_SD1_CLK__USDHC1_CLK,
 352         MX6_PAD_SD1_DAT0__USDHC1_DAT0,
 353         MX6_PAD_SD1_DAT1__USDHC1_DAT1,
 354         MX6_PAD_SD1_DAT2__USDHC1_DAT2,
 355         MX6_PAD_SD1_DAT3__USDHC1_DAT3,
 356         /* SD1 CD */
 357         MX6_PAD_SD3_CMD__GPIO_7_2,
 358 };
 359
 360 static const iomux_v3_cfg_t mmc1_pads[] = {
 361         MX6_PAD_SD2_CMD__USDHC2_CMD,
 362         MX6_PAD_SD2_CLK__USDHC2_CLK,
 363         MX6_PAD_SD2_DAT0__USDHC2_DAT0,
 364         MX6_PAD_SD2_DAT1__USDHC2_DAT1,
 365         MX6_PAD_SD2_DAT2__USDHC2_DAT2,
 366         MX6_PAD_SD2_DAT3__USDHC2_DAT3,
 367         /* SD2 CD */
 368         MX6_PAD_SD3_CLK__GPIO_7_3,
 369 };
 370
 371 static struct tx6q_esdhc_cfg {
 372         const iomux_v3_cfg_t *pads;
 373         int num_pads;
 374         enum mxc_clock clkid;
 375         struct fsl_esdhc_cfg cfg;
 376 } tx6qdl_esdhc_cfg[] = {
 377         {
 378                 .pads = mmc0_pads,
 379                 .num_pads = ARRAY_SIZE(mmc0_pads),
 380                 .clkid = MXC_ESDHC_CLK,
 381                 .cfg = {
 382                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 383                         .cd_gpio = IMX_GPIO_NR(7, 2),
 384                         .wp_gpio = -EINVAL,
 385                 },
 386         },
 387         {
 388                 .pads = mmc1_pads,
 389                 .num_pads = ARRAY_SIZE(mmc1_pads),
 390                 .clkid = MXC_ESDHC2_CLK,
 391                 .cfg = {
 392                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 393                         .cd_gpio = IMX_GPIO_NR(7, 3),
 394                         .wp_gpio = -EINVAL,
 395                 },
 396         },
 397 };
 398
 399 static inline struct tx6q_esdhc_cfg *to_tx6q_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 400 {
 401         void *p = cfg;
 402
 403         return p - offsetof(struct tx6q_esdhc_cfg, cfg);
 404 }
 405
 406 int board_mmc_getcd(struct mmc *mmc)
 407 {
 408         struct fsl_esdhc_cfg *cfg = mmc->priv;
 409
 410         if (cfg->cd_gpio < 0)
 411                 return cfg->cd_gpio;
 412
 413         debug("SD card %d is %spresent\n",
 414                 to_tx6q_esdhc_cfg(cfg) - tx6qdl_esdhc_cfg,
 415                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 416         return !gpio_get_value(cfg->cd_gpio);
 417 }
 418
 419 int board_mmc_init(bd_t *bis)
 420 {
 421         int i;
 422
 423         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 424                 struct mmc *mmc;
 425                 struct fsl_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i].cfg;
 426
 427                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 428                         break;
 429
 430                 cfg->sdhc_clk = mxc_get_clock(tx6qdl_esdhc_cfg[i].clkid);
 431                 imx_iomux_v3_setup_multiple_pads(tx6qdl_esdhc_cfg[i].pads,
 432                                                 tx6qdl_esdhc_cfg[i].num_pads);
 433
 434                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 435                 fsl_esdhc_initialize(bis, cfg);
 436
 437                 mmc = find_mmc_device(i);
 438                 if (mmc == NULL)
 439                         continue;
 440                 if (board_mmc_getcd(mmc) > 0)
 441                         mmc_init(mmc);
 442         }
 443         return 0;
 444 }
 445 #endif /* CONFIG_CMD_MMC */
 446
 447 #ifdef CONFIG_FEC_MXC
 448
 449 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 450                         PAD_CTL_SRE_FAST)
 451 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 452 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 453
 454 #ifndef ETH_ALEN
 455 #define ETH_ALEN 6
 456 #endif
 457
 458 int board_eth_init(bd_t *bis)
 459 {
 460         int ret;
 461
 462         /* delay at least 21ms for the PHY internal POR signal to deassert */
 463         udelay(22000);
 464
 465         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
 466
 467         /* Deassert RESET to the external phy */
 468         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 469
 470         ret = cpu_eth_init(bis);
 471         if (ret)
 472                 printf("cpu_eth_init() failed: %d\n", ret);
 473
 474         return ret;
 475 }
 476 #endif /* CONFIG_FEC_MXC */
 477
 478 enum {
 479         LED_STATE_INIT = -1,
 480         LED_STATE_OFF,
 481         LED_STATE_ON,
 482 };
 483
 484 static inline int calc_blink_rate(int tmp)
 485 {
 486         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 487                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 488                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 489 }
 490
 491 void show_activity(int arg)
 492 {
 493         static int led_state = LED_STATE_INIT;
 494         static int blink_rate;
 495         static ulong last;
 496
 497         if (led_state == LED_STATE_INIT) {
 498                 last = get_timer(0);
 499                 gpio_set_value(TX6_LED_GPIO, 1);
 500                 led_state = LED_STATE_ON;
 501                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
 502         } else {
 503                 if (get_timer(last) > blink_rate) {
 504                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
 505                         last = get_timer_masked();
 506                         if (led_state == LED_STATE_ON) {
 507                                 gpio_set_value(TX6_LED_GPIO, 0);
 508                         } else {
 509                                 gpio_set_value(TX6_LED_GPIO, 1);
 510                         }
 511                         led_state = 1 - led_state;
 512                 }
 513         }
 514 }
 515
 516 static const iomux_v3_cfg_t stk5_pads[] = {
 517         /* SW controlled LED on STK5 baseboard */
 518         MX6_PAD_EIM_A18__GPIO_2_20,
 519
 520         /* LCD data pins */
 521         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 522         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 523         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 524         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 525         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 526         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 527         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 528         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 529         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 530         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 531         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 532         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 533         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 534         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 535         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 536         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 537         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 538         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 539         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 540         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 541         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 542         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 543         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 544         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 545         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
 546         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
 547         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 548         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 549
 550         /* I2C bus on DIMM pins 40/41 */
 551         MX6_PAD_GPIO_6__I2C3_SDA,
 552         MX6_PAD_GPIO_3__I2C3_SCL,
 553
 554         /* TSC200x PEN IRQ */
 555         MX6_PAD_EIM_D26__GPIO_3_26,
 556
 557         /* EDT-FT5x06 Polytouch panel */
 558         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
 559         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
 560         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
 561
 562         /* USBH1 */
 563         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
 564         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
 565         /* USBOTG */
 566         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
 567         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
 568         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
 569 };
 570
 571 static const struct gpio stk5_gpios[] = {
 572         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 573
 574         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
 575         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 576         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 577         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 578         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 579 };
 580
 581 #ifdef CONFIG_LCD
 582 vidinfo_t panel_info = {
 583         /* set to max. size supported by SoC */
 584         .vl_col = 1920,
 585         .vl_row = 1080,
 586
 587         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 588 };
 589
 590 static struct fb_videomode tx6_fb_modes[] = {
 591         {
 592                 /* Standard VGA timing */
 593                 .name           = "VGA",
 594                 .refresh        = 60,
 595                 .xres           = 640,
 596                 .yres           = 480,
 597                 .pixclock       = KHZ2PICOS(25175),
 598                 .left_margin    = 48,
 599                 .hsync_len      = 96,
 600                 .right_margin   = 16,
 601                 .upper_margin   = 31,
 602                 .vsync_len      = 2,
 603                 .lower_margin   = 12,
 604                 .sync           = FB_SYNC_CLK_LAT_FALL,
 605         },
 606         {
 607                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 608                  * DE high active, 115.2 mm x 86.4 mm display area
 609                  * VGA compatible timing
 610                  */
 611                 .name           = "ETV570",
 612                 .refresh        = 60,
 613                 .xres           = 640,
 614                 .yres           = 480,
 615                 .pixclock       = KHZ2PICOS(25175),
 616                 .left_margin    = 114,
 617                 .hsync_len      = 30,
 618                 .right_margin   = 16,
 619                 .upper_margin   = 32,
 620                 .vsync_len      = 3,
 621                 .lower_margin   = 10,
 622                 .sync           = FB_SYNC_CLK_LAT_FALL,
 623         },
 624         {
 625                 /* Emerging ET0350G0DH6 320 x 240 display.
 626                  * 70.08 mm x 52.56 mm display area.
 627                  */
 628                 .name           = "ET0350",
 629                 .refresh        = 60,
 630                 .xres           = 320,
 631                 .yres           = 240,
 632                 .pixclock       = KHZ2PICOS(6500),
 633                 .left_margin    = 68 - 34,
 634                 .hsync_len      = 34,
 635                 .right_margin   = 20,
 636                 .upper_margin   = 18 - 3,
 637                 .vsync_len      = 3,
 638                 .lower_margin   = 4,
 639                 .sync           = FB_SYNC_CLK_LAT_FALL,
 640         },
 641         {
 642                 /* Emerging ET0430G0DH6 480 x 272 display.
 643                  * 95.04 mm x 53.856 mm display area.
 644                  */
 645                 .name           = "ET0430",
 646                 .refresh        = 60,
 647                 .xres           = 480,
 648                 .yres           = 272,
 649                 .pixclock       = KHZ2PICOS(9000),
 650                 .left_margin    = 2,
 651                 .hsync_len      = 41,
 652                 .right_margin   = 2,
 653                 .upper_margin   = 2,
 654                 .vsync_len      = 10,
 655                 .lower_margin   = 2,
 656                 .sync           = FB_SYNC_CLK_LAT_FALL,
 657         },
 658         {
 659                 /* Emerging ET0500G0DH6 800 x 480 display.
 660                  * 109.6 mm x 66.4 mm display area.
 661                  */
 662                 .name           = "ET0500",
 663                 .refresh        = 60,
 664                 .xres           = 800,
 665                 .yres           = 480,
 666                 .pixclock       = KHZ2PICOS(33260),
 667                 .left_margin    = 216 - 128,
 668                 .hsync_len      = 128,
 669                 .right_margin   = 1056 - 800 - 216,
 670                 .upper_margin   = 35 - 2,
 671                 .vsync_len      = 2,
 672                 .lower_margin   = 525 - 480 - 35,
 673                 .sync           = FB_SYNC_CLK_LAT_FALL,
 674         },
 675         {
 676                 /* Emerging ETQ570G0DH6 320 x 240 display.
 677                  * 115.2 mm x 86.4 mm display area.
 678                  */
 679                 .name           = "ETQ570",
 680                 .refresh        = 60,
 681                 .xres           = 320,
 682                 .yres           = 240,
 683                 .pixclock       = KHZ2PICOS(6400),
 684                 .left_margin    = 38,
 685                 .hsync_len      = 30,
 686                 .right_margin   = 30,
 687                 .upper_margin   = 16, /* 15 according to datasheet */
 688                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 689                 .lower_margin   = 4, /* 4.5 according to datasheet */
 690                 .sync           = FB_SYNC_CLK_LAT_FALL,
 691         },
 692         {
 693                 /* Emerging ET0700G0DH6 800 x 480 display.
 694                  * 152.4 mm x 91.44 mm display area.
 695                  */
 696                 .name           = "ET0700",
 697                 .refresh        = 60,
 698                 .xres           = 800,
 699                 .yres           = 480,
 700                 .pixclock       = KHZ2PICOS(33260),
 701                 .left_margin    = 216 - 128,
 702                 .hsync_len      = 128,
 703                 .right_margin   = 1056 - 800 - 216,
 704                 .upper_margin   = 35 - 2,
 705                 .vsync_len      = 2,
 706                 .lower_margin   = 525 - 480 - 35,
 707                 .sync           = FB_SYNC_CLK_LAT_FALL,
 708         },
 709         {
 710                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 711                 .refresh        = 60,
 712                 .left_margin    = 48,
 713                 .hsync_len      = 96,
 714                 .right_margin   = 16,
 715                 .upper_margin   = 31,
 716                 .vsync_len      = 2,
 717                 .lower_margin   = 12,
 718                 .sync           = FB_SYNC_CLK_LAT_FALL,
 719         },
 720 };
 721
 722 static int lcd_enabled = 1;
 723
 724 void lcd_enable(void)
 725 {
 726         /* HACK ALERT:
 727          * global variable from common/lcd.c
 728          * Set to 0 here to prevent messages from going to LCD
 729          * rather than serial console
 730          */
 731         lcd_is_enabled = 0;
 732
 733         karo_load_splashimage(1);
 734         if (lcd_enabled) {
 735                 debug("Switching LCD on\n");
 736                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 737                 udelay(100);
 738                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 739                 udelay(300000);
 740                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
 741         }
 742 }
 743
 744 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 745         /* LCD RESET */
 746         MX6_PAD_EIM_D29__GPIO_3_29,
 747         /* LCD POWER_ENABLE */
 748         MX6_PAD_EIM_EB3__GPIO_2_31,
 749         /* LCD Backlight (PWM) */
 750         MX6_PAD_GPIO_1__GPIO_1_1,
 751
 752         /* Display */
 753         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 754         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 755         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 756         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 757         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 758         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 759         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 760         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 761         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 762         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 763         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 764         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 765         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 766         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 767         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 768         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 769         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 770         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 771         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 772         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 773         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 774         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 775         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 776         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 777         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 778         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 779         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 780         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 781 };
 782
 783 static const struct gpio stk5_lcd_gpios[] = {
 784         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 785         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 786         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 787 };
 788
 789 void lcd_ctrl_init(void *lcdbase)
 790 {
 791         int color_depth = 24;
 792         char *vm;
 793         unsigned long val;
 794         int refresh = 60;
 795         struct fb_videomode *p = &tx6_fb_modes[0];
 796         struct fb_videomode fb_mode;
 797         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 798         int pix_fmt = 0;
 799         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 800         unsigned long di_clk_rate = 65000000;
 801
 802         if (!lcd_enabled) {
 803                 debug("LCD disabled\n");
 804                 return;
 805         }
 806
 807         if (tstc() || (wrsr & WRSR_TOUT)) {
 808                 debug("Disabling LCD\n");
 809                 lcd_enabled = 0;
 810                 return;
 811         }
 812
 813         karo_fdt_move_fdt();
 814
 815         vm = getenv("video_mode");
 816         if (vm == NULL) {
 817                 debug("Disabling LCD\n");
 818                 lcd_enabled = 0;
 819                 return;
 820         }
 821         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 822                 p = &fb_mode;
 823                 debug("Using video mode from FDT\n");
 824                 vm += strlen(vm);
 825                 if (fb_mode.xres < panel_info.vl_col)
 826                         panel_info.vl_col = fb_mode.xres;
 827                 if (fb_mode.yres < panel_info.vl_row)
 828                         panel_info.vl_row = fb_mode.yres;
 829         }
 830         if (p->name != NULL)
 831                 debug("Trying compiled-in video modes\n");
 832         while (p->name != NULL) {
 833                 if (strcmp(p->name, vm) == 0) {
 834                         debug("Using video mode: '%s'\n", p->name);
 835                         vm += strlen(vm);
 836                         break;
 837                 }
 838                 p++;
 839         }
 840         if (*vm != '\0')
 841                 debug("Trying to decode video_mode: '%s'\n", vm);
 842         while (*vm != '\0') {
 843                 if (*vm >= '0' && *vm <= '9') {
 844                         char *end;
 845
 846                         val = simple_strtoul(vm, &end, 0);
 847                         if (end > vm) {
 848                                 if (!xres_set) {
 849                                         if (val > panel_info.vl_col)
 850                                                 val = panel_info.vl_col;
 851                                         p->xres = val;
 852                                         panel_info.vl_col = val;
 853                                         xres_set = 1;
 854                                 } else if (!yres_set) {
 855                                         if (val > panel_info.vl_row)
 856                                                 val = panel_info.vl_row;
 857                                         p->yres = val;
 858                                         panel_info.vl_row = val;
 859                                         yres_set = 1;
 860                                 } else if (!bpp_set) {
 861                                         switch (val) {
 862                                         case 24:
 863                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 864                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 865                                                 /* fallthru */
 866                                         case 16:
 867                                         case 8:
 868                                                 color_depth = val;
 869                                                 break;
 870
 871                                         case 18:
 872                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 873                                                         color_depth = val;
 874                                                         break;
 875                                                 }
 876                                                 /* fallthru */
 877                                         default:
 878                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 879                                                         end - vm, vm, color_depth);
 880                                         }
 881                                         bpp_set = 1;
 882                                 } else if (!refresh_set) {
 883                                         refresh = val;
 884                                         refresh_set = 1;
 885                                 }
 886                         }
 887                         vm = end;
 888                 }
 889                 switch (*vm) {
 890                 case '@':
 891                         bpp_set = 1;
 892                         /* fallthru */
 893                 case '-':
 894                         yres_set = 1;
 895                         /* fallthru */
 896                 case 'x':
 897                         xres_set = 1;
 898                         /* fallthru */
 899                 case 'M':
 900                 case 'R':
 901                         vm++;
 902                         break;
 903
 904                 default:
 905                         if (!pix_fmt) {
 906                                 char *tmp;
 907
 908                                 if (strncmp(vm, "LVDS", 4) == 0) {
 909                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 910                                         di_clk_parent = DI_PCLK_LDB;
 911                                 } else {
 912                                         pix_fmt = IPU_PIX_FMT_RGB24;
 913                                 }
 914                                 tmp = strchr(vm, ':');
 915                                 if (tmp)
 916                                         vm = tmp;
 917                         }
 918                         if (*vm != '\0')
 919                                 vm++;
 920                 }
 921         }
 922         if (p->xres == 0 || p->yres == 0) {
 923                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 924                 lcd_enabled = 0;
 925                 printf("Supported video modes are:");
 926                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
 927                         printf(" %s", p->name);
 928                 }
 929                 printf("\n");
 930                 return;
 931         }
 932
 933         p->pixclock = KHZ2PICOS(refresh *
 934                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 935                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 936                 / 1000);
 937         debug("Pixel clock set to %lu.%03lu MHz\n",
 938                 PICOS2KHZ(p->pixclock) / 1000,
 939                 PICOS2KHZ(p->pixclock) % 1000);
 940
 941         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 942         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 943                                         ARRAY_SIZE(stk5_lcd_pads));
 944
 945         debug("Initializing FB driver\n");
 946         if (!pix_fmt)
 947                 pix_fmt = IPU_PIX_FMT_RGB24;
 948         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 949                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 950         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 951                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 952         }
 953         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 954                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 955                 /* enable LDB & DI0 clock */
 956                 writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2),
 957                         &ccm_regs->CCGR3);
 958         }
 959
 960         if (karo_load_splashimage(0) == 0) {
 961                 debug("Initializing LCD controller\n");
 962                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 963         } else {
 964                 debug("Skipping initialization of LCD controller\n");
 965         }
 966 }
 967 #else
 968 #define lcd_enabled 0
 969 #endif /* CONFIG_LCD */
 970
 971 static void stk5_board_init(void)
 972 {
 973         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 974         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 975 }
 976
 977 static void stk5v3_board_init(void)
 978 {
 979         stk5_board_init();
 980 }
 981
 982 static void stk5v5_board_init(void)
 983 {
 984         stk5_board_init();
 985
 986         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
 987                         "Flexcan Transceiver");
 988         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
 989 }
 990
 991 static void tx6qdl_set_cpu_clock(void)
 992 {
 993         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 994
 995         if (tstc() || (wrsr & WRSR_TOUT))
 996                 return;
 997
 998         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 999                 return;
1000
1001         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1002                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1003                 printf("CPU clock set to %lu.%03lu MHz\n",
1004                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1005         } else {
1006                 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
1007         }
1008 }
1009
1010 static void tx6_init_mac(void)
1011 {
1012         u8 mac[ETH_ALEN];
1013         char mac_str[ETH_ALEN * 3] = "";
1014
1015         imx_get_mac_from_fuse(-1, mac);
1016         if (!is_valid_ether_addr(mac)) {
1017                 printf("No valid MAC address programmed\n");
1018                 return;
1019         }
1020
1021         snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
1022                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1023         setenv("ethaddr", mac_str);
1024         printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n",
1025                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1026 }
1027
1028 int board_late_init(void)
1029 {
1030         int ret = 0;
1031         const char *baseboard;
1032
1033         tx6qdl_set_cpu_clock();
1034         karo_fdt_move_fdt();
1035
1036         baseboard = getenv("baseboard");
1037         if (!baseboard)
1038                 goto exit;
1039
1040         printf("Baseboard: %s\n", baseboard);
1041
1042         if (strncmp(baseboard, "stk5", 4) == 0) {
1043                 if ((strlen(baseboard) == 4) ||
1044                         strcmp(baseboard, "stk5-v3") == 0) {
1045                         stk5v3_board_init();
1046                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1047                         stk5v5_board_init();
1048                 } else {
1049                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1050                                 baseboard + 4);
1051                 }
1052         } else {
1053                 printf("WARNING: Unsupported baseboard: '%s'\n",
1054                         baseboard);
1055                 ret = -EINVAL;
1056         }
1057
1058 exit:
1059         tx6_init_mac();
1060
1061         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1062         return ret;
1063 }
1064
1065 int checkboard(void)
1066 {
1067         u32 cpurev = get_cpu_rev();
1068         int cpu_variant = (cpurev >> 12) & 0xff;
1069
1070         print_cpuinfo();
1071
1072         printf("Board: Ka-Ro TX6%c-%dxx%d\n",
1073                 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1074                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1075                 1 - PHYS_SDRAM_1_WIDTH / 64);
1076
1077         return 0;
1078 }
1079
1080 #ifdef CONFIG_SERIAL_TAG
1081 void get_board_serial(struct tag_serialnr *serialnr)
1082 {
1083         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
1084         struct fuse_bank0_regs *fuse = (void *)iim->bank[0].fuse_regs;
1085
1086         serialnr->low = readl(&fuse->cfg0);
1087         serialnr->high = readl(&fuse->cfg1);
1088 }
1089 #endif
1090
1091 #if defined(CONFIG_OF_BOARD_SETUP)
1092 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1093 #include <jffs2/jffs2.h>
1094 #include <mtd_node.h>
1095 struct node_info nodes[] = {
1096         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1097 };
1098
1099 #else
1100 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1101 #endif
1102
1103 static void tx6qdl_fixup_flexcan(void *blob)
1104 {
1105         const char *baseboard = getenv("baseboard");
1106
1107         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1108                 return;
1109
1110         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch");
1111         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch");
1112 }
1113
1114 void ft_board_setup(void *blob, bd_t *bd)
1115 {
1116         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1117         fdt_fixup_ethernet(blob);
1118
1119         karo_fdt_fixup_touchpanel(blob);
1120         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1121         tx6qdl_fixup_flexcan(blob);
1122         karo_fdt_update_fb_mode(blob, getenv("video_mode"));
1123 }
1124 #endif