board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17 #include <common.h>
  18 #include <errno.h>
  19 #include <libfdt.h>
  20 #include <fdt_support.h>
  21 #include <lcd.h>
  22 #include <netdev.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <video_fb.h>
  26 #include <ipu.h>
  27 #include <mxcfb.h>
  28 #include <i2c.h>
  29 #include <linux/fb.h>
  30 #include <asm/io.h>
  31 #include <asm/gpio.h>
  32 #include <asm/arch/mx6-pins.h>
  33 #include <asm/arch/clock.h>
  34 #include <asm/arch/imx-regs.h>
  35 #include <asm/arch/crm_regs.h>
  36 #include <asm/arch/sys_proto.h>
  37
  38 #include "../common/karo.h"
  39 #include "pmic.h"
  40
  41 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  42 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  43 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  44 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  45
  46 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  47 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  48 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  49
  50 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  51
  52 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  53 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  54 #else
  55 #define TEMPERATURE_MIN                 (-40)
  56 #endif
  57 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  58 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  59 #else
  60 #define TEMPERATURE_HOT                 80
  61 #endif
  62
  63 DECLARE_GLOBAL_DATA_PTR;
  64
  65 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  66
  67 static const iomux_v3_cfg_t tx6qdl_pads[] = {
  68 #ifndef CONFIG_NO_NAND
  69         /* NAND flash pads */
  70         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
  71         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
  72         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
  73         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
  74         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
  75         MX6_PAD_SD4_CMD__RAWNAND_RDN,
  76         MX6_PAD_SD4_CLK__RAWNAND_WRN,
  77         MX6_PAD_NANDF_D0__RAWNAND_D0,
  78         MX6_PAD_NANDF_D1__RAWNAND_D1,
  79         MX6_PAD_NANDF_D2__RAWNAND_D2,
  80         MX6_PAD_NANDF_D3__RAWNAND_D3,
  81         MX6_PAD_NANDF_D4__RAWNAND_D4,
  82         MX6_PAD_NANDF_D5__RAWNAND_D5,
  83         MX6_PAD_NANDF_D6__RAWNAND_D6,
  84         MX6_PAD_NANDF_D7__RAWNAND_D7,
  85 #endif
  86         /* RESET_OUT */
  87         MX6_PAD_GPIO_17__GPIO_7_12,
  88
  89         /* UART pads */
  90 #if CONFIG_MXC_UART_BASE == UART1_BASE
  91         MX6_PAD_SD3_DAT7__UART1_TXD,
  92         MX6_PAD_SD3_DAT6__UART1_RXD,
  93         MX6_PAD_SD3_DAT1__UART1_RTS,
  94         MX6_PAD_SD3_DAT0__UART1_CTS,
  95 #endif
  96 #if CONFIG_MXC_UART_BASE == UART2_BASE
  97         MX6_PAD_SD4_DAT4__UART2_RXD,
  98         MX6_PAD_SD4_DAT7__UART2_TXD,
  99         MX6_PAD_SD4_DAT5__UART2_RTS,
 100         MX6_PAD_SD4_DAT6__UART2_CTS,
 101 #endif
 102 #if CONFIG_MXC_UART_BASE == UART3_BASE
 103         MX6_PAD_EIM_D24__UART3_TXD,
 104         MX6_PAD_EIM_D25__UART3_RXD,
 105         MX6_PAD_SD3_RST__UART3_RTS,
 106         MX6_PAD_SD3_DAT3__UART3_CTS,
 107 #endif
 108         /* internal I2C */
 109         MX6_PAD_EIM_D28__I2C1_SDA,
 110         MX6_PAD_EIM_D21__I2C1_SCL,
 111
 112         /* FEC PHY GPIO functions */
 113         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
 114         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
 115         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
 116 };
 117
 118 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
 119         /* FEC functions */
 120         MX6_PAD_ENET_MDC__ENET_MDC,
 121         MX6_PAD_ENET_MDIO__ENET_MDIO,
 122         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
 123         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 124         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 125         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
 126         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
 127         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 128         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
 129         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
 130 };
 131
 132 static const struct gpio tx6qdl_gpios[] = {
 133         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 134         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 135         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 136         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 137 };
 138
 139 /*
 140  * Functions
 141  */
 142 /* placed in section '.data' to prevent overwriting relocation info
 143  * overlayed with bss
 144  */
 145 static u32 wrsr __attribute__((section(".data")));
 146
 147 #define WRSR_POR                        (1 << 4)
 148 #define WRSR_TOUT                       (1 << 1)
 149 #define WRSR_SFTW                       (1 << 0)
 150
 151 static void print_reset_cause(void)
 152 {
 153         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 154         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 155         u32 srsr;
 156         char *dlm = "";
 157
 158         printf("Reset cause: ");
 159
 160         srsr = readl(&src_regs->srsr);
 161         wrsr = readw(wdt_base + 4);
 162
 163         if (wrsr & WRSR_POR) {
 164                 printf("%sPOR", dlm);
 165                 dlm = " | ";
 166         }
 167         if (srsr & 0x00004) {
 168                 printf("%sCSU", dlm);
 169                 dlm = " | ";
 170         }
 171         if (srsr & 0x00008) {
 172                 printf("%sIPP USER", dlm);
 173                 dlm = " | ";
 174         }
 175         if (srsr & 0x00010) {
 176                 if (wrsr & WRSR_SFTW) {
 177                         printf("%sSOFT", dlm);
 178                         dlm = " | ";
 179                 }
 180                 if (wrsr & WRSR_TOUT) {
 181                         printf("%sWDOG", dlm);
 182                         dlm = " | ";
 183                 }
 184         }
 185         if (srsr & 0x00020) {
 186                 printf("%sJTAG HIGH-Z", dlm);
 187                 dlm = " | ";
 188         }
 189         if (srsr & 0x00040) {
 190                 printf("%sJTAG SW", dlm);
 191                 dlm = " | ";
 192         }
 193         if (srsr & 0x10000) {
 194                 printf("%sWARM BOOT", dlm);
 195                 dlm = " | ";
 196         }
 197         if (dlm[0] == '\0')
 198                 printf("unknown");
 199
 200         printf("\n");
 201 }
 202
 203 static const char *tx6_mod_suffix;
 204
 205 static void tx6qdl_print_cpuinfo(void)
 206 {
 207         u32 cpurev = get_cpu_rev();
 208         char *cpu_str = "?";
 209
 210         switch ((cpurev >> 12) & 0xff) {
 211         case MXC_CPU_MX6SL:
 212                 cpu_str = "SL";
 213                 tx6_mod_suffix = "?";
 214                 break;
 215         case MXC_CPU_MX6DL:
 216                 cpu_str = "DL";
 217                 tx6_mod_suffix = "U";
 218                 break;
 219         case MXC_CPU_MX6SOLO:
 220                 cpu_str = "SOLO";
 221                 tx6_mod_suffix = "S";
 222                 break;
 223         case MXC_CPU_MX6Q:
 224                 cpu_str = "Q";
 225                 tx6_mod_suffix = "Q";
 226                 break;
 227         }
 228
 229         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 230                 cpu_str,
 231                 (cpurev & 0x000F0) >> 4,
 232                 (cpurev & 0x0000F) >> 0,
 233                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 234
 235         print_reset_cause();
 236 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 237         check_cpu_temperature(1);
 238 #endif
 239 }
 240
 241 int board_early_init_f(void)
 242 {
 243         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 244         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 245
 246         return 0;
 247 }
 248
 249 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 250 static bool tx6_temp_check_enabled = true;
 251 #else
 252 #define tx6_temp_check_enabled  0
 253 #endif
 254
 255 int board_init(void)
 256 {
 257         int ret;
 258
 259         /* Address of boot parameters */
 260         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 261         gd->bd->bi_arch_number = -1;
 262
 263         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 264                 if (wrsr & WRSR_TOUT)
 265                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 266                 else
 267                         printf("<CTRL-C> detected; safeboot enabled\n");
 268 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 269                 tx6_temp_check_enabled = false;
 270 #endif
 271                 return 1;
 272         }
 273
 274         ret = tx6_pmic_init();
 275         if (ret) {
 276                 printf("Failed to setup PMIC voltages\n");
 277                 hang();
 278         }
 279         return 0;
 280 }
 281
 282 int dram_init(void)
 283 {
 284         /* dram_init must store complete ramsize in gd->ram_size */
 285         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 286                                 PHYS_SDRAM_1_SIZE);
 287         return 0;
 288 }
 289
 290 void dram_init_banksize(void)
 291 {
 292         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 293         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 294                         PHYS_SDRAM_1_SIZE);
 295 #if CONFIG_NR_DRAM_BANKS > 1
 296         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 297         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 298                         PHYS_SDRAM_2_SIZE);
 299 #endif
 300 }
 301
 302 #ifdef  CONFIG_CMD_MMC
 303 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
 304         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
 305         PAD_CTL_SRE_FAST)
 306
 307 static const iomux_v3_cfg_t mmc0_pads[] = {
 308         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 309         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 310         MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 311         MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 312         MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 313         MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 314         /* SD1 CD */
 315         MX6_PAD_SD3_CMD__GPIO_7_2,
 316 };
 317
 318 static const iomux_v3_cfg_t mmc1_pads[] = {
 319         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 320         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 321         MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 322         MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 323         MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 324         MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 325         /* SD2 CD */
 326         MX6_PAD_SD3_CLK__GPIO_7_3,
 327 };
 328
 329 #ifdef CONFIG_MMC_BOOT_SIZE
 330 static const iomux_v3_cfg_t mmc3_pads[] = {
 331         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 332         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 333         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 334         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 335         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 336         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 337         /* eMMC RESET */
 338         MX6_PAD_NANDF_ALE__USDHC4_RST,
 339 };
 340 #endif
 341
 342 static struct tx6_esdhc_cfg {
 343         const iomux_v3_cfg_t *pads;
 344         int num_pads;
 345         enum mxc_clock clkid;
 346         struct fsl_esdhc_cfg cfg;
 347         int cd_gpio;
 348 } tx6qdl_esdhc_cfg[] = {
 349 #ifdef CONFIG_MMC_BOOT_SIZE
 350         {
 351                 .pads = mmc3_pads,
 352                 .num_pads = ARRAY_SIZE(mmc3_pads),
 353                 .clkid = MXC_ESDHC4_CLK,
 354                 .cfg = {
 355                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 356                         .max_bus_width = 4,
 357                 },
 358                 .cd_gpio = -EINVAL,
 359         },
 360 #endif
 361         {
 362                 .pads = mmc0_pads,
 363                 .num_pads = ARRAY_SIZE(mmc0_pads),
 364                 .clkid = MXC_ESDHC_CLK,
 365                 .cfg = {
 366                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 367                         .max_bus_width = 4,
 368                 },
 369                 .cd_gpio = IMX_GPIO_NR(7, 2),
 370         },
 371         {
 372                 .pads = mmc1_pads,
 373                 .num_pads = ARRAY_SIZE(mmc1_pads),
 374                 .clkid = MXC_ESDHC2_CLK,
 375                 .cfg = {
 376                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 377                         .max_bus_width = 4,
 378                 },
 379                 .cd_gpio = IMX_GPIO_NR(7, 3),
 380         },
 381 };
 382
 383 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 384 {
 385         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 386 }
 387
 388 int board_mmc_getcd(struct mmc *mmc)
 389 {
 390         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 391
 392         if (cfg->cd_gpio < 0)
 393                 return 1;
 394
 395         debug("SD card %d is %spresent (GPIO %d)\n",
 396                 cfg - tx6qdl_esdhc_cfg,
 397                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 398                 cfg->cd_gpio);
 399         return !gpio_get_value(cfg->cd_gpio);
 400 }
 401
 402 int board_mmc_init(bd_t *bis)
 403 {
 404         int i;
 405
 406         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 407                 struct mmc *mmc;
 408                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 409                 int ret;
 410
 411                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 412                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 413
 414                 if (cfg->cd_gpio >= 0) {
 415                         ret = gpio_request_one(cfg->cd_gpio,
 416                                         GPIOF_INPUT, "MMC CD");
 417                         if (ret) {
 418                                 printf("Error %d requesting GPIO%d_%d\n",
 419                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 420                                 continue;
 421                         }
 422                 }
 423
 424                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 425                 fsl_esdhc_initialize(bis, &cfg->cfg);
 426
 427                 mmc = find_mmc_device(i);
 428                 if (mmc == NULL)
 429                         continue;
 430                 if (board_mmc_getcd(mmc))
 431                         mmc_init(mmc);
 432         }
 433         return 0;
 434 }
 435 #endif /* CONFIG_CMD_MMC */
 436
 437 #ifdef CONFIG_FEC_MXC
 438
 439 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 440                         PAD_CTL_SRE_FAST)
 441 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 442 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 443
 444 #ifndef ETH_ALEN
 445 #define ETH_ALEN 6
 446 #endif
 447
 448 int board_eth_init(bd_t *bis)
 449 {
 450         int ret;
 451
 452         /* delay at least 21ms for the PHY internal POR signal to deassert */
 453         udelay(22000);
 454
 455         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
 456
 457         /* Deassert RESET to the external phy */
 458         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 459
 460         ret = cpu_eth_init(bis);
 461         if (ret)
 462                 printf("cpu_eth_init() failed: %d\n", ret);
 463
 464         return ret;
 465 }
 466 #endif /* CONFIG_FEC_MXC */
 467
 468 enum {
 469         LED_STATE_INIT = -1,
 470         LED_STATE_OFF,
 471         LED_STATE_ON,
 472 };
 473
 474 static inline int calc_blink_rate(void)
 475 {
 476         if (!tx6_temp_check_enabled)
 477                 return CONFIG_SYS_HZ;
 478
 479         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 480                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 481                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 482 }
 483
 484 void show_activity(int arg)
 485 {
 486         static int led_state = LED_STATE_INIT;
 487         static int blink_rate;
 488         static ulong last;
 489
 490         if (led_state == LED_STATE_INIT) {
 491                 last = get_timer(0);
 492                 gpio_set_value(TX6_LED_GPIO, 1);
 493                 led_state = LED_STATE_ON;
 494                 blink_rate = calc_blink_rate();
 495         } else {
 496                 if (get_timer(last) > blink_rate) {
 497                         blink_rate = calc_blink_rate();
 498                         last = get_timer_masked();
 499                         if (led_state == LED_STATE_ON) {
 500                                 gpio_set_value(TX6_LED_GPIO, 0);
 501                         } else {
 502                                 gpio_set_value(TX6_LED_GPIO, 1);
 503                         }
 504                         led_state = 1 - led_state;
 505                 }
 506         }
 507 }
 508
 509 static const iomux_v3_cfg_t stk5_pads[] = {
 510         /* SW controlled LED on STK5 baseboard */
 511         MX6_PAD_EIM_A18__GPIO_2_20,
 512
 513         /* I2C bus on DIMM pins 40/41 */
 514         MX6_PAD_GPIO_6__I2C3_SDA,
 515         MX6_PAD_GPIO_3__I2C3_SCL,
 516
 517         /* TSC200x PEN IRQ */
 518         MX6_PAD_EIM_D26__GPIO_3_26,
 519
 520         /* EDT-FT5x06 Polytouch panel */
 521         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
 522         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
 523         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
 524
 525         /* USBH1 */
 526         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
 527         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
 528         /* USBOTG */
 529         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
 530         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
 531         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
 532 };
 533
 534 static const struct gpio stk5_gpios[] = {
 535         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 536
 537         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
 538         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 539         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 540         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 541         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 542 };
 543
 544 #ifdef CONFIG_LCD
 545 static u16 tx6_cmap[256];
 546 vidinfo_t panel_info = {
 547         /* set to max. size supported by SoC */
 548         .vl_col = 1920,
 549         .vl_row = 1080,
 550
 551         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 552         .cmap = tx6_cmap,
 553 };
 554
 555 static struct fb_videomode tx6_fb_modes[] = {
 556 #ifndef CONFIG_SYS_LVDS_IF
 557         {
 558                 /* Standard VGA timing */
 559                 .name           = "VGA",
 560                 .refresh        = 60,
 561                 .xres           = 640,
 562                 .yres           = 480,
 563                 .pixclock       = KHZ2PICOS(25175),
 564                 .left_margin    = 48,
 565                 .hsync_len      = 96,
 566                 .right_margin   = 16,
 567                 .upper_margin   = 31,
 568                 .vsync_len      = 2,
 569                 .lower_margin   = 12,
 570                 .sync           = FB_SYNC_CLK_LAT_FALL,
 571         },
 572         {
 573                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 574                  * DE high active, 115.2 mm x 86.4 mm display area
 575                  * VGA compatible timing
 576                  */
 577                 .name           = "ETV570",
 578                 .refresh        = 60,
 579                 .xres           = 640,
 580                 .yres           = 480,
 581                 .pixclock       = KHZ2PICOS(25175),
 582                 .left_margin    = 114,
 583                 .hsync_len      = 30,
 584                 .right_margin   = 16,
 585                 .upper_margin   = 32,
 586                 .vsync_len      = 3,
 587                 .lower_margin   = 10,
 588                 .sync           = FB_SYNC_CLK_LAT_FALL,
 589         },
 590         {
 591                 /* Emerging ET0350G0DH6 320 x 240 display.
 592                  * 70.08 mm x 52.56 mm display area.
 593                  */
 594                 .name           = "ET0350",
 595                 .refresh        = 60,
 596                 .xres           = 320,
 597                 .yres           = 240,
 598                 .pixclock       = KHZ2PICOS(6500),
 599                 .left_margin    = 68 - 34,
 600                 .hsync_len      = 34,
 601                 .right_margin   = 20,
 602                 .upper_margin   = 18 - 3,
 603                 .vsync_len      = 3,
 604                 .lower_margin   = 4,
 605                 .sync           = FB_SYNC_CLK_LAT_FALL,
 606         },
 607         {
 608                 /* Emerging ET0430G0DH6 480 x 272 display.
 609                  * 95.04 mm x 53.856 mm display area.
 610                  */
 611                 .name           = "ET0430",
 612                 .refresh        = 60,
 613                 .xres           = 480,
 614                 .yres           = 272,
 615                 .pixclock       = KHZ2PICOS(9000),
 616                 .left_margin    = 2,
 617                 .hsync_len      = 41,
 618                 .right_margin   = 2,
 619                 .upper_margin   = 2,
 620                 .vsync_len      = 10,
 621                 .lower_margin   = 2,
 622                 .sync           = FB_SYNC_CLK_LAT_FALL,
 623         },
 624         {
 625                 /* Emerging ET0500G0DH6 800 x 480 display.
 626                  * 109.6 mm x 66.4 mm display area.
 627                  */
 628                 .name           = "ET0500",
 629                 .refresh        = 60,
 630                 .xres           = 800,
 631                 .yres           = 480,
 632                 .pixclock       = KHZ2PICOS(33260),
 633                 .left_margin    = 216 - 128,
 634                 .hsync_len      = 128,
 635                 .right_margin   = 1056 - 800 - 216,
 636                 .upper_margin   = 35 - 2,
 637                 .vsync_len      = 2,
 638                 .lower_margin   = 525 - 480 - 35,
 639                 .sync           = FB_SYNC_CLK_LAT_FALL,
 640         },
 641         {
 642                 /* Emerging ETQ570G0DH6 320 x 240 display.
 643                  * 115.2 mm x 86.4 mm display area.
 644                  */
 645                 .name           = "ETQ570",
 646                 .refresh        = 60,
 647                 .xres           = 320,
 648                 .yres           = 240,
 649                 .pixclock       = KHZ2PICOS(6400),
 650                 .left_margin    = 38,
 651                 .hsync_len      = 30,
 652                 .right_margin   = 30,
 653                 .upper_margin   = 16, /* 15 according to datasheet */
 654                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 655                 .lower_margin   = 4, /* 4.5 according to datasheet */
 656                 .sync           = FB_SYNC_CLK_LAT_FALL,
 657         },
 658         {
 659                 /* Emerging ET0700G0DH6 800 x 480 display.
 660                  * 152.4 mm x 91.44 mm display area.
 661                  */
 662                 .name           = "ET0700",
 663                 .refresh        = 60,
 664                 .xres           = 800,
 665                 .yres           = 480,
 666                 .pixclock       = KHZ2PICOS(33260),
 667                 .left_margin    = 216 - 128,
 668                 .hsync_len      = 128,
 669                 .right_margin   = 1056 - 800 - 216,
 670                 .upper_margin   = 35 - 2,
 671                 .vsync_len      = 2,
 672                 .lower_margin   = 525 - 480 - 35,
 673                 .sync           = FB_SYNC_CLK_LAT_FALL,
 674         },
 675         {
 676                 /* Emerging ET070001DM6 800 x 480 display.
 677                  * 152.4 mm x 91.44 mm display area.
 678                  */
 679                 .name           = "ET070001DM6",
 680                 .refresh        = 60,
 681                 .xres           = 800,
 682                 .yres           = 480,
 683                 .pixclock       = KHZ2PICOS(33260),
 684                 .left_margin    = 216 - 128,
 685                 .hsync_len      = 128,
 686                 .right_margin   = 1056 - 800 - 216,
 687                 .upper_margin   = 35 - 2,
 688                 .vsync_len      = 2,
 689                 .lower_margin   = 525 - 480 - 35,
 690                 .sync           = 0,
 691         },
 692 #else
 693         {
 694                 /* HannStar HSD100PXN1
 695                  * 202.7m mm x 152.06 mm display area.
 696                  */
 697                 .name           = "HSD100PXN1",
 698                 .refresh        = 60,
 699                 .xres           = 1024,
 700                 .yres           = 768,
 701                 .pixclock       = KHZ2PICOS(65000),
 702                 .left_margin    = 0,
 703                 .hsync_len      = 0,
 704                 .right_margin   = 320,
 705                 .upper_margin   = 0,
 706                 .vsync_len      = 0,
 707                 .lower_margin   = 38,
 708                 .sync           = FB_SYNC_CLK_LAT_FALL,
 709         },
 710 #endif
 711         {
 712                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 713                 .refresh        = 60,
 714                 .left_margin    = 48,
 715                 .hsync_len      = 96,
 716                 .right_margin   = 16,
 717                 .upper_margin   = 31,
 718                 .vsync_len      = 2,
 719                 .lower_margin   = 12,
 720                 .sync           = FB_SYNC_CLK_LAT_FALL,
 721         },
 722 };
 723
 724 static int lcd_enabled = 1;
 725 static int lcd_bl_polarity;
 726
 727 static int lcd_backlight_polarity(void)
 728 {
 729         return lcd_bl_polarity;
 730 }
 731
 732 void lcd_enable(void)
 733 {
 734         /* HACK ALERT:
 735          * global variable from common/lcd.c
 736          * Set to 0 here to prevent messages from going to LCD
 737          * rather than serial console
 738          */
 739         lcd_is_enabled = 0;
 740
 741         karo_load_splashimage(1);
 742
 743         if (lcd_enabled) {
 744                 debug("Switching LCD on\n");
 745                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 746                 udelay(100);
 747                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 748                 udelay(300000);
 749                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 750                         lcd_backlight_polarity());
 751         }
 752 }
 753
 754 void lcd_disable(void)
 755 {
 756         if (lcd_enabled) {
 757                 printf("Disabling LCD\n");
 758                 ipuv3_fb_shutdown();
 759         }
 760 }
 761
 762 void lcd_panel_disable(void)
 763 {
 764         if (lcd_enabled) {
 765                 debug("Switching LCD off\n");
 766                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 767                         !lcd_backlight_polarity());
 768                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
 769                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 770         }
 771 }
 772
 773 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 774         /* LCD RESET */
 775         MX6_PAD_EIM_D29__GPIO_3_29,
 776         /* LCD POWER_ENABLE */
 777         MX6_PAD_EIM_EB3__GPIO_2_31,
 778         /* LCD Backlight (PWM) */
 779         MX6_PAD_GPIO_1__GPIO_1_1,
 780
 781 #ifndef CONFIG_SYS_LVDS_IF
 782         /* Display */
 783         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 784         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 785         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 786         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 787         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 788         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 789         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 790         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 791         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 792         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 793         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 794         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 795         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 796         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 797         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 798         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 799         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 800         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 801         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 802         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 803         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 804         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 805         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 806         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 807         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
 808         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
 809         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 810         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 811 #endif
 812 };
 813
 814 static const struct gpio stk5_lcd_gpios[] = {
 815         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 816         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 817         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 818 };
 819
 820 void lcd_ctrl_init(void *lcdbase)
 821 {
 822         int color_depth = 24;
 823         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 824         const char *vm;
 825         unsigned long val;
 826         int refresh = 60;
 827         struct fb_videomode *p = &tx6_fb_modes[0];
 828         struct fb_videomode fb_mode;
 829         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 830         int pix_fmt;
 831         int lcd_bus_width;
 832         unsigned long di_clk_rate = 65000000;
 833
 834         if (!lcd_enabled) {
 835                 debug("LCD disabled\n");
 836                 return;
 837         }
 838
 839         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 840                 debug("Disabling LCD\n");
 841                 lcd_enabled = 0;
 842                 setenv("splashimage", NULL);
 843                 return;
 844         }
 845
 846         karo_fdt_move_fdt();
 847         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 848
 849         if (video_mode == NULL) {
 850                 debug("Disabling LCD\n");
 851                 lcd_enabled = 0;
 852                 return;
 853         }
 854         vm = video_mode;
 855         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 856                 p = &fb_mode;
 857                 debug("Using video mode from FDT\n");
 858                 vm += strlen(vm);
 859                 if (fb_mode.xres > panel_info.vl_col ||
 860                         fb_mode.yres > panel_info.vl_row) {
 861                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 862                                 fb_mode.xres, fb_mode.yres,
 863                                 panel_info.vl_col, panel_info.vl_row);
 864                         lcd_enabled = 0;
 865                         return;
 866                 }
 867         }
 868         if (p->name != NULL)
 869                 debug("Trying compiled-in video modes\n");
 870         while (p->name != NULL) {
 871                 if (strcmp(p->name, vm) == 0) {
 872                         debug("Using video mode: '%s'\n", p->name);
 873                         vm += strlen(vm);
 874                         break;
 875                 }
 876                 p++;
 877         }
 878         if (*vm != '\0')
 879                 debug("Trying to decode video_mode: '%s'\n", vm);
 880         while (*vm != '\0') {
 881                 if (*vm >= '0' && *vm <= '9') {
 882                         char *end;
 883
 884                         val = simple_strtoul(vm, &end, 0);
 885                         if (end > vm) {
 886                                 if (!xres_set) {
 887                                         if (val > panel_info.vl_col)
 888                                                 val = panel_info.vl_col;
 889                                         p->xres = val;
 890                                         panel_info.vl_col = val;
 891                                         xres_set = 1;
 892                                 } else if (!yres_set) {
 893                                         if (val > panel_info.vl_row)
 894                                                 val = panel_info.vl_row;
 895                                         p->yres = val;
 896                                         panel_info.vl_row = val;
 897                                         yres_set = 1;
 898                                 } else if (!bpp_set) {
 899                                         switch (val) {
 900                                         case 32:
 901                                         case 24:
 902                                                 if (is_lvds())
 903                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 904                                                 /* fallthru */
 905                                         case 16:
 906                                         case 8:
 907                                                 color_depth = val;
 908                                                 break;
 909
 910                                         case 18:
 911                                                 if (is_lvds()) {
 912                                                         color_depth = val;
 913                                                         break;
 914                                                 }
 915                                                 /* fallthru */
 916                                         default:
 917                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 918                                                         end - vm, vm, color_depth);
 919                                         }
 920                                         bpp_set = 1;
 921                                 } else if (!refresh_set) {
 922                                         refresh = val;
 923                                         refresh_set = 1;
 924                                 }
 925                         }
 926                         vm = end;
 927                 }
 928                 switch (*vm) {
 929                 case '@':
 930                         bpp_set = 1;
 931                         /* fallthru */
 932                 case '-':
 933                         yres_set = 1;
 934                         /* fallthru */
 935                 case 'x':
 936                         xres_set = 1;
 937                         /* fallthru */
 938                 case 'M':
 939                 case 'R':
 940                         vm++;
 941                         break;
 942
 943                 default:
 944                         if (*vm != '\0')
 945                                 vm++;
 946                 }
 947         }
 948         if (p->xres == 0 || p->yres == 0) {
 949                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 950                 lcd_enabled = 0;
 951                 printf("Supported video modes are:");
 952                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
 953                         printf(" %s", p->name);
 954                 }
 955                 printf("\n");
 956                 return;
 957         }
 958         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 959                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 960                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 961                 lcd_enabled = 0;
 962                 return;
 963         }
 964         panel_info.vl_col = p->xres;
 965         panel_info.vl_row = p->yres;
 966
 967         switch (color_depth) {
 968         case 8:
 969                 panel_info.vl_bpix = LCD_COLOR8;
 970                 break;
 971         case 16:
 972                 panel_info.vl_bpix = LCD_COLOR16;
 973                 break;
 974         default:
 975                 panel_info.vl_bpix = LCD_COLOR24;
 976         }
 977
 978         p->pixclock = KHZ2PICOS(refresh *
 979                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 980                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 981                                 1000);
 982         debug("Pixel clock set to %lu.%03lu MHz\n",
 983                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 984
 985         if (p != &fb_mode) {
 986                 int ret;
 987
 988                 debug("Creating new display-timing node from '%s'\n",
 989                         video_mode);
 990                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
 991                 if (ret)
 992                         printf("Failed to create new display-timing node from '%s': %d\n",
 993                                 video_mode, ret);
 994         }
 995
 996         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 997         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 998                                         ARRAY_SIZE(stk5_lcd_pads));
 999
1000         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1001         switch (lcd_bus_width) {
1002         case 24:
1003                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1004                 break;
1005
1006         case 18:
1007                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1008                 break;
1009
1010         case 16:
1011                 if (!is_lvds()) {
1012                         pix_fmt = IPU_PIX_FMT_RGB565;
1013                         break;
1014                 }
1015                 /* fallthru */
1016         default:
1017                 lcd_enabled = 0;
1018                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1019                         lcd_bus_width);
1020                 return;
1021         }
1022         if (is_lvds()) {
1023                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1024                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1025                 uint32_t gpr2;
1026                 uint32_t gpr3;
1027
1028                 if (lvds_chan_mask == 0) {
1029                         printf("No LVDS channel active\n");
1030                         lcd_enabled = 0;
1031                         return;
1032                 }
1033
1034                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1035                 if (lcd_bus_width == 24)
1036                         gpr2 |= (1 << 5) | (1 << 7);
1037                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1038                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1039                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1040                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1041
1042                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1043                 gpr3 &= ~((3 << 8) | (3 << 6));
1044                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1045         }
1046         if (karo_load_splashimage(0) == 0) {
1047                 int ret;
1048
1049                 debug("Initializing LCD controller\n");
1050                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1051                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1052                                 di_clk_rate, -1);
1053                 if (ret) {
1054                         printf("Failed to initialize FB driver: %d\n", ret);
1055                         lcd_enabled = 0;
1056                 }
1057         } else {
1058                 debug("Skipping initialization of LCD controller\n");
1059         }
1060 }
1061 #else
1062 #define lcd_enabled 0
1063 #endif /* CONFIG_LCD */
1064
1065 static void stk5_board_init(void)
1066 {
1067         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1068         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1069 }
1070
1071 static void stk5v3_board_init(void)
1072 {
1073         stk5_board_init();
1074 }
1075
1076 static void stk5v5_board_init(void)
1077 {
1078         stk5_board_init();
1079
1080         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1081                         "Flexcan Transceiver");
1082         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1083 }
1084
1085 static void tx6qdl_set_cpu_clock(void)
1086 {
1087         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1088
1089         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1090                 return;
1091
1092         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1093                 printf("%s detected; skipping cpu clock change\n",
1094                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1095                 return;
1096         }
1097         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1098                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1099                 printf("CPU clock set to %lu.%03lu MHz\n",
1100                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1101         } else {
1102                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1103         }
1104 }
1105
1106 static void tx6_init_mac(void)
1107 {
1108         u8 mac[ETH_ALEN];
1109
1110         imx_get_mac_from_fuse(-1, mac);
1111         if (!is_valid_ether_addr(mac)) {
1112                 printf("No valid MAC address programmed\n");
1113                 return;
1114         }
1115
1116         printf("MAC addr from fuse: %pM\n", mac);
1117         eth_setenv_enetaddr("ethaddr", mac);
1118 }
1119
1120 int board_late_init(void)
1121 {
1122         int ret = 0;
1123         const char *baseboard;
1124
1125         env_cleanup();
1126
1127         if (tx6_temp_check_enabled)
1128                 check_cpu_temperature(1);
1129
1130         tx6qdl_set_cpu_clock();
1131
1132         if (had_ctrlc())
1133                 setenv_ulong("safeboot", 1);
1134         else if (wrsr & WRSR_TOUT)
1135                 setenv_ulong("wdreset", 1);
1136         else
1137                 karo_fdt_move_fdt();
1138
1139         baseboard = getenv("baseboard");
1140         if (!baseboard)
1141                 goto exit;
1142
1143         printf("Baseboard: %s\n", baseboard);
1144
1145         if (strncmp(baseboard, "stk5", 4) == 0) {
1146                 if ((strlen(baseboard) == 4) ||
1147                         strcmp(baseboard, "stk5-v3") == 0) {
1148                         stk5v3_board_init();
1149                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1150                         const char *otg_mode = getenv("otg_mode");
1151
1152                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1153                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1154                                         otg_mode, baseboard);
1155                                 setenv("otg_mode", "none");
1156                         }
1157                         stk5v5_board_init();
1158                 } else {
1159                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1160                                 baseboard + 4);
1161                 }
1162         } else {
1163                 printf("WARNING: Unsupported baseboard: '%s'\n",
1164                         baseboard);
1165                 ret = -EINVAL;
1166         }
1167
1168 exit:
1169         tx6_init_mac();
1170
1171         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1172         clear_ctrlc();
1173         return ret;
1174 }
1175
1176 #ifdef CONFIG_NO_NAND
1177 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
1178 #else /* CONFIG_NO_NAND */
1179 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
1180 #endif /* CONFIG_NO_NAND */
1181
1182 #ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
1183 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
1184 #else
1185 #define TX6_DDR_SZ      2
1186 #endif
1187
1188 static char tx6_mem_table[] = {
1189         '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
1190         '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
1191         '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
1192         '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
1193         '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
1194         '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
1195         '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
1196         '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
1197         '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
1198         '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
1199         '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
1200         '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
1201 };
1202
1203 static inline char tx6_mem_suffix(void)
1204 {
1205         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
1206
1207         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
1208                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
1209
1210         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
1211                 return '?';
1212
1213         return tx6_mem_table[mem_idx];
1214 };
1215
1216 static struct {
1217         uchar addr;
1218         uchar rev;
1219 } tx6_mod_revs[] = {
1220         { 0x3c, 1, },
1221         { 0x32, 2, },
1222         { 0x33, 3, },
1223 };
1224
1225 static int tx6_get_mod_rev(void)
1226 {
1227         int i;
1228
1229         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
1230                 int ret = i2c_probe(tx6_mod_revs[i].addr);
1231                 if (ret == 0) {
1232                         debug("I2C probe succeeded for addr %02x\n", tx6_mod_revs[i].addr);
1233                         return tx6_mod_revs[i].rev;
1234                 }
1235                 debug("I2C probe returned %d for addr %02x\n", ret,
1236                         tx6_mod_revs[i].addr);
1237         }
1238         return 0;
1239 }
1240
1241 int checkboard(void)
1242 {
1243         u32 cpurev = get_cpu_rev();
1244         int cpu_variant = (cpurev >> 12) & 0xff;
1245
1246         tx6qdl_print_cpuinfo();
1247
1248         i2c_init(CONFIG_SYS_I2C_SPEED, 0 /* unused */);
1249
1250         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
1251                 tx6_mod_suffix,
1252                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1253                 is_lvds(), tx6_get_mod_rev(),
1254                 tx6_mem_suffix());
1255
1256         return 0;
1257 }
1258
1259 #ifdef CONFIG_SERIAL_TAG
1260 void get_board_serial(struct tag_serialnr *serialnr)
1261 {
1262         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1263         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1264
1265         serialnr->low = readl(&fuse->cfg0);
1266         serialnr->high = readl(&fuse->cfg1);
1267 }
1268 #endif
1269
1270 #if defined(CONFIG_OF_BOARD_SETUP)
1271 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1272 #include <jffs2/jffs2.h>
1273 #include <mtd_node.h>
1274 static struct node_info nodes[] = {
1275         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1276 };
1277 #else
1278 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1279 #endif
1280
1281 static const char *tx6_touchpanels[] = {
1282         "ti,tsc2007",
1283         "edt,edt-ft5x06",
1284         "eeti,egalax_ts",
1285 };
1286
1287 void ft_board_setup(void *blob, bd_t *bd)
1288 {
1289         const char *baseboard = getenv("baseboard");
1290         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1291         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1292         int ret;
1293
1294         ret = fdt_increase_size(blob, 4096);
1295         if (ret)
1296                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1297
1298         if (stk5_v5)
1299                 karo_fdt_enable_node(blob, "stk5led", 0);
1300
1301         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1302         fdt_fixup_ethernet(blob);
1303
1304         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1305                                 ARRAY_SIZE(tx6_touchpanels));
1306         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1307         karo_fdt_fixup_flexcan(blob, stk5_v5);
1308
1309         karo_fdt_update_fb_mode(blob, video_mode);
1310 }
1311 #endif /* CONFIG_OF_BOARD_SETUP */