karo: txul: fix LDO4 output voltage
[karo-tx-uboot.git] / board / karo / tx6 / tx6ul.c
1 /*
2  * Copyright (C) 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
37
38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
40
41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
42
43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
46
47 #ifdef CONFIG_SYS_I2C_SOFT
48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
50 #endif
51
52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
53
54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
56 #else
57 #define TEMPERATURE_MIN                 (-40)
58 #endif
59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
61 #else
62 #define TEMPERATURE_HOT                 80
63 #endif
64
65 DECLARE_GLOBAL_DATA_PTR;
66
67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
68
69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
70 #ifdef CONFIG_SECURE_BOOT
71 char __csf_data[0] __attribute__((section(".__csf_data")));
72 #endif
73
74 #define TX6UL_DEFAULT_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
75                                         PAD_CTL_SPEED_MED |             \
76                                         PAD_CTL_DSE_40ohm |             \
77                                         PAD_CTL_SRE_FAST)
78 #define TX6UL_I2C_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
79                                         PAD_CTL_ODE |                   \
80                                         PAD_CTL_HYS |                   \
81                                         PAD_CTL_SPEED_LOW |             \
82                                         PAD_CTL_DSE_34ohm |             \
83                                         PAD_CTL_SRE_FAST)
84 #define TX6UL_ENET_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
85                                         PAD_CTL_DSE_120ohm |            \
86                                         PAD_CTL_PUS_100K_UP |           \
87                                         PAD_CTL_SRE_FAST)
88 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
89                                         PAD_CTL_DSE_60ohm |             \
90                                         PAD_CTL_SRE_SLOW)
91 #define TX6UL_GPIO_IN_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
92                                         PAD_CTL_PUS_47K_UP)
93
94
95 static const iomux_v3_cfg_t const tx6ul_pads[] = {
96         /* UART pads */
97 #if CONFIG_MXC_UART_BASE == UART1_BASE
98         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
99         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
100         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
101         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
102 #endif
103 #if CONFIG_MXC_UART_BASE == UART2_BASE
104         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
105         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
106         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
107         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
108 #endif
109 #if CONFIG_MXC_UART_BASE == UART5_BASE
110         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
111         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
112         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
113         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
114 #endif
115         /* FEC PHY GPIO functions */
116         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
117         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
118         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
119 };
120
121 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
122         /* FEC functions */
123         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm |
124                                                      PAD_CTL_SPEED_LOW),
125         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
126                                                       PAD_CTL_DSE_120ohm |
127                                                       PAD_CTL_SPEED_LOW),
128         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
129                                                      PAD_CTL_DSE_80ohm |
130                                                      PAD_CTL_SRE_SLOW),
131
132         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
133         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
134         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
135         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
136         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
137         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
138         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
139 };
140
141 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
142         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
143                                                             PAD_CTL_DSE_80ohm |
144                                                             PAD_CTL_SRE_SLOW),
145         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
146         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
147         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
148         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
149         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
150         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
151         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
152 };
153
154 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
155         /* internal I2C */
156         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
157                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
158         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
159                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
160 };
161
162 static const struct gpio const tx6ul_gpios[] = {
163 #ifdef CONFIG_SYS_I2C_SOFT
164         /* These two entries are used to forcefully reinitialize the I2C bus */
165         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
166         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
167 #endif
168         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
169         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
170         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
171 };
172
173 static const struct gpio const tx6ul_fec2_gpios[] = {
174         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
175         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
176 };
177
178 #define GPIO_DR 0
179 #define GPIO_DIR 4
180 #define GPIO_PSR 8
181
182 /* run with default environment */
183 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
184 #define SCL_BANK        (TX6UL_I2C1_SCL_GPIO / 32)
185 #define SDA_BANK        (TX6UL_I2C1_SDA_GPIO / 32)
186 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
187 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
188
189 static void * const gpio_ports[] = {
190         (void *)GPIO1_BASE_ADDR,
191         (void *)GPIO2_BASE_ADDR,
192         (void *)GPIO3_BASE_ADDR,
193         (void *)GPIO4_BASE_ADDR,
194         (void *)GPIO5_BASE_ADDR,
195 };
196
197 static void tx6ul_i2c_recover(void)
198 {
199         int i;
200         int bad = 0;
201         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
202         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
203
204         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
205             (readl(&sda_regs->gpio_psr) & SDA_BIT))
206                 return;
207
208         debug("Clearing I2C bus\n");
209         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
210                 printf("I2C SCL stuck LOW\n");
211                 bad++;
212
213                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
214                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
215
216                 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
217                                        MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
218         }
219         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
220                 printf("I2C SDA stuck LOW\n");
221                 bad++;
222
223                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
224                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
225                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
226
227                 udelay(5);
228
229                 for (i = 0; i < 18; i++) {
230                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
231
232                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
233                         writel(reg, &scl_regs->gpio_dr);
234                         udelay(5);
235                         if (reg & SCL_BIT) {
236                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
237                                         break;
238                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
239                                         break;
240                                 break;
241                         }
242                 }
243         }
244         if (bad) {
245                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
246                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
247
248                 if (scl && sda) {
249                         printf("I2C bus recovery succeeded\n");
250                 } else {
251                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
252                                scl, sda);
253                 }
254                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
255                                                  ARRAY_SIZE(tx6ul_i2c_pads));
256         }
257 }
258 #else
259 static inline void tx6ul_i2c_recover(void)
260 {
261 }
262 #endif
263
264 /* placed in section '.data' to prevent overwriting relocation info
265  * overlayed with bss
266  */
267 static u32 wrsr __data;
268
269 #define WRSR_POR                        (1 << 4)
270 #define WRSR_TOUT                       (1 << 1)
271 #define WRSR_SFTW                       (1 << 0)
272
273 static void print_reset_cause(void)
274 {
275         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
276         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
277         u32 srsr;
278         char *dlm = "";
279
280         printf("Reset cause: ");
281
282         srsr = readl(&src_regs->srsr);
283         wrsr = readw(wdt_base + 4);
284
285         if (wrsr & WRSR_POR) {
286                 printf("%sPOR", dlm);
287                 dlm = " | ";
288         }
289         if (srsr & 0x00004) {
290                 printf("%sCSU", dlm);
291                 dlm = " | ";
292         }
293         if (srsr & 0x00008) {
294                 printf("%sIPP USER", dlm);
295                 dlm = " | ";
296         }
297         if (srsr & 0x00010) {
298                 if (wrsr & WRSR_SFTW) {
299                         printf("%sSOFT", dlm);
300                         dlm = " | ";
301                 }
302                 if (wrsr & WRSR_TOUT) {
303                         printf("%sWDOG", dlm);
304                         dlm = " | ";
305                 }
306         }
307         if (srsr & 0x00020) {
308                 printf("%sJTAG HIGH-Z", dlm);
309                 dlm = " | ";
310         }
311         if (srsr & 0x00040) {
312                 printf("%sJTAG SW", dlm);
313                 dlm = " | ";
314         }
315         if (srsr & 0x10000) {
316                 printf("%sWARM BOOT", dlm);
317                 dlm = " | ";
318         }
319         if (dlm[0] == '\0')
320                 printf("unknown");
321
322         printf("\n");
323 }
324
325 #ifdef CONFIG_IMX6_THERMAL
326 #include <thermal.h>
327 #include <imx_thermal.h>
328 #include <fuse.h>
329
330 static void print_temperature(void)
331 {
332         struct udevice *thermal_dev;
333         int cpu_tmp, minc, maxc, ret;
334         char const *grade_str;
335         static u32 __data thermal_calib;
336
337         puts("Temperature: ");
338         switch (get_cpu_temp_grade(&minc, &maxc)) {
339         case TEMP_AUTOMOTIVE:
340                 grade_str = "Automotive";
341                 break;
342         case TEMP_INDUSTRIAL:
343                 grade_str = "Industrial";
344                 break;
345         case TEMP_EXTCOMMERCIAL:
346                 grade_str = "Extended Commercial";
347                 break;
348         default:
349                 grade_str = "Commercial";
350         }
351         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
352         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
353         if (ret == 0) {
354                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
355
356                 if (ret == 0)
357                         printf(" at %dC", cpu_tmp);
358                 else
359                         puts(" - failed to read sensor data");
360         } else {
361                 puts(" - no sensor device found");
362         }
363
364         if (fuse_read(1, 6, &thermal_calib) == 0) {
365                 printf(" - calibration data 0x%08x\n", thermal_calib);
366         } else {
367                 puts(" - Failed to read thermal calib fuse\n");
368         }
369 }
370 #else
371 static inline void print_temperature(void)
372 {
373 }
374 #endif
375
376 int checkboard(void)
377 {
378         u32 cpurev = get_cpu_rev();
379         char *cpu_str = "?";
380
381         if (is_cpu_type(MXC_CPU_MX6SL))
382                 cpu_str = "SL";
383         else if (is_cpu_type(MXC_CPU_MX6DL))
384                 cpu_str = "DL";
385         else if (is_cpu_type(MXC_CPU_MX6SOLO))
386                 cpu_str = "SOLO";
387         else if (is_cpu_type(MXC_CPU_MX6Q))
388                 cpu_str = "Q";
389         else if (is_cpu_type(MXC_CPU_MX6UL))
390                 cpu_str = "UL";
391         else if (is_cpu_type(MXC_CPU_MX6ULL))
392                 cpu_str = "ULL";
393
394         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
395                 cpu_str,
396                 (cpurev & 0x000F0) >> 4,
397                 (cpurev & 0x0000F) >> 0,
398                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
399
400         print_temperature();
401         print_reset_cause();
402 #ifdef CONFIG_MX6_TEMPERATURE_HOT
403         check_cpu_temperature(1);
404 #endif
405         tx6ul_i2c_recover();
406         return 0;
407 }
408
409 /* serial port not initialized at this point */
410 int board_early_init_f(void)
411 {
412         return 0;
413 }
414
415 #ifndef CONFIG_MX6_TEMPERATURE_HOT
416 static bool tx6ul_temp_check_enabled = true;
417 #else
418 #define tx6ul_temp_check_enabled        0
419 #endif
420
421 static inline u8 tx6ul_mem_suffix(void)
422 {
423         return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
424                 IS_ENABLED(CONFIG_TX6_EMMC);
425 }
426
427 #ifdef CONFIG_RN5T567
428 /* PMIC settings */
429 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
430 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
431 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
432 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
433 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
434 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval(3300)         /* DCDC4 */
435 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval(3300)
436 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
437 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
438 #define VDD_ADC_VAL             rn5t_mV_to_regval2(3300)        /* LDO2 */
439 #define VDD_ADC_VAL_LP          rn5t_mV_to_regval2(3300)
440 #define VDD_PMIC_VAL            rn5t_mV_to_regval2(2500)        /* LDO3 */
441 #define VDD_PMIC_VAL_LP         rn5t_mV_to_regval2(2500)
442 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 */
443 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
444
445 static struct pmic_regs rn5t567_regs[] = {
446         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
447         { RN5T567_DC1DAC, VDD_CORE_VAL, },
448         { RN5T567_DC3DAC, VDD_DDR_VAL, },
449         { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
450         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
451         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
452         { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
453         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
454         { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
455         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
456         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
457         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
458         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
459         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
460         { RN5T567_LDO2DAC, VDD_ADC_VAL, },
461         { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
462         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
463         { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, },
464         { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
465         { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
466         { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
467         { RN5T567_LDOEN1, 0x0f, ~0x1f, },
468         { RN5T567_LDOEN2, 0x10, ~0x30, },
469         { RN5T567_LDODIS, 0x10, ~0x1f, },
470         { RN5T567_INTPOL, 0, },
471         { RN5T567_INTEN, 0x3, },
472         { RN5T567_IREN, 0xf, },
473         { RN5T567_EN_GPIR, 0, },
474 };
475
476 static int pmic_addr = 0x33;
477 #endif
478
479 int board_init(void)
480 {
481         int ret;
482         u32 cpurev = get_cpu_rev();
483         char f = '?';
484
485         if (is_cpu_type(MXC_CPU_MX6UL))
486                 f = ((cpurev & 0xff) > 0x10) ? '5' : '0';
487         else if (is_cpu_type(MXC_CPU_MX6ULL))
488                 f = '8';
489
490         debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
491
492         printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
493
494         get_hab_status();
495
496         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
497         if (ret < 0)
498                 printf("Failed to request tx6ul_gpios: %d\n", ret);
499
500         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
501
502         /* Address of boot parameters */
503         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
504         gd->bd->bi_arch_number = -1;
505
506         if (ctrlc() || (wrsr & WRSR_TOUT)) {
507                 if (wrsr & WRSR_TOUT)
508                         printf("WDOG RESET detected; Skipping PMIC setup\n");
509                 else
510                         printf("<CTRL-C> detected; safeboot enabled\n");
511 #ifndef CONFIG_MX6_TEMPERATURE_HOT
512                 tx6ul_temp_check_enabled = false;
513 #endif
514                 return 0;
515         }
516
517         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
518         if (ret) {
519                 printf("Failed to setup PMIC voltages: %d\n", ret);
520                 hang();
521         }
522         return 0;
523 }
524
525 int dram_init(void)
526 {
527         debug("%s@%d: \n", __func__, __LINE__);
528
529         /* dram_init must store complete ramsize in gd->ram_size */
530         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
531                                     PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
532         return 0;
533 }
534
535 void dram_init_banksize(void)
536 {
537         debug("%s@%d: \n", __func__, __LINE__);
538
539         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
540         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
541                                                PHYS_SDRAM_1_SIZE);
542 #if CONFIG_NR_DRAM_BANKS > 1
543         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
544         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
545                                                PHYS_SDRAM_2_SIZE);
546 #endif
547 }
548
549 #ifdef  CONFIG_FSL_ESDHC
550 #define TX6UL_SD_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
551                                         PAD_CTL_SPEED_MED |             \
552                                         PAD_CTL_DSE_40ohm |             \
553                                         PAD_CTL_SRE_FAST)
554
555 static const iomux_v3_cfg_t mmc0_pads[] = {
556         MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
557         MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
558         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
559         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
560         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
561         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
562         /* SD1 CD */
563         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
564 };
565
566 #ifdef CONFIG_TX6_EMMC
567 static const iomux_v3_cfg_t mmc1_pads[] = {
568         MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
569         MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
570         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
571         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
572         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
573         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
574         /* eMMC RESET */
575         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
576                                                         PAD_CTL_DSE_40ohm),
577 };
578 #endif
579
580 static struct tx6ul_esdhc_cfg {
581         const iomux_v3_cfg_t *pads;
582         int num_pads;
583         enum mxc_clock clkid;
584         struct fsl_esdhc_cfg cfg;
585         int cd_gpio;
586 } tx6ul_esdhc_cfg[] = {
587 #ifdef CONFIG_TX6_EMMC
588         {
589                 .pads = mmc1_pads,
590                 .num_pads = ARRAY_SIZE(mmc1_pads),
591                 .clkid = MXC_ESDHC2_CLK,
592                 .cfg = {
593                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
594                         .max_bus_width = 4,
595                 },
596                 .cd_gpio = -EINVAL,
597         },
598 #endif
599         {
600                 .pads = mmc0_pads,
601                 .num_pads = ARRAY_SIZE(mmc0_pads),
602                 .clkid = MXC_ESDHC_CLK,
603                 .cfg = {
604                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
605                         .max_bus_width = 4,
606                 },
607                 .cd_gpio = TX6UL_SD1_CD_GPIO,
608         },
609 };
610
611 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
612 {
613         return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
614 }
615
616 int board_mmc_getcd(struct mmc *mmc)
617 {
618         struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
619
620         if (cfg->cd_gpio < 0)
621                 return 1;
622
623         debug("SD card %d is %spresent (GPIO %d)\n",
624               cfg - tx6ul_esdhc_cfg,
625               gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
626               cfg->cd_gpio);
627         return !gpio_get_value(cfg->cd_gpio);
628 }
629
630 int board_mmc_init(bd_t *bis)
631 {
632         int i;
633
634         debug("%s@%d: \n", __func__, __LINE__);
635
636 #ifndef CONFIG_ENV_IS_IN_MMC
637         if (!(gd->flags & GD_FLG_ENV_READY)) {
638                 printf("deferred ...");
639                 return 0;
640         }
641 #endif
642         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
643                 struct mmc *mmc;
644                 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
645                 int ret;
646
647                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
648                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
649
650                 if (cfg->cd_gpio >= 0) {
651                         ret = gpio_request_one(cfg->cd_gpio,
652                                                GPIOFLAG_INPUT, "MMC CD");
653                         if (ret) {
654                                 printf("Error %d requesting GPIO%d_%d\n",
655                                        ret, cfg->cd_gpio / 32,
656                                        cfg->cd_gpio % 32);
657                                 continue;
658                         }
659                 }
660
661                 debug("%s: Initializing MMC slot %d\n", __func__, i);
662                 fsl_esdhc_initialize(bis, &cfg->cfg);
663
664                 mmc = find_mmc_device(i);
665                 if (mmc == NULL)
666                         continue;
667                 if (board_mmc_getcd(mmc))
668                         mmc_init(mmc);
669         }
670         return 0;
671 }
672 #endif /* CONFIG_FSL_ESDHC */
673
674 enum {
675         LED_STATE_INIT = -1,
676         LED_STATE_OFF,
677         LED_STATE_ON,
678         LED_STATE_ERR,
679 };
680
681 static inline int calc_blink_rate(void)
682 {
683         if (!tx6ul_temp_check_enabled)
684                 return CONFIG_SYS_HZ;
685
686         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
687                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
688                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
689 }
690
691 void show_activity(int arg)
692 {
693         static int led_state = LED_STATE_INIT;
694         static int blink_rate;
695         static ulong last;
696         int ret;
697
698         switch (led_state) {
699         case LED_STATE_ERR:
700                 return;
701
702         case LED_STATE_INIT:
703                 last = get_timer(0);
704                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
705                 if (ret)
706                         led_state = LED_STATE_ERR;
707                 else
708                         led_state = LED_STATE_ON;
709                 blink_rate = calc_blink_rate();
710                 break;
711
712         case LED_STATE_ON:
713         case LED_STATE_OFF:
714                 if (get_timer(last) > blink_rate) {
715                         blink_rate = calc_blink_rate();
716                         last = get_timer_masked();
717                         if (led_state == LED_STATE_ON) {
718                                 gpio_set_value(TX6UL_LED_GPIO, 0);
719                         } else {
720                                 gpio_set_value(TX6UL_LED_GPIO, 1);
721                         }
722                         led_state = 1 - led_state;
723                 }
724                 break;
725         }
726 }
727
728 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
729         MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
730         MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
731         MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
732         MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
733         MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
734         MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
735 };
736
737 static const iomux_v3_cfg_t stk5_pads[] = {
738         /* SW controlled LED on STK5 baseboard */
739         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
740
741         /* I2C bus on DIMM pins 40/41 */
742         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
743         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
744
745         /* TSC200x PEN IRQ */
746         MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
747
748         /* EDT-FT5x06 Polytouch panel */
749         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
750         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
751         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
752
753         /* USBH1 */
754         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
755         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
756
757         /* USBOTG */
758         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
759         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
760 };
761
762 static const struct gpio stk5_gpios[] = {
763         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
764
765         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
766         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
767 };
768
769 static const iomux_v3_cfg_t tx_tester_pads[] = {
770         /* SW controlled LEDs on TX-TESTER-V5 baseboard */
771         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04, /* red LED */
772         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09, /* yellow LED */
773         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08, /* green LED */
774
775         MX6_PAD_LCD_DATA04__GPIO3_IO09, /* IO_RESET */
776
777         /* I2C bus on DIMM pins 40/41 */
778         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
779         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
780
781         /* USBH1 */
782         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
783         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
784
785         /* USBOTG */
786         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
787         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
788
789         MX6_PAD_LCD_DATA08__GPIO3_IO13 | TX6UL_GPIO_OUT_PAD_CTRL,
790         MX6_PAD_LCD_DATA09__GPIO3_IO14 | TX6UL_GPIO_OUT_PAD_CTRL,
791         MX6_PAD_LCD_DATA10__GPIO3_IO15 | TX6UL_GPIO_OUT_PAD_CTRL,
792
793         /* USBH_VBUSEN */
794         MX6_PAD_LCD_DATA11__GPIO3_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
795
796         /*
797          * no drive capability for DUT_ETN_LINKLED, DUT_ETN_ACTLED
798          * to not interfere whith the DUT ETN PHY strap pins
799          */
800         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02, MUX_PAD_CTRL(PAD_CTL_HYS |
801                                                        PAD_CTL_DSE_DISABLE |
802                                                        PAD_CTL_SPEED_LOW),
803         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03, MUX_PAD_CTRL(PAD_CTL_HYS |
804                                                        PAD_CTL_DSE_DISABLE |
805                                                        PAD_CTL_SPEED_LOW),
806 };
807
808 static const struct gpio tx_tester_gpios[] = {
809         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LEDGE#", },
810         { IMX_GPIO_NR(5, 4), GPIOFLAG_OUTPUT_INIT_LOW, "LEDRT#", },
811         { IMX_GPIO_NR(5, 8), GPIOFLAG_OUTPUT_INIT_LOW, "LEDGN#", },
812
813         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_HIGH, "PMIC PWR_ON", },
814
815         { IMX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "TSTART#", },
816         { IMX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "STARTED", },
817         { IMX_GPIO_NR(3, 7), GPIOFLAG_INPUT, "TSTOP#", },
818         { IMX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "STOP#", },
819
820         { IMX_GPIO_NR(3, 10), GPIOFLAG_INPUT, "DUT_PGOOD", },
821
822         { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_HIGH, "VBACKUP_OFF", },
823         { IMX_GPIO_NR(3, 12), GPIOFLAG_OUTPUT_INIT_LOW, "VBACKUP_LOAD", },
824
825         { IMX_GPIO_NR(1, 10), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD1", },
826         { IMX_GPIO_NR(3, 30), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD2", },
827         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD3", },
828
829         { IMX_GPIO_NR(3, 13), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD1", },
830         { IMX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD2", },
831         { IMX_GPIO_NR(3, 15), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD3", },
832 };
833
834 #ifdef CONFIG_LCD
835 vidinfo_t panel_info = {
836         /* set to max. size supported by SoC */
837         .vl_col = 4096,
838         .vl_row = 1024,
839
840         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
841 };
842
843 static struct fb_videomode tx6ul_fb_modes[] = {
844 #ifndef CONFIG_SYS_LVDS_IF
845         {
846                 /* Standard VGA timing */
847                 .name           = "VGA",
848                 .refresh        = 60,
849                 .xres           = 640,
850                 .yres           = 480,
851                 .pixclock       = KHZ2PICOS(25175),
852                 .left_margin    = 48,
853                 .hsync_len      = 96,
854                 .right_margin   = 16,
855                 .upper_margin   = 31,
856                 .vsync_len      = 2,
857                 .lower_margin   = 12,
858                 .sync           = FB_SYNC_CLK_LAT_FALL,
859         },
860         {
861                 /* Emerging ETV570 640 x 480 display. Syncs low active,
862                  * DE high active, 115.2 mm x 86.4 mm display area
863                  * VGA compatible timing
864                  */
865                 .name           = "ETV570",
866                 .refresh        = 60,
867                 .xres           = 640,
868                 .yres           = 480,
869                 .pixclock       = KHZ2PICOS(25175),
870                 .left_margin    = 114,
871                 .hsync_len      = 30,
872                 .right_margin   = 16,
873                 .upper_margin   = 32,
874                 .vsync_len      = 3,
875                 .lower_margin   = 10,
876                 .sync           = FB_SYNC_CLK_LAT_FALL,
877         },
878         {
879                 /* Emerging ET0350G0DH6 320 x 240 display.
880                  * 70.08 mm x 52.56 mm display area.
881                  */
882                 .name           = "ET0350",
883                 .refresh        = 60,
884                 .xres           = 320,
885                 .yres           = 240,
886                 .pixclock       = KHZ2PICOS(6500),
887                 .left_margin    = 68 - 34,
888                 .hsync_len      = 34,
889                 .right_margin   = 20,
890                 .upper_margin   = 18 - 3,
891                 .vsync_len      = 3,
892                 .lower_margin   = 4,
893                 .sync           = FB_SYNC_CLK_LAT_FALL,
894         },
895         {
896                 /* Emerging ET0430G0DH6 480 x 272 display.
897                  * 95.04 mm x 53.856 mm display area.
898                  */
899                 .name           = "ET0430",
900                 .refresh        = 60,
901                 .xres           = 480,
902                 .yres           = 272,
903                 .pixclock       = KHZ2PICOS(9000),
904                 .left_margin    = 2,
905                 .hsync_len      = 41,
906                 .right_margin   = 2,
907                 .upper_margin   = 2,
908                 .vsync_len      = 10,
909                 .lower_margin   = 2,
910         },
911         {
912                 /* Emerging ET0500G0DH6 800 x 480 display.
913                  * 109.6 mm x 66.4 mm display area.
914                  */
915                 .name           = "ET0500",
916                 .refresh        = 60,
917                 .xres           = 800,
918                 .yres           = 480,
919                 .pixclock       = KHZ2PICOS(33260),
920                 .left_margin    = 216 - 128,
921                 .hsync_len      = 128,
922                 .right_margin   = 1056 - 800 - 216,
923                 .upper_margin   = 35 - 2,
924                 .vsync_len      = 2,
925                 .lower_margin   = 525 - 480 - 35,
926                 .sync           = FB_SYNC_CLK_LAT_FALL,
927         },
928         {
929                 /* Emerging ETQ570G0DH6 320 x 240 display.
930                  * 115.2 mm x 86.4 mm display area.
931                  */
932                 .name           = "ETQ570",
933                 .refresh        = 60,
934                 .xres           = 320,
935                 .yres           = 240,
936                 .pixclock       = KHZ2PICOS(6400),
937                 .left_margin    = 38,
938                 .hsync_len      = 30,
939                 .right_margin   = 30,
940                 .upper_margin   = 16, /* 15 according to datasheet */
941                 .vsync_len      = 3, /* TVP -> 1>x>5 */
942                 .lower_margin   = 4, /* 4.5 according to datasheet */
943                 .sync           = FB_SYNC_CLK_LAT_FALL,
944         },
945         {
946                 /* Emerging ET0700G0DH6 800 x 480 display.
947                  * 152.4 mm x 91.44 mm display area.
948                  */
949                 .name           = "ET0700",
950                 .refresh        = 60,
951                 .xres           = 800,
952                 .yres           = 480,
953                 .pixclock       = KHZ2PICOS(33260),
954                 .left_margin    = 216 - 128,
955                 .hsync_len      = 128,
956                 .right_margin   = 1056 - 800 - 216,
957                 .upper_margin   = 35 - 2,
958                 .vsync_len      = 2,
959                 .lower_margin   = 525 - 480 - 35,
960                 .sync           = FB_SYNC_CLK_LAT_FALL,
961         },
962         {
963                 /* Emerging ET070001DM6 800 x 480 display.
964                  * 152.4 mm x 91.44 mm display area.
965                  */
966                 .name           = "ET070001DM6",
967                 .refresh        = 60,
968                 .xres           = 800,
969                 .yres           = 480,
970                 .pixclock       = KHZ2PICOS(33260),
971                 .left_margin    = 216 - 128,
972                 .hsync_len      = 128,
973                 .right_margin   = 1056 - 800 - 216,
974                 .upper_margin   = 35 - 2,
975                 .vsync_len      = 2,
976                 .lower_margin   = 525 - 480 - 35,
977                 .sync           = 0,
978         },
979 #else
980         {
981                 /* HannStar HSD100PXN1
982                  * 202.7m mm x 152.06 mm display area.
983                  */
984                 .name           = "HSD100PXN1",
985                 .refresh        = 60,
986                 .xres           = 1024,
987                 .yres           = 768,
988                 .pixclock       = KHZ2PICOS(65000),
989                 .left_margin    = 0,
990                 .hsync_len      = 0,
991                 .right_margin   = 320,
992                 .upper_margin   = 0,
993                 .vsync_len      = 0,
994                 .lower_margin   = 38,
995                 .sync           = FB_SYNC_CLK_LAT_FALL,
996         },
997 #endif
998         {
999                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1000                 .refresh        = 60,
1001                 .left_margin    = 48,
1002                 .hsync_len      = 96,
1003                 .right_margin   = 16,
1004                 .upper_margin   = 31,
1005                 .vsync_len      = 2,
1006                 .lower_margin   = 12,
1007                 .sync           = FB_SYNC_CLK_LAT_FALL,
1008         },
1009 };
1010
1011 static int lcd_enabled = 1;
1012 static int lcd_bl_polarity;
1013
1014 static int lcd_backlight_polarity(void)
1015 {
1016         return lcd_bl_polarity;
1017 }
1018
1019 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1020 #ifdef CONFIG_LCD
1021         /* LCD RESET */
1022         MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
1023         /* LCD POWER_ENABLE */
1024         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
1025         /* LCD Backlight (PWM) */
1026         MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
1027         /* Display */
1028         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
1029         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
1030         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
1031         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
1032         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
1033         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
1034         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
1035         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
1036         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
1037         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
1038         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
1039         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
1040         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
1041         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
1042         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
1043         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
1044         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
1045         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
1046         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
1047         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
1048         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
1049         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1050         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1051         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1052         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1053         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1054         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1055         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1056 #endif
1057 };
1058
1059 static const struct gpio stk5_lcd_gpios[] = {
1060         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1061         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1062         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1063 };
1064
1065 /* run with valid env from NAND/eMMC */
1066 void lcd_enable(void)
1067 {
1068         /* HACK ALERT:
1069          * global variable from common/lcd.c
1070          * Set to 0 here to prevent messages from going to LCD
1071          * rather than serial console
1072          */
1073         lcd_is_enabled = 0;
1074
1075         if (lcd_enabled) {
1076                 karo_load_splashimage(1);
1077
1078                 debug("Switching LCD on\n");
1079                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1080                 udelay(100);
1081                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1082                 udelay(300000);
1083                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1084                                lcd_backlight_polarity());
1085         }
1086 }
1087
1088 static void lcd_disable(void)
1089 {
1090         if (lcd_enabled) {
1091                 printf("Disabling LCD\n");
1092                 panel_info.vl_row = 0;
1093                 lcd_enabled = 0;
1094         }
1095 }
1096
1097 void lcd_ctrl_init(void *lcdbase)
1098 {
1099         int color_depth = 24;
1100         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1101         const char *vm;
1102         unsigned long val;
1103         int refresh = 60;
1104         struct fb_videomode *p = &tx6ul_fb_modes[0];
1105         struct fb_videomode fb_mode;
1106         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1107
1108         if (!lcd_enabled) {
1109                 debug("LCD disabled\n");
1110                 return;
1111         }
1112
1113         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1114                 lcd_disable();
1115                 setenv("splashimage", NULL);
1116                 return;
1117         }
1118
1119         karo_fdt_move_fdt();
1120         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1121
1122         if (video_mode == NULL) {
1123                 lcd_disable();
1124                 return;
1125         }
1126         vm = video_mode;
1127         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1128                 p = &fb_mode;
1129                 debug("Using video mode from FDT\n");
1130                 vm += strlen(vm);
1131                 if (fb_mode.xres > panel_info.vl_col ||
1132                         fb_mode.yres > panel_info.vl_row) {
1133                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1134                                fb_mode.xres, fb_mode.yres,
1135                                panel_info.vl_col, panel_info.vl_row);
1136                         lcd_enabled = 0;
1137                         return;
1138                 }
1139         }
1140         if (p->name != NULL)
1141                 debug("Trying compiled-in video modes\n");
1142         while (p->name != NULL) {
1143                 if (strcmp(p->name, vm) == 0) {
1144                         debug("Using video mode: '%s'\n", p->name);
1145                         vm += strlen(vm);
1146                         break;
1147                 }
1148                 p++;
1149         }
1150         if (*vm != '\0')
1151                 debug("Trying to decode video_mode: '%s'\n", vm);
1152         while (*vm != '\0') {
1153                 if (*vm >= '0' && *vm <= '9') {
1154                         char *end;
1155
1156                         val = simple_strtoul(vm, &end, 0);
1157                         if (end > vm) {
1158                                 if (!xres_set) {
1159                                         if (val > panel_info.vl_col)
1160                                                 val = panel_info.vl_col;
1161                                         p->xres = val;
1162                                         panel_info.vl_col = val;
1163                                         xres_set = 1;
1164                                 } else if (!yres_set) {
1165                                         if (val > panel_info.vl_row)
1166                                                 val = panel_info.vl_row;
1167                                         p->yres = val;
1168                                         panel_info.vl_row = val;
1169                                         yres_set = 1;
1170                                 } else if (!bpp_set) {
1171                                         switch (val) {
1172                                         case 8:
1173                                         case 16:
1174                                         case 18:
1175                                         case 24:
1176                                         case 32:
1177                                                 color_depth = val;
1178                                                 break;
1179
1180                                         default:
1181                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1182                                                        end - vm, vm,
1183                                                        color_depth);
1184                                         }
1185                                         bpp_set = 1;
1186                                 } else if (!refresh_set) {
1187                                         refresh = val;
1188                                         refresh_set = 1;
1189                                 }
1190                         }
1191                         vm = end;
1192                 }
1193                 switch (*vm) {
1194                 case '@':
1195                         bpp_set = 1;
1196                         /* fallthru */
1197                 case '-':
1198                         yres_set = 1;
1199                         /* fallthru */
1200                 case 'x':
1201                         xres_set = 1;
1202                         /* fallthru */
1203                 case 'M':
1204                 case 'R':
1205                         vm++;
1206                         break;
1207
1208                 default:
1209                         if (*vm != '\0')
1210                                 vm++;
1211                 }
1212         }
1213         if (p->xres == 0 || p->yres == 0) {
1214                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1215                 lcd_enabled = 0;
1216                 printf("Supported video modes are:");
1217                 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1218                         printf(" %s", p->name);
1219                 }
1220                 printf("\n");
1221                 return;
1222         }
1223         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1224                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1225                        p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1226                 lcd_enabled = 0;
1227                 return;
1228         }
1229         panel_info.vl_col = p->xres;
1230         panel_info.vl_row = p->yres;
1231
1232         switch (color_depth) {
1233         case 8:
1234                 panel_info.vl_bpix = LCD_COLOR8;
1235                 break;
1236         case 16:
1237                 panel_info.vl_bpix = LCD_COLOR16;
1238                 break;
1239         default:
1240                 panel_info.vl_bpix = LCD_COLOR32;
1241         }
1242
1243         p->pixclock = KHZ2PICOS(refresh *
1244                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1245                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1246                                 1000);
1247         debug("Pixel clock set to %lu.%03lu MHz\n",
1248               PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1249
1250         if (p != &fb_mode) {
1251                 int ret;
1252
1253                 debug("Creating new display-timing node from '%s'\n",
1254                       video_mode);
1255                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1256                 if (ret)
1257                         printf("Failed to create new display-timing node from '%s': %d\n",
1258                                video_mode, ret);
1259         }
1260
1261         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1262         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1263                                          ARRAY_SIZE(stk5_lcd_pads));
1264
1265         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1266               color_depth, refresh);
1267
1268         if (karo_load_splashimage(0) == 0) {
1269                 char vmode[128];
1270
1271                 /* setup env variable for mxsfb display driver */
1272                 snprintf(vmode, sizeof(vmode),
1273                          "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1274                          p->xres, p->yres, p->left_margin, p->right_margin,
1275                          p->upper_margin, p->lower_margin, p->hsync_len,
1276                          p->vsync_len, p->sync, p->pixclock, color_depth);
1277                 setenv("videomode", vmode);
1278
1279                 debug("Initializing LCD controller\n");
1280                 lcdif_clk_enable();
1281                 video_hw_init();
1282                 setenv("videomode", NULL);
1283         } else {
1284                 debug("Skipping initialization of LCD controller\n");
1285         }
1286 }
1287 #else
1288 #define lcd_enabled 0
1289 #endif /* CONFIG_LCD */
1290
1291 #ifndef CONFIG_ENV_IS_IN_MMC
1292 static void tx6ul_mmc_init(void)
1293 {
1294         puts("MMC:   ");
1295         if (board_mmc_init(gd->bd) < 0)
1296                 cpu_mmc_init(gd->bd);
1297         print_mmc_devices(',');
1298 }
1299 #else
1300 static inline void tx6ul_mmc_init(void)
1301 {
1302 }
1303 #endif
1304
1305 static void stk5_board_init(void)
1306 {
1307         int ret;
1308
1309         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1310         if (ret < 0) {
1311                 printf("Failed to request stk5_gpios: %d\n", ret);
1312                 return;
1313         }
1314
1315         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1316         if (getenv_yesno("jtag_enable") != 0) {
1317                 /* true if unset or set to one of: 'yYtT1' */
1318                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1319         }
1320
1321         debug("%s@%d: \n", __func__, __LINE__);
1322 }
1323
1324 static void stk5v3_board_init(void)
1325 {
1326         debug("%s@%d: \n", __func__, __LINE__);
1327         stk5_board_init();
1328         debug("%s@%d: \n", __func__, __LINE__);
1329         tx6ul_mmc_init();
1330 }
1331
1332 static void stk5v5_board_init(void)
1333 {
1334         int ret;
1335
1336         stk5_board_init();
1337         tx6ul_mmc_init();
1338
1339         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1340                                "Flexcan Transceiver");
1341         if (ret) {
1342                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1343                 return;
1344         }
1345
1346         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1347                                TX6UL_GPIO_OUT_PAD_CTRL);
1348 }
1349
1350 static void tx_tester_board_init(void)
1351 {
1352         int ret;
1353
1354         setenv("video_mode", NULL);
1355         setenv("touchpanel", NULL);
1356         if (getenv("eth1addr") && !getenv("ethprime"))
1357                 setenv("ethprime", "FEC1");
1358
1359         ret = gpio_request_array(tx_tester_gpios, ARRAY_SIZE(tx_tester_gpios));
1360         if (ret) {
1361                 printf("Failed to request TX-Tester GPIOs: %d\n", ret);
1362                 return;
1363         }
1364         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1365
1366         if (wrsr & WRSR_TOUT)
1367                 gpio_set_value(IMX_GPIO_NR(5, 4), 1);
1368
1369         if (getenv_yesno("jtag_enable") != 0) {
1370                 /* true if unset or set to one of: 'yYtT1' */
1371                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads,
1372                                                  ARRAY_SIZE(stk5_jtag_pads));
1373         }
1374
1375         gpio_set_value(IMX_GPIO_NR(3, 8), 1);
1376 }
1377
1378 static void tx6ul_set_cpu_clock(void)
1379 {
1380         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1381
1382         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1383                 return;
1384
1385         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1386                 printf("%s detected; skipping cpu clock change\n",
1387                        (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1388                 return;
1389         }
1390         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1391                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1392                 printf("CPU clock set to %lu.%03lu MHz\n",
1393                        cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1394         } else {
1395                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1396         }
1397 }
1398
1399 int board_late_init(void)
1400 {
1401         const char *baseboard;
1402
1403         debug("%s@%d: \n", __func__, __LINE__);
1404
1405         env_cleanup();
1406
1407         if (tx6ul_temp_check_enabled)
1408                 check_cpu_temperature(1);
1409
1410         tx6ul_set_cpu_clock();
1411
1412         if (had_ctrlc())
1413                 setenv_ulong("safeboot", 1);
1414         else if (wrsr & WRSR_TOUT)
1415                 setenv_ulong("wdreset", 1);
1416         else
1417                 karo_fdt_move_fdt();
1418
1419         baseboard = getenv("baseboard");
1420         if (!baseboard)
1421                 goto exit;
1422
1423         printf("Baseboard: %s\n", baseboard);
1424
1425         if (strncmp(baseboard, "stk5", 4) == 0) {
1426                 if ((strlen(baseboard) == 4) ||
1427                         strcmp(baseboard, "stk5-v3") == 0) {
1428                         stk5v3_board_init();
1429                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1430                         const char *otg_mode = getenv("otg_mode");
1431
1432                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1433                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1434                                        otg_mode, baseboard);
1435                                 setenv("otg_mode", "none");
1436                         }
1437                         stk5v5_board_init();
1438                 } else {
1439                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1440                                 baseboard + 4);
1441                 }
1442         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1443                         const char *otg_mode = getenv("otg_mode");
1444
1445                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1446                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1447                                        otg_mode, baseboard);
1448                                 setenv("otg_mode", "none");
1449                         }
1450                         stk5_board_init();
1451         } else if (strncmp(baseboard, "tx-tester-", 10) == 0) {
1452                         const char *otg_mode = getenv("otg_mode");
1453
1454                         if (!otg_mode || strcmp(otg_mode, "none") != 0)
1455                                 setenv("otg_mode", "device");
1456                         tx_tester_board_init();
1457         } else {
1458                 printf("WARNING: Unsupported baseboard: '%s'\n",
1459                         baseboard);
1460                 printf("Reboot with <CTRL-C> pressed to fix this\n");
1461                 if (!had_ctrlc())
1462                         return -EINVAL;
1463         }
1464
1465 exit:
1466         debug("%s@%d: \n", __func__, __LINE__);
1467
1468         clear_ctrlc();
1469         return 0;
1470 }
1471
1472 #ifdef CONFIG_FEC_MXC
1473
1474 #ifndef ETH_ALEN
1475 #define ETH_ALEN 6
1476 #endif
1477
1478 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
1479 {
1480         unsigned int mac0, mac1, mac2;
1481         unsigned int __maybe_unused fuse3_override, fuse4_override;
1482
1483         memset(mac, 0, 6);
1484
1485         switch (dev_id) {
1486         case 0:
1487                 if (fuse_read(4, 2, &mac0)) {
1488                         printf("Failed to read MAC0 fuse\n");
1489                         return;
1490                 }
1491                 if (fuse_read(4, 3, &mac1)) {
1492                         printf("Failed to read MAC1 fuse\n");
1493                         return;
1494                 }
1495                 mac[0] = mac1 >> 8;
1496                 mac[1] = mac1;
1497                 mac[2] = mac0 >> 24;
1498                 mac[3] = mac0 >> 16;
1499                 mac[4] = mac0 >> 8;
1500                 mac[5] = mac0;
1501                 break;
1502
1503         case 1:
1504                 if (fuse_read(4, 3, &mac1)) {
1505                         printf("Failed to read MAC1 fuse\n");
1506                         return;
1507                 }
1508                 debug("read %08x from fuse 3\n", mac1);
1509                 if (fuse_read(4, 4, &mac2)) {
1510                         printf("Failed to read MAC2 fuse\n");
1511                         return;
1512                 }
1513                 debug("read %08x from fuse 4\n", mac2);
1514                 mac[0] = mac2 >> 24;
1515                 mac[1] = mac2 >> 16;
1516                 mac[2] = mac2 >> 8;
1517                 mac[3] = mac2;
1518                 mac[4] = mac1 >> 24;
1519                 mac[5] = mac1 >> 16;
1520                 break;
1521
1522         default:
1523                 return;
1524         }
1525         debug("%s@%d: Done %d %pM\n", __func__, __LINE__, dev_id, mac);
1526 }
1527
1528 static void tx6ul_init_mac(void)
1529 {
1530         u8 mac[ETH_ALEN];
1531         const char *baseboard = getenv("baseboard");
1532
1533         imx_get_mac_from_fuse(0, mac);
1534         if (!is_valid_ethaddr(mac)) {
1535                 printf("No valid MAC address programmed\n");
1536                 return;
1537         }
1538         printf("MAC addr from fuse: %pM\n", mac);
1539         if (!getenv("ethaddr"))
1540                 eth_setenv_enetaddr("ethaddr", mac);
1541
1542         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1543                 setenv("eth1addr", NULL);
1544                 return;
1545         }
1546         if (getenv("eth1addr"))
1547                 return;
1548         imx_get_mac_from_fuse(1, mac);
1549         if (is_valid_ethaddr(mac))
1550                 eth_setenv_enetaddr("eth1addr", mac);
1551 }
1552
1553 int board_eth_init(bd_t *bis)
1554 {
1555         int ret;
1556
1557         tx6ul_init_mac();
1558
1559         /* delay at least 21ms for the PHY internal POR signal to deassert */
1560         udelay(22000);
1561
1562         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1563                                          ARRAY_SIZE(tx6ul_enet1_pads));
1564
1565         /* Deassert RESET to the external phys */
1566         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1567
1568         if (getenv("ethaddr")) {
1569                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1570                 if (ret) {
1571                         printf("failed to initialize FEC0: %d\n", ret);
1572                         return ret;
1573                 }
1574         }
1575         if (getenv("eth1addr")) {
1576                 ret = gpio_request_array(tx6ul_fec2_gpios,
1577                                          ARRAY_SIZE(tx6ul_fec2_gpios));
1578                 if (ret < 0) {
1579                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1580                 }
1581                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1582                                                  ARRAY_SIZE(tx6ul_enet2_pads));
1583
1584                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1585
1586                 /* Minimum PHY reset duration */
1587                 udelay(100);
1588                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1589                 /* Wait for PHY internal POR to finish */
1590                 udelay(22000);
1591
1592                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1593                 if (ret) {
1594                         printf("failed to initialize FEC1: %d\n", ret);
1595                         return ret;
1596                 }
1597         }
1598         return 0;
1599 }
1600 #endif /* CONFIG_FEC_MXC */
1601
1602 #ifdef CONFIG_SERIAL_TAG
1603 void get_board_serial(struct tag_serialnr *serialnr)
1604 {
1605         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1606         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1607
1608         serialnr->low = readl(&fuse->cfg0);
1609         serialnr->high = readl(&fuse->cfg1);
1610 }
1611 #endif
1612
1613 #if defined(CONFIG_OF_BOARD_SETUP)
1614 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1615 #include <jffs2/jffs2.h>
1616 #include <mtd_node.h>
1617 static struct node_info nodes[] = {
1618         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1619 };
1620 #else
1621 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1622 #endif
1623
1624 static const char *tx6ul_touchpanels[] = {
1625         "ti,tsc2007",
1626         "edt,edt-ft5x06",
1627         "eeti,egalax_ts",
1628 };
1629
1630 int ft_board_setup(void *blob, bd_t *bd)
1631 {
1632         const char *baseboard = getenv("baseboard");
1633         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1634         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1635         int ret;
1636
1637         ret = fdt_increase_size(blob, 4096);
1638         if (ret) {
1639                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1640                 return ret;
1641         }
1642         if (stk5_v5)
1643                 karo_fdt_enable_node(blob, "stk5led", 0);
1644
1645         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1646
1647         karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1648                                   ARRAY_SIZE(tx6ul_touchpanels));
1649         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1650         karo_fdt_fixup_flexcan(blob, stk5_v5);
1651
1652         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1653
1654         return 0;
1655 }
1656 #endif /* CONFIG_OF_BOARD_SETUP */