board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37
  38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
  39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
  40
  41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  42
  43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  46
  47 #ifdef CONFIG_SYS_I2C_SOFT
  48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
  49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
  50 #endif
  51
  52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  70 #ifdef CONFIG_SECURE_BOOT
  71 char __csf_data[0] __attribute__((section(".__csf_data")));
  72 #endif
  73
  74 #define TX6UL_DEFAULT_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  75                                         PAD_CTL_SPEED_MED |             \
  76                                         PAD_CTL_DSE_40ohm |             \
  77                                         PAD_CTL_SRE_FAST)
  78 #define TX6UL_I2C_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  79                                         PAD_CTL_ODE |                   \
  80                                         PAD_CTL_HYS |                   \
  81                                         PAD_CTL_SPEED_LOW |             \
  82                                         PAD_CTL_DSE_34ohm |             \
  83                                         PAD_CTL_SRE_FAST)
  84 #define TX6UL_I2C_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  85                                         PAD_CTL_HYS |                   \
  86                                         PAD_CTL_DSE_34ohm |             \
  87                                         PAD_CTL_SPEED_MED)
  88 #define TX6UL_ENET_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
  89                                         PAD_CTL_DSE_48ohm |             \
  90                                         PAD_CTL_PUS_100K_UP |           \
  91                                         PAD_CTL_SRE_FAST)
  92 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  93                                         PAD_CTL_DSE_60ohm |             \
  94                                         PAD_CTL_SRE_SLOW)
  95 #define TX6UL_GPIO_IN_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  96                                         PAD_CTL_PUS_47K_UP)
  97
  98
  99 static const iomux_v3_cfg_t const tx6ul_pads[] = {
 100         /* UART pads */
 101 #if CONFIG_MXC_UART_BASE == UART1_BASE
 102         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 103         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 104         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 105         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 106 #endif
 107 #if CONFIG_MXC_UART_BASE == UART2_BASE
 108         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 109         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 110         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 111         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 112 #endif
 113 #if CONFIG_MXC_UART_BASE == UART5_BASE
 114         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 115         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 116         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 117         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 118 #endif
 119         /* FEC PHY GPIO functions */
 120         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
 121         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
 122         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
 123 };
 124
 125 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 126         /* FEC functions */
 127         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
 128                                 PAD_CTL_SPEED_MED),
 129         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 130                                 PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED),
 131         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
 132                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
 133                                 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST),
 134         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
 135         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
 136         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
 137         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
 138         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
 139         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
 140         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
 141 };
 142
 143 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
 144         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
 145                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
 146                                 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
 147         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
 148         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
 149         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
 150         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
 151         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
 152         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
 153         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
 154 };
 155
 156 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
 157         /* internal I2C */
 158         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 159                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 160         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 161                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 162 };
 163
 164 static const iomux_v3_cfg_t const tx6ul_i2c_gpio_pads[] = {
 165         /* internal I2C set up for I2C bus recovery */
 166         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 167                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 168         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 169                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 170 };
 171
 172 static const struct gpio const tx6ul_gpios[] = {
 173 #ifdef CONFIG_SYS_I2C_SOFT
 174         /* These two entries are used to forcefully reinitialize the I2C bus */
 175         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 176         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 177 #endif
 178         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 179         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 180         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 181 };
 182
 183 static const struct gpio const tx6ul_fec2_gpios[] = {
 184         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
 185         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
 186 };
 187
 188 #define GPIO_DR 0
 189 #define GPIO_DIR 4
 190 #define GPIO_PSR 8
 191
 192 /* run with default environment */
 193 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
 194 #define SCL_BANK        (TX6UL_I2C1_SCL_GPIO / 32)
 195 #define SDA_BANK        (TX6UL_I2C1_SDA_GPIO / 32)
 196 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 197 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 198
 199 static void * const gpio_ports[] = {
 200         (void *)GPIO1_BASE_ADDR,
 201         (void *)GPIO2_BASE_ADDR,
 202         (void *)GPIO3_BASE_ADDR,
 203         (void *)GPIO4_BASE_ADDR,
 204         (void *)GPIO5_BASE_ADDR,
 205 };
 206
 207 static void tx6ul_i2c_recover(void)
 208 {
 209         int i;
 210         int bad = 0;
 211         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
 212         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 213
 214         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
 215                 (readl(&sda_regs->gpio_psr) & SDA_BIT))
 216                 return;
 217
 218         debug("Clearing I2C bus\n");
 219         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
 220                 printf("I2C SCL stuck LOW\n");
 221                 bad++;
 222
 223                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 224                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 225
 226                 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
 227                                 MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
 228         }
 229         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
 230                 printf("I2C SDA stuck LOW\n");
 231                 bad++;
 232
 233                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
 234                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 235                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 236
 237                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_gpio_pads,
 238                                                 ARRAY_SIZE(tx6ul_i2c_gpio_pads));
 239
 240                 udelay(5);
 241
 242                 for (i = 0; i < 18; i++) {
 243                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
 244
 245                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 246                         writel(reg, &scl_regs->gpio_dr);
 247                         udelay(5);
 248                         if (reg & SCL_BIT) {
 249                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
 250                                         break;
 251                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
 252                                         break;
 253                                 break;
 254                         }
 255                 }
 256         }
 257         if (bad) {
 258                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
 259                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 260
 261                 if (scl && sda) {
 262                         printf("I2C bus recovery succeeded\n");
 263                 } else {
 264                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
 265                                 scl, sda);
 266                 }
 267                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
 268                                                 ARRAY_SIZE(tx6ul_i2c_pads));
 269         }
 270 }
 271 #else
 272 static inline void tx6ul_i2c_recover(void)
 273 {
 274 }
 275 #endif
 276
 277 /* placed in section '.data' to prevent overwriting relocation info
 278  * overlayed with bss
 279  */
 280 static u32 wrsr __data;
 281
 282 #define WRSR_POR                        (1 << 4)
 283 #define WRSR_TOUT                       (1 << 1)
 284 #define WRSR_SFTW                       (1 << 0)
 285
 286 static void print_reset_cause(void)
 287 {
 288         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 289         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 290         u32 srsr;
 291         char *dlm = "";
 292
 293         printf("Reset cause: ");
 294
 295         srsr = readl(&src_regs->srsr);
 296         wrsr = readw(wdt_base + 4);
 297
 298         if (wrsr & WRSR_POR) {
 299                 printf("%sPOR", dlm);
 300                 dlm = " | ";
 301         }
 302         if (srsr & 0x00004) {
 303                 printf("%sCSU", dlm);
 304                 dlm = " | ";
 305         }
 306         if (srsr & 0x00008) {
 307                 printf("%sIPP USER", dlm);
 308                 dlm = " | ";
 309         }
 310         if (srsr & 0x00010) {
 311                 if (wrsr & WRSR_SFTW) {
 312                         printf("%sSOFT", dlm);
 313                         dlm = " | ";
 314                 }
 315                 if (wrsr & WRSR_TOUT) {
 316                         printf("%sWDOG", dlm);
 317                         dlm = " | ";
 318                 }
 319         }
 320         if (srsr & 0x00020) {
 321                 printf("%sJTAG HIGH-Z", dlm);
 322                 dlm = " | ";
 323         }
 324         if (srsr & 0x00040) {
 325                 printf("%sJTAG SW", dlm);
 326                 dlm = " | ";
 327         }
 328         if (srsr & 0x10000) {
 329                 printf("%sWARM BOOT", dlm);
 330                 dlm = " | ";
 331         }
 332         if (dlm[0] == '\0')
 333                 printf("unknown");
 334
 335         printf("\n");
 336 }
 337
 338 #ifdef CONFIG_IMX6_THERMAL
 339 #include <thermal.h>
 340 #include <imx_thermal.h>
 341 #include <fuse.h>
 342
 343 static void print_temperature(void)
 344 {
 345         struct udevice *thermal_dev;
 346         int cpu_tmp, minc, maxc, ret;
 347         char const *grade_str;
 348         static u32 __data thermal_calib;
 349
 350         puts("Temperature: ");
 351         switch (get_cpu_temp_grade(&minc, &maxc)) {
 352         case TEMP_AUTOMOTIVE:
 353                 grade_str = "Automotive";
 354                 break;
 355         case TEMP_INDUSTRIAL:
 356                 grade_str = "Industrial";
 357                 break;
 358         case TEMP_EXTCOMMERCIAL:
 359                 grade_str = "Extended Commercial";
 360                 break;
 361         default:
 362                 grade_str = "Commercial";
 363         }
 364         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 365         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 366         if (ret == 0) {
 367                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 368
 369                 if (ret == 0)
 370                         printf(" at %dC", cpu_tmp);
 371                 else
 372                         puts(" - failed to read sensor data");
 373         } else {
 374                 puts(" - no sensor device found");
 375         }
 376
 377         if (fuse_read(1, 6, &thermal_calib) == 0) {
 378                 printf(" - calibration data 0x%08x\n", thermal_calib);
 379         } else {
 380                 puts(" - Failed to read thermal calib fuse\n");
 381         }
 382 }
 383 #else
 384 static inline void print_temperature(void)
 385 {
 386 }
 387 #endif
 388
 389 int checkboard(void)
 390 {
 391         u32 cpurev = get_cpu_rev();
 392         char *cpu_str = "?";
 393
 394         if (is_cpu_type(MXC_CPU_MX6SL))
 395                 cpu_str = "SL";
 396         else if (is_cpu_type(MXC_CPU_MX6DL))
 397                 cpu_str = "DL";
 398         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 399                 cpu_str = "SOLO";
 400         else if (is_cpu_type(MXC_CPU_MX6Q))
 401                 cpu_str = "Q";
 402         else if (is_cpu_type(MXC_CPU_MX6UL))
 403                 cpu_str = "UL";
 404         else if (is_cpu_type(MXC_CPU_MX6ULL))
 405                 cpu_str = "ULL";
 406
 407         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 408                 cpu_str,
 409                 (cpurev & 0x000F0) >> 4,
 410                 (cpurev & 0x0000F) >> 0,
 411                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 412
 413         print_temperature();
 414         print_reset_cause();
 415 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 416         check_cpu_temperature(1);
 417 #endif
 418         tx6ul_i2c_recover();
 419         return 0;
 420 }
 421
 422 /* serial port not initialized at this point */
 423 int board_early_init_f(void)
 424 {
 425         return 0;
 426 }
 427
 428 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 429 static bool tx6ul_temp_check_enabled = true;
 430 #else
 431 #define tx6ul_temp_check_enabled        0
 432 #endif
 433
 434 static inline u8 tx6ul_mem_suffix(void)
 435 {
 436         return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
 437                 IS_ENABLED(CONFIG_TX6_EMMC);
 438 }
 439
 440 #ifdef CONFIG_RN5T567
 441 /* PMIC settings */
 442 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 443 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
 444 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 445 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
 446 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 447 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval(3300)         /* DCDC4 */
 448 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval(3300)
 449 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
 450 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
 451 #define VDD_ADC_VAL             rn5t_mV_to_regval2(3300)        /* LDO2 */
 452 #define VDD_ADC_VAL_LP          rn5t_mV_to_regval2(3300)
 453 #define VDD_PMIC_VAL            rn5t_mV_to_regval2(2500)        /* LDO3 */
 454 #define VDD_PMIC_VAL_LP         rn5t_mV_to_regval2(2500)
 455 #define VDD_CSI_VAL             rn5t_mV_to_regval2(1800)        /* LDO4 */
 456 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(1800)
 457
 458 static struct pmic_regs rn5t567_regs[] = {
 459         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
 460         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 461         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 462         { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
 463         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 464         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 465         { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
 466         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 467         { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
 468         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 469         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 470         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 471         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 472         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
 473         { RN5T567_LDO2DAC, VDD_ADC_VAL, },
 474         { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
 475         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
 476         { RN5T567_LDOEN1, 0x0f, ~0x1f, },
 477         { RN5T567_LDOEN2, 0x10, ~0x30, },
 478         { RN5T567_LDODIS, 0x10, ~0x1f, },
 479         { RN5T567_INTPOL, 0, },
 480         { RN5T567_INTEN, 0x3, },
 481         { RN5T567_IREN, 0xf, },
 482         { RN5T567_EN_GPIR, 0, },
 483 };
 484
 485 static int pmic_addr = 0x33;
 486 #endif
 487
 488 int board_init(void)
 489 {
 490         int ret;
 491         u32 cpurev = get_cpu_rev();
 492         char f = '?';
 493
 494         if (is_cpu_type(MXC_CPU_MX6UL))
 495                 f = ((cpurev & 0xf0) > 0x10) ? '5' : '0';
 496         else if (is_cpu_type(MXC_CPU_MX6ULL))
 497                 f = '8';
 498
 499         debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
 500
 501         printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
 502
 503         get_hab_status();
 504
 505         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 506         if (ret < 0)
 507                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 508
 509         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 510
 511         /* Address of boot parameters */
 512         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 513         gd->bd->bi_arch_number = -1;
 514
 515         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 516                 if (wrsr & WRSR_TOUT)
 517                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 518                 else
 519                         printf("<CTRL-C> detected; safeboot enabled\n");
 520 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 521                 tx6ul_temp_check_enabled = false;
 522 #endif
 523                 return 0;
 524         }
 525
 526         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
 527         if (ret) {
 528                 printf("Failed to setup PMIC voltages: %d\n", ret);
 529                 hang();
 530         }
 531         return 0;
 532 }
 533
 534 int dram_init(void)
 535 {
 536         debug("%s@%d: \n", __func__, __LINE__);
 537
 538         /* dram_init must store complete ramsize in gd->ram_size */
 539         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 540                                     PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 541         return 0;
 542 }
 543
 544 void dram_init_banksize(void)
 545 {
 546         debug("%s@%d: \n", __func__, __LINE__);
 547
 548         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 549         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 550                         PHYS_SDRAM_1_SIZE);
 551 #if CONFIG_NR_DRAM_BANKS > 1
 552         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 553         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 554                         PHYS_SDRAM_2_SIZE);
 555 #endif
 556 }
 557
 558 #ifdef  CONFIG_FSL_ESDHC
 559 #define TX6UL_SD_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
 560                                         PAD_CTL_SPEED_MED |             \
 561                                         PAD_CTL_DSE_40ohm |             \
 562                                         PAD_CTL_SRE_FAST)
 563
 564 static const iomux_v3_cfg_t mmc0_pads[] = {
 565         MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
 566         MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
 567         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
 568         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
 569         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
 570         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
 571         /* SD1 CD */
 572         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
 573 };
 574
 575 #ifdef CONFIG_TX6_EMMC
 576 static const iomux_v3_cfg_t mmc1_pads[] = {
 577         MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
 578         MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
 579         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
 580         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
 581         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
 582         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
 583         /* eMMC RESET */
 584         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 585                                                 PAD_CTL_DSE_40ohm),
 586 };
 587 #endif
 588
 589 static struct tx6ul_esdhc_cfg {
 590         const iomux_v3_cfg_t *pads;
 591         int num_pads;
 592         enum mxc_clock clkid;
 593         struct fsl_esdhc_cfg cfg;
 594         int cd_gpio;
 595 } tx6ul_esdhc_cfg[] = {
 596 #ifdef CONFIG_TX6_EMMC
 597         {
 598                 .pads = mmc1_pads,
 599                 .num_pads = ARRAY_SIZE(mmc1_pads),
 600                 .clkid = MXC_ESDHC2_CLK,
 601                 .cfg = {
 602                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 603                         .max_bus_width = 4,
 604                 },
 605                 .cd_gpio = -EINVAL,
 606         },
 607 #endif
 608         {
 609                 .pads = mmc0_pads,
 610                 .num_pads = ARRAY_SIZE(mmc0_pads),
 611                 .clkid = MXC_ESDHC_CLK,
 612                 .cfg = {
 613                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 614                         .max_bus_width = 4,
 615                 },
 616                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 617         },
 618 };
 619
 620 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 621 {
 622         return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
 623 }
 624
 625 int board_mmc_getcd(struct mmc *mmc)
 626 {
 627         struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
 628
 629         if (cfg->cd_gpio < 0)
 630                 return 1;
 631
 632         debug("SD card %d is %spresent (GPIO %d)\n",
 633                 cfg - tx6ul_esdhc_cfg,
 634                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 635                 cfg->cd_gpio);
 636         return !gpio_get_value(cfg->cd_gpio);
 637 }
 638
 639 int board_mmc_init(bd_t *bis)
 640 {
 641         int i;
 642
 643         debug("%s@%d: \n", __func__, __LINE__);
 644
 645 #ifndef CONFIG_ENV_IS_IN_MMC
 646         if (!(gd->flags & GD_FLG_ENV_READY)) {
 647                 printf("deferred ...");
 648                 return 0;
 649         }
 650 #endif
 651         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 652                 struct mmc *mmc;
 653                 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 654                 int ret;
 655
 656                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 657                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 658
 659                 if (cfg->cd_gpio >= 0) {
 660                         ret = gpio_request_one(cfg->cd_gpio,
 661                                         GPIOFLAG_INPUT, "MMC CD");
 662                         if (ret) {
 663                                 printf("Error %d requesting GPIO%d_%d\n",
 664                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 665                                 continue;
 666                         }
 667                 }
 668
 669                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 670                 fsl_esdhc_initialize(bis, &cfg->cfg);
 671
 672                 mmc = find_mmc_device(i);
 673                 if (mmc == NULL)
 674                         continue;
 675                 if (board_mmc_getcd(mmc))
 676                         mmc_init(mmc);
 677         }
 678         return 0;
 679 }
 680 #endif /* CONFIG_FSL_ESDHC */
 681
 682 enum {
 683         LED_STATE_INIT = -1,
 684         LED_STATE_OFF,
 685         LED_STATE_ON,
 686         LED_STATE_ERR,
 687 };
 688
 689 static inline int calc_blink_rate(void)
 690 {
 691         if (!tx6ul_temp_check_enabled)
 692                 return CONFIG_SYS_HZ;
 693
 694         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 695                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 696                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 697 }
 698
 699 void show_activity(int arg)
 700 {
 701         static int led_state = LED_STATE_INIT;
 702         static int blink_rate;
 703         static ulong last;
 704         int ret;
 705
 706         switch (led_state) {
 707         case LED_STATE_ERR:
 708                 return;
 709
 710         case LED_STATE_INIT:
 711                 last = get_timer(0);
 712                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
 713                 if (ret)
 714                         led_state = LED_STATE_ERR;
 715                 else
 716                         led_state = LED_STATE_ON;
 717                 blink_rate = calc_blink_rate();
 718                 break;
 719
 720         case LED_STATE_ON:
 721         case LED_STATE_OFF:
 722                 if (get_timer(last) > blink_rate) {
 723                         blink_rate = calc_blink_rate();
 724                         last = get_timer_masked();
 725                         if (led_state == LED_STATE_ON) {
 726                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 727                         } else {
 728                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 729                         }
 730                         led_state = 1 - led_state;
 731                 }
 732                 break;
 733         }
 734 }
 735
 736 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
 737         MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
 738         MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
 739         MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
 740         MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
 741         MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
 742         MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
 743 };
 744
 745 static const iomux_v3_cfg_t stk5_pads[] = {
 746         /* SW controlled LED on STK5 baseboard */
 747         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 748
 749         /* I2C bus on DIMM pins 40/41 */
 750         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 751         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 752
 753         /* TSC200x PEN IRQ */
 754         MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
 755
 756         /* EDT-FT5x06 Polytouch panel */
 757         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
 758         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
 759         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
 760
 761         /* USBH1 */
 762         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 763         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 764
 765         /* USBOTG */
 766         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 767         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 768 };
 769
 770 static const struct gpio stk5_gpios[] = {
 771         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 772
 773         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
 774         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 775 };
 776
 777 #ifdef CONFIG_LCD
 778 vidinfo_t panel_info = {
 779         /* set to max. size supported by SoC */
 780         .vl_col = 4096,
 781         .vl_row = 1024,
 782
 783         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 784 };
 785
 786 static struct fb_videomode tx6ul_fb_modes[] = {
 787 #ifndef CONFIG_SYS_LVDS_IF
 788         {
 789                 /* Standard VGA timing */
 790                 .name           = "VGA",
 791                 .refresh        = 60,
 792                 .xres           = 640,
 793                 .yres           = 480,
 794                 .pixclock       = KHZ2PICOS(25175),
 795                 .left_margin    = 48,
 796                 .hsync_len      = 96,
 797                 .right_margin   = 16,
 798                 .upper_margin   = 31,
 799                 .vsync_len      = 2,
 800                 .lower_margin   = 12,
 801                 .sync           = FB_SYNC_CLK_LAT_FALL,
 802         },
 803         {
 804                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 805                  * DE high active, 115.2 mm x 86.4 mm display area
 806                  * VGA compatible timing
 807                  */
 808                 .name           = "ETV570",
 809                 .refresh        = 60,
 810                 .xres           = 640,
 811                 .yres           = 480,
 812                 .pixclock       = KHZ2PICOS(25175),
 813                 .left_margin    = 114,
 814                 .hsync_len      = 30,
 815                 .right_margin   = 16,
 816                 .upper_margin   = 32,
 817                 .vsync_len      = 3,
 818                 .lower_margin   = 10,
 819                 .sync           = FB_SYNC_CLK_LAT_FALL,
 820         },
 821         {
 822                 /* Emerging ET0350G0DH6 320 x 240 display.
 823                  * 70.08 mm x 52.56 mm display area.
 824                  */
 825                 .name           = "ET0350",
 826                 .refresh        = 60,
 827                 .xres           = 320,
 828                 .yres           = 240,
 829                 .pixclock       = KHZ2PICOS(6500),
 830                 .left_margin    = 68 - 34,
 831                 .hsync_len      = 34,
 832                 .right_margin   = 20,
 833                 .upper_margin   = 18 - 3,
 834                 .vsync_len      = 3,
 835                 .lower_margin   = 4,
 836                 .sync           = FB_SYNC_CLK_LAT_FALL,
 837         },
 838         {
 839                 /* Emerging ET0430G0DH6 480 x 272 display.
 840                  * 95.04 mm x 53.856 mm display area.
 841                  */
 842                 .name           = "ET0430",
 843                 .refresh        = 60,
 844                 .xres           = 480,
 845                 .yres           = 272,
 846                 .pixclock       = KHZ2PICOS(9000),
 847                 .left_margin    = 2,
 848                 .hsync_len      = 41,
 849                 .right_margin   = 2,
 850                 .upper_margin   = 2,
 851                 .vsync_len      = 10,
 852                 .lower_margin   = 2,
 853         },
 854         {
 855                 /* Emerging ET0500G0DH6 800 x 480 display.
 856                  * 109.6 mm x 66.4 mm display area.
 857                  */
 858                 .name           = "ET0500",
 859                 .refresh        = 60,
 860                 .xres           = 800,
 861                 .yres           = 480,
 862                 .pixclock       = KHZ2PICOS(33260),
 863                 .left_margin    = 216 - 128,
 864                 .hsync_len      = 128,
 865                 .right_margin   = 1056 - 800 - 216,
 866                 .upper_margin   = 35 - 2,
 867                 .vsync_len      = 2,
 868                 .lower_margin   = 525 - 480 - 35,
 869                 .sync           = FB_SYNC_CLK_LAT_FALL,
 870         },
 871         {
 872                 /* Emerging ETQ570G0DH6 320 x 240 display.
 873                  * 115.2 mm x 86.4 mm display area.
 874                  */
 875                 .name           = "ETQ570",
 876                 .refresh        = 60,
 877                 .xres           = 320,
 878                 .yres           = 240,
 879                 .pixclock       = KHZ2PICOS(6400),
 880                 .left_margin    = 38,
 881                 .hsync_len      = 30,
 882                 .right_margin   = 30,
 883                 .upper_margin   = 16, /* 15 according to datasheet */
 884                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 885                 .lower_margin   = 4, /* 4.5 according to datasheet */
 886                 .sync           = FB_SYNC_CLK_LAT_FALL,
 887         },
 888         {
 889                 /* Emerging ET0700G0DH6 800 x 480 display.
 890                  * 152.4 mm x 91.44 mm display area.
 891                  */
 892                 .name           = "ET0700",
 893                 .refresh        = 60,
 894                 .xres           = 800,
 895                 .yres           = 480,
 896                 .pixclock       = KHZ2PICOS(33260),
 897                 .left_margin    = 216 - 128,
 898                 .hsync_len      = 128,
 899                 .right_margin   = 1056 - 800 - 216,
 900                 .upper_margin   = 35 - 2,
 901                 .vsync_len      = 2,
 902                 .lower_margin   = 525 - 480 - 35,
 903                 .sync           = FB_SYNC_CLK_LAT_FALL,
 904         },
 905         {
 906                 /* Emerging ET070001DM6 800 x 480 display.
 907                  * 152.4 mm x 91.44 mm display area.
 908                  */
 909                 .name           = "ET070001DM6",
 910                 .refresh        = 60,
 911                 .xres           = 800,
 912                 .yres           = 480,
 913                 .pixclock       = KHZ2PICOS(33260),
 914                 .left_margin    = 216 - 128,
 915                 .hsync_len      = 128,
 916                 .right_margin   = 1056 - 800 - 216,
 917                 .upper_margin   = 35 - 2,
 918                 .vsync_len      = 2,
 919                 .lower_margin   = 525 - 480 - 35,
 920                 .sync           = 0,
 921         },
 922 #else
 923         {
 924                 /* HannStar HSD100PXN1
 925                  * 202.7m mm x 152.06 mm display area.
 926                  */
 927                 .name           = "HSD100PXN1",
 928                 .refresh        = 60,
 929                 .xres           = 1024,
 930                 .yres           = 768,
 931                 .pixclock       = KHZ2PICOS(65000),
 932                 .left_margin    = 0,
 933                 .hsync_len      = 0,
 934                 .right_margin   = 320,
 935                 .upper_margin   = 0,
 936                 .vsync_len      = 0,
 937                 .lower_margin   = 38,
 938                 .sync           = FB_SYNC_CLK_LAT_FALL,
 939         },
 940 #endif
 941         {
 942                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 943                 .refresh        = 60,
 944                 .left_margin    = 48,
 945                 .hsync_len      = 96,
 946                 .right_margin   = 16,
 947                 .upper_margin   = 31,
 948                 .vsync_len      = 2,
 949                 .lower_margin   = 12,
 950                 .sync           = FB_SYNC_CLK_LAT_FALL,
 951         },
 952 };
 953
 954 static int lcd_enabled = 1;
 955 static int lcd_bl_polarity;
 956
 957 static int lcd_backlight_polarity(void)
 958 {
 959         return lcd_bl_polarity;
 960 }
 961
 962 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 963 #ifdef CONFIG_LCD
 964         /* LCD RESET */
 965         MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
 966         /* LCD POWER_ENABLE */
 967         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
 968         /* LCD Backlight (PWM) */
 969         MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
 970         /* Display */
 971         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
 972         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
 973         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
 974         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
 975         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
 976         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
 977         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
 978         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
 979         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
 980         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
 981         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
 982         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
 983         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
 984         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
 985         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
 986         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
 987         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
 988         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
 989         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
 990         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
 991         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
 992         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
 993         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
 994         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
 995         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
 996         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
 997         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
 998         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
 999 #endif
1000 };
1001
1002 static const struct gpio stk5_lcd_gpios[] = {
1003         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1004         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1005         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1006 };
1007
1008 /* run with valid env from NAND/eMMC */
1009 void lcd_enable(void)
1010 {
1011         /* HACK ALERT:
1012          * global variable from common/lcd.c
1013          * Set to 0 here to prevent messages from going to LCD
1014          * rather than serial console
1015          */
1016         lcd_is_enabled = 0;
1017
1018         if (lcd_enabled) {
1019                 karo_load_splashimage(1);
1020
1021                 debug("Switching LCD on\n");
1022                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1023                 udelay(100);
1024                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1025                 udelay(300000);
1026                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1027                         lcd_backlight_polarity());
1028         }
1029 }
1030
1031 static void lcd_disable(void)
1032 {
1033         if (lcd_enabled) {
1034                 printf("Disabling LCD\n");
1035                 panel_info.vl_row = 0;
1036                 lcd_enabled = 0;
1037         }
1038 }
1039
1040 void lcd_ctrl_init(void *lcdbase)
1041 {
1042         int color_depth = 24;
1043         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1044         const char *vm;
1045         unsigned long val;
1046         int refresh = 60;
1047         struct fb_videomode *p = &tx6ul_fb_modes[0];
1048         struct fb_videomode fb_mode;
1049         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1050
1051         if (!lcd_enabled) {
1052                 debug("LCD disabled\n");
1053                 return;
1054         }
1055
1056         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1057                 lcd_disable();
1058                 setenv("splashimage", NULL);
1059                 return;
1060         }
1061
1062         karo_fdt_move_fdt();
1063         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1064
1065         if (video_mode == NULL) {
1066                 lcd_disable();
1067                 return;
1068         }
1069         vm = video_mode;
1070         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1071                 p = &fb_mode;
1072                 debug("Using video mode from FDT\n");
1073                 vm += strlen(vm);
1074                 if (fb_mode.xres > panel_info.vl_col ||
1075                         fb_mode.yres > panel_info.vl_row) {
1076                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1077                                 fb_mode.xres, fb_mode.yres,
1078                                 panel_info.vl_col, panel_info.vl_row);
1079                         lcd_enabled = 0;
1080                         return;
1081                 }
1082         }
1083         if (p->name != NULL)
1084                 debug("Trying compiled-in video modes\n");
1085         while (p->name != NULL) {
1086                 if (strcmp(p->name, vm) == 0) {
1087                         debug("Using video mode: '%s'\n", p->name);
1088                         vm += strlen(vm);
1089                         break;
1090                 }
1091                 p++;
1092         }
1093         if (*vm != '\0')
1094                 debug("Trying to decode video_mode: '%s'\n", vm);
1095         while (*vm != '\0') {
1096                 if (*vm >= '0' && *vm <= '9') {
1097                         char *end;
1098
1099                         val = simple_strtoul(vm, &end, 0);
1100                         if (end > vm) {
1101                                 if (!xres_set) {
1102                                         if (val > panel_info.vl_col)
1103                                                 val = panel_info.vl_col;
1104                                         p->xres = val;
1105                                         panel_info.vl_col = val;
1106                                         xres_set = 1;
1107                                 } else if (!yres_set) {
1108                                         if (val > panel_info.vl_row)
1109                                                 val = panel_info.vl_row;
1110                                         p->yres = val;
1111                                         panel_info.vl_row = val;
1112                                         yres_set = 1;
1113                                 } else if (!bpp_set) {
1114                                         switch (val) {
1115                                         case 8:
1116                                         case 16:
1117                                         case 18:
1118                                         case 24:
1119                                         case 32:
1120                                                 color_depth = val;
1121                                                 break;
1122
1123                                         default:
1124                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1125                                                         end - vm, vm, color_depth);
1126                                         }
1127                                         bpp_set = 1;
1128                                 } else if (!refresh_set) {
1129                                         refresh = val;
1130                                         refresh_set = 1;
1131                                 }
1132                         }
1133                         vm = end;
1134                 }
1135                 switch (*vm) {
1136                 case '@':
1137                         bpp_set = 1;
1138                         /* fallthru */
1139                 case '-':
1140                         yres_set = 1;
1141                         /* fallthru */
1142                 case 'x':
1143                         xres_set = 1;
1144                         /* fallthru */
1145                 case 'M':
1146                 case 'R':
1147                         vm++;
1148                         break;
1149
1150                 default:
1151                         if (*vm != '\0')
1152                                 vm++;
1153                 }
1154         }
1155         if (p->xres == 0 || p->yres == 0) {
1156                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1157                 lcd_enabled = 0;
1158                 printf("Supported video modes are:");
1159                 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1160                         printf(" %s", p->name);
1161                 }
1162                 printf("\n");
1163                 return;
1164         }
1165         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1166                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1167                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1168                 lcd_enabled = 0;
1169                 return;
1170         }
1171         panel_info.vl_col = p->xres;
1172         panel_info.vl_row = p->yres;
1173
1174         switch (color_depth) {
1175         case 8:
1176                 panel_info.vl_bpix = LCD_COLOR8;
1177                 break;
1178         case 16:
1179                 panel_info.vl_bpix = LCD_COLOR16;
1180                 break;
1181         default:
1182                 panel_info.vl_bpix = LCD_COLOR32;
1183         }
1184
1185         p->pixclock = KHZ2PICOS(refresh *
1186                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1187                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1188                                 1000);
1189         debug("Pixel clock set to %lu.%03lu MHz\n",
1190                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1191
1192         if (p != &fb_mode) {
1193                 int ret;
1194
1195                 debug("Creating new display-timing node from '%s'\n",
1196                         video_mode);
1197                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1198                 if (ret)
1199                         printf("Failed to create new display-timing node from '%s': %d\n",
1200                                 video_mode, ret);
1201         }
1202
1203         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1204         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1205                                         ARRAY_SIZE(stk5_lcd_pads));
1206
1207         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1208                 color_depth, refresh);
1209
1210         if (karo_load_splashimage(0) == 0) {
1211                 char vmode[128];
1212
1213                 /* setup env variable for mxsfb display driver */
1214                 snprintf(vmode, sizeof(vmode),
1215                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1216                         p->xres, p->yres, p->left_margin, p->right_margin,
1217                         p->upper_margin, p->lower_margin, p->hsync_len,
1218                         p->vsync_len, p->sync, p->pixclock, color_depth);
1219                 setenv("videomode", vmode);
1220
1221                 debug("Initializing LCD controller\n");
1222                 lcdif_clk_enable();
1223                 video_hw_init();
1224                 setenv("videomode", NULL);
1225         } else {
1226                 debug("Skipping initialization of LCD controller\n");
1227         }
1228 }
1229 #else
1230 #define lcd_enabled 0
1231 #endif /* CONFIG_LCD */
1232
1233 #ifndef CONFIG_ENV_IS_IN_MMC
1234 static void tx6ul_mmc_init(void)
1235 {
1236         puts("MMC:   ");
1237         if (board_mmc_init(gd->bd) < 0)
1238                 cpu_mmc_init(gd->bd);
1239         print_mmc_devices(',');
1240 }
1241 #else
1242 static inline void tx6ul_mmc_init(void)
1243 {
1244 }
1245 #endif
1246
1247 static void stk5_board_init(void)
1248 {
1249         int ret;
1250
1251         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1252         if (ret < 0) {
1253                 printf("Failed to request stk5_gpios: %d\n", ret);
1254                 return;
1255         }
1256
1257         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1258         if (getenv_yesno("jtag_enable") != 0) {
1259                 /* true if unset or set to one of: 'yYtT1' */
1260                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1261         }
1262
1263         debug("%s@%d: \n", __func__, __LINE__);
1264 }
1265
1266 static void stk5v3_board_init(void)
1267 {
1268         debug("%s@%d: \n", __func__, __LINE__);
1269         stk5_board_init();
1270         debug("%s@%d: \n", __func__, __LINE__);
1271         tx6ul_mmc_init();
1272 }
1273
1274 static void stk5v5_board_init(void)
1275 {
1276         int ret;
1277
1278         stk5_board_init();
1279         tx6ul_mmc_init();
1280
1281         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1282                         "Flexcan Transceiver");
1283         if (ret) {
1284                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1285                 return;
1286         }
1287
1288         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1289                         TX6UL_GPIO_OUT_PAD_CTRL);
1290 }
1291
1292 static void tx6ul_set_cpu_clock(void)
1293 {
1294         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1295
1296         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1297                 return;
1298
1299         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1300                 printf("%s detected; skipping cpu clock change\n",
1301                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1302                 return;
1303         }
1304         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1305                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1306                 printf("CPU clock set to %lu.%03lu MHz\n",
1307                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1308         } else {
1309                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1310         }
1311 }
1312
1313 int board_late_init(void)
1314 {
1315         const char *baseboard;
1316
1317         debug("%s@%d: \n", __func__, __LINE__);
1318
1319         env_cleanup();
1320
1321         if (tx6ul_temp_check_enabled)
1322                 check_cpu_temperature(1);
1323
1324         tx6ul_set_cpu_clock();
1325
1326         if (had_ctrlc())
1327                 setenv_ulong("safeboot", 1);
1328         else if (wrsr & WRSR_TOUT)
1329                 setenv_ulong("wdreset", 1);
1330         else
1331                 karo_fdt_move_fdt();
1332
1333         baseboard = getenv("baseboard");
1334         if (!baseboard)
1335                 goto exit;
1336
1337         printf("Baseboard: %s\n", baseboard);
1338
1339         if (strncmp(baseboard, "stk5", 4) == 0) {
1340                 if ((strlen(baseboard) == 4) ||
1341                         strcmp(baseboard, "stk5-v3") == 0) {
1342                         stk5v3_board_init();
1343                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1344                         const char *otg_mode = getenv("otg_mode");
1345
1346                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1347                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1348                                         otg_mode, baseboard);
1349                                 setenv("otg_mode", "none");
1350                         }
1351                         stk5v5_board_init();
1352                 } else {
1353                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1354                                 baseboard + 4);
1355                 }
1356         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1357                         const char *otg_mode = getenv("otg_mode");
1358
1359                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1360                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1361                                         otg_mode, baseboard);
1362                                 setenv("otg_mode", "none");
1363                         }
1364                         stk5_board_init();
1365         } else {
1366                 printf("WARNING: Unsupported baseboard: '%s'\n",
1367                         baseboard);
1368                 if (!had_ctrlc())
1369                         return -EINVAL;
1370         }
1371
1372 exit:
1373         debug("%s@%d: \n", __func__, __LINE__);
1374
1375         clear_ctrlc();
1376         return 0;
1377 }
1378
1379 #ifdef CONFIG_FEC_MXC
1380
1381 #ifndef ETH_ALEN
1382 #define ETH_ALEN 6
1383 #endif
1384
1385 static void tx6ul_init_mac(void)
1386 {
1387         u8 mac[ETH_ALEN];
1388         const char *baseboard = getenv("baseboard");
1389
1390         imx_get_mac_from_fuse(0, mac);
1391         if (!is_valid_ethaddr(mac)) {
1392                 printf("No valid MAC address programmed\n");
1393                 return;
1394         }
1395         printf("MAC addr from fuse: %pM\n", mac);
1396         if (!getenv("ethaddr"))
1397                 eth_setenv_enetaddr("ethaddr", mac);
1398
1399         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1400                 setenv("eth1addr", NULL);
1401                 return;
1402         }
1403         if (getenv("eth1addr"))
1404                 return;
1405         imx_get_mac_from_fuse(1, mac);
1406         eth_setenv_enetaddr("eth1addr", mac);
1407 }
1408
1409 int board_eth_init(bd_t *bis)
1410 {
1411         int ret;
1412
1413         tx6ul_init_mac();
1414
1415         /* delay at least 21ms for the PHY internal POR signal to deassert */
1416         udelay(22000);
1417
1418         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1419                                         ARRAY_SIZE(tx6ul_enet1_pads));
1420
1421         /* Deassert RESET to the external phys */
1422         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1423
1424         if (getenv("ethaddr")) {
1425                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1426                 if (ret) {
1427                         printf("failed to initialize FEC0: %d\n", ret);
1428                         return ret;
1429                 }
1430         }
1431         if (getenv("eth1addr")) {
1432                 ret = gpio_request_array(tx6ul_fec2_gpios,
1433                                         ARRAY_SIZE(tx6ul_fec2_gpios));
1434                 if (ret < 0) {
1435                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1436                 }
1437                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1438                                                 ARRAY_SIZE(tx6ul_enet2_pads));
1439
1440                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1441
1442                 /* Minimum PHY reset duration */
1443                 udelay(100);
1444                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1445                 /* Wait for PHY internal POR to finish */
1446                 udelay(22000);
1447
1448                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1449                 if (ret) {
1450                         printf("failed to initialize FEC1: %d\n", ret);
1451                         return ret;
1452                 }
1453         }
1454         return 0;
1455 }
1456 #endif /* CONFIG_FEC_MXC */
1457
1458 #ifdef CONFIG_SERIAL_TAG
1459 void get_board_serial(struct tag_serialnr *serialnr)
1460 {
1461         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1462         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1463
1464         serialnr->low = readl(&fuse->cfg0);
1465         serialnr->high = readl(&fuse->cfg1);
1466 }
1467 #endif
1468
1469 #if defined(CONFIG_OF_BOARD_SETUP)
1470 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1471 #include <jffs2/jffs2.h>
1472 #include <mtd_node.h>
1473 static struct node_info nodes[] = {
1474         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1475 };
1476 #else
1477 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1478 #endif
1479
1480 static const char *tx6ul_touchpanels[] = {
1481         "ti,tsc2007",
1482         "edt,edt-ft5x06",
1483         "eeti,egalax_ts",
1484 };
1485
1486 int ft_board_setup(void *blob, bd_t *bd)
1487 {
1488         const char *baseboard = getenv("baseboard");
1489         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1490         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1491         int ret;
1492
1493         ret = fdt_increase_size(blob, 4096);
1494         if (ret) {
1495                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1496                 return ret;
1497         }
1498         if (stk5_v5)
1499                 karo_fdt_enable_node(blob, "stk5led", 0);
1500
1501         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1502
1503         karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1504                                 ARRAY_SIZE(tx6ul_touchpanels));
1505         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1506         karo_fdt_fixup_flexcan(blob, stk5_v5);
1507
1508         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1509
1510         return 0;
1511 }
1512 #endif /* CONFIG_OF_BOARD_SETUP */