board/renesas/MigoR/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2007-2008
   3  * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
   4  *
   5  * Copyright (C) 2007
   6  * Kenati Technologies, Inc.
   7  *
   8  * board/MigoR/lowlevel_init.S
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <config.h>
  14
  15 #include <asm/processor.h>
  16 #include <asm/macro.h>
  17
  18 /*
  19  * Board specific low level init code, called _very_ early in the
  20  * startup sequence. Relocation to SDRAM has not happened yet, no
  21  * stack is available, bss section has not been initialised, etc.
  22  *
  23  * (Note: As no stack is available, no subroutines can be called...).
  24  */
  25
  26         .global lowlevel_init
  27
  28         .text
  29         .align  2
  30
  31 lowlevel_init:
  32         write32 CCR_A, CCR_D            ! Address of Cache Control Register
  33                                         ! Instruction Cache Invalidate
  34
  35         write32 MMUCR_A, MMUCR_D        ! Address of MMU Control Register
  36                                         ! TI == TLB Invalidate bit
  37
  38         write32 MSTPCR0_A, MSTPCR0_D    ! Address of Power Control Register 0
  39
  40         write32 MSTPCR2_A, MSTPCR2_D    ! Address of Power Control Register 2
  41
  42         write16 PFC_PULCR_A, PFC_PULCR_D
  43
  44         write16 PFC_DRVCR_A, PFC_DRVCR_D
  45
  46         write16 SBSCR_A, SBSCR_D
  47
  48         write16 PSCR_A, PSCR_D
  49
  50         write16 RWTCSR_A, RWTCSR_D_1    ! 0xA4520004 (Watchdog Control / Status Register)
  51                                         ! 0xA507 -> timer_STOP / WDT_CLK = max
  52
  53         write16 RWTCNT_A, RWTCNT_D      ! 0xA4520000 (Watchdog Count Register)
  54                                         ! 0x5A00 -> Clear
  55
  56         write16 RWTCSR_A, RWTCSR_D_2    ! 0xA4520004 (Watchdog Control / Status Register)
  57                                         ! 0xA504 -> timer_STOP / CLK = 500ms
  58
  59         write32 DLLFRQ_A, DLLFRQ_D      ! 20080115
  60                                         ! 20080115
  61
  62         write32 FRQCR_A, FRQCR_D        ! 0xA4150000 Frequency control register
  63                                         ! 20080115
  64
  65         write32 CCR_A, CCR_D_2          ! Address of Cache Control Register
  66                                         ! ??
  67
  68 bsc_init:
  69         write32 CMNCR_A, CMNCR_D
  70
  71         write32 CS0BCR_A, CS0BCR_D
  72
  73         write32 CS4BCR_A, CS4BCR_D
  74
  75         write32 CS5ABCR_A, CS5ABCR_D
  76
  77         write32 CS5BBCR_A, CS5BBCR_D
  78
  79         write32 CS6ABCR_A, CS6ABCR_D
  80
  81         write32 CS0WCR_A, CS0WCR_D
  82
  83         write32 CS4WCR_A, CS4WCR_D
  84
  85         write32 CS5AWCR_A, CS5AWCR_D
  86
  87         write32 CS5BWCR_A, CS5BWCR_D
  88
  89         write32 CS6AWCR_A, CS6AWCR_D
  90
  91         ! SDRAM initialization
  92         write32 SDCR_A, SDCR_D
  93
  94         write32 SDWCR_A, SDWCR_D
  95
  96         write32 SDPCR_A, SDPCR_D
  97
  98         write32 RTCOR_A, RTCOR_D
  99
 100         write32 RTCNT_A, RTCNT_D
 101
 102         write32 RTCSR_A, RTCSR_D
 103
 104         write32 RFCR_A, RFCR_D
 105
 106         write8  SDMR3_A, SDMR3_D
 107
 108         ! BL bit off (init = ON) (?!?)
 109
 110         stc     sr, r0                          ! BL bit off(init=ON)
 111         mov.l   SR_MASK_D, r1
 112         and     r1, r0
 113         ldc     r0, sr
 114
 115         rts
 116         mov     #0, r0
 117
 118         .align  4
 119
 120 CCR_A:          .long   CCR
 121 MMUCR_A:        .long   MMUCR
 122 MSTPCR0_A:      .long   MSTPCR0
 123 MSTPCR2_A:      .long   MSTPCR2
 124 PFC_PULCR_A:    .long   PULCR
 125 PFC_DRVCR_A:    .long   DRVCR
 126 SBSCR_A:        .long   SBSCR
 127 PSCR_A:         .long   PSCR
 128 RWTCSR_A:       .long   RWTCSR
 129 RWTCNT_A:       .long   RWTCNT
 130 FRQCR_A:        .long   FRQCR
 131 PLLCR_A:        .long   PLLCR
 132 DLLFRQ_A:       .long   DLLFRQ
 133
 134 CCR_D:          .long   0x00000800
 135 CCR_D_2:        .long   0x00000103
 136 MMUCR_D:        .long   0x00000004
 137 MSTPCR0_D:      .long   0x00001001
 138 MSTPCR2_D:      .long   0xffffffff
 139 PFC_PULCR_D:    .long   0x6000
 140 PFC_DRVCR_D:    .long   0x0464
 141 FRQCR_D:        .long   0x07033639
 142 PLLCR_D:        .long   0x00005000
 143 DLLFRQ_D:       .long   0x000004F6
 144
 145 CMNCR_A:        .long   CMNCR
 146 CMNCR_D:        .long   0x0000001B
 147 CS0BCR_A:       .long   CS0BCR
 148 CS0BCR_D:       .long   0x24920400
 149 CS4BCR_A:       .long   CS4BCR
 150 CS4BCR_D:       .long   0x00003400
 151 CS5ABCR_A:      .long   CS5ABCR
 152 CS5ABCR_D:      .long   0x24920400
 153 CS5BBCR_A:      .long   CS5BBCR
 154 CS5BBCR_D:      .long   0x24920400
 155 CS6ABCR_A:      .long   CS6ABCR
 156 CS6ABCR_D:      .long   0x24920400
 157
 158 CS0WCR_A:       .long   CS0WCR
 159 CS0WCR_D:       .long   0x00000380
 160 CS4WCR_A:       .long   CS4WCR
 161 CS4WCR_D:       .long   0x00110080
 162 CS5AWCR_A:      .long   CS5AWCR
 163 CS5AWCR_D:      .long   0x00000300
 164 CS5BWCR_A:      .long   CS5BWCR
 165 CS5BWCR_D:      .long   0x00000300
 166 CS6AWCR_A:      .long   CS6AWCR
 167 CS6AWCR_D:      .long   0x00000300
 168
 169 SDCR_A:         .long   SBSC_SDCR
 170 SDCR_D:         .long   0x80160809
 171 SDWCR_A:        .long   SBSC_SDWCR
 172 SDWCR_D:        .long   0x0014450C
 173 SDPCR_A:        .long   SBSC_SDPCR
 174 SDPCR_D:        .long   0x00000087
 175 RTCOR_A:        .long   SBSC_RTCOR
 176 RTCNT_A:        .long   SBSC_RTCNT
 177 RTCNT_D:        .long   0xA55A0012
 178 RTCOR_D:        .long   0xA55A001C
 179 RTCSR_A:        .long   SBSC_RTCSR
 180 RFCR_A:         .long   SBSC_RFCR
 181 RFCR_D:         .long   0xA55A0221
 182 RTCSR_D:        .long   0xA55A009a
 183 SDMR3_A:        .long   0xFE581180
 184 SDMR3_D:        .long   0x0
 185
 186 SR_MASK_D:      .long   0xEFFFFF0F
 187
 188         .align  2
 189
 190 SBSCR_D:        .word   0x0044
 191 PSCR_D:         .word   0x0000
 192 RWTCSR_D_1:     .word   0xA507
 193 RWTCSR_D_2:     .word   0xA504
 194 RWTCNT_D:       .word   0x5A00