board/samsung/smdk5250/smdk5250.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <cros_ec.h>
   9 #include <fdtdec.h>
  10 #include <asm/io.h>
  11 #include <errno.h>
  12 #include <i2c.h>
  13 #include <lcd.h>
  14 #include <netdev.h>
  15 #include <spi.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/dwmmc.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/mmc.h>
  20 #include <asm/arch/pinmux.h>
  21 #include <asm/arch/power.h>
  22 #include <asm/arch/sromc.h>
  23 #include <asm/arch/dp_info.h>
  24 #include <power/pmic.h>
  25 #include <power/max77686_pmic.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_SOUND_MAX98095
  30 static void  board_enable_audio_codec(void)
  31 {
  32         /* Enable MAX98095 Codec */
  33         gpio_direction_output(EXYNOS5_GPIO_X17, 1);
  34         gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
  35 }
  36 #endif
  37
  38 int exynos_init(void)
  39 {
  40 #ifdef CONFIG_SOUND_MAX98095
  41         board_enable_audio_codec();
  42 #endif
  43         return 0;
  44 }
  45
  46 int board_eth_init(bd_t *bis)
  47 {
  48 #ifdef CONFIG_SMC911X
  49         u32 smc_bw_conf, smc_bc_conf;
  50         struct fdt_sromc config;
  51         fdt_addr_t base_addr;
  52
  53         /* Non-FDT configuration - bank number and timing parameters*/
  54         config.bank = CONFIG_ENV_SROM_BANK;
  55         config.width = 2;
  56
  57         config.timing[FDT_SROM_TACS] = 0x01;
  58         config.timing[FDT_SROM_TCOS] = 0x01;
  59         config.timing[FDT_SROM_TACC] = 0x06;
  60         config.timing[FDT_SROM_TCOH] = 0x01;
  61         config.timing[FDT_SROM_TAH] = 0x0C;
  62         config.timing[FDT_SROM_TACP] = 0x09;
  63         config.timing[FDT_SROM_PMC] = 0x01;
  64         base_addr = CONFIG_SMC911X_BASE;
  65
  66         /* Ethernet needs data bus width of 16 bits */
  67         if (config.width != 2) {
  68                 debug("%s: Unsupported bus width %d\n", __func__,
  69                         config.width);
  70                 return -1;
  71         }
  72         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
  73                         | SROMC_BYTE_ENABLE(config.bank);
  74
  75         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
  76                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
  77                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
  78                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
  79                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
  80                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
  81                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
  82
  83         /* Select and configure the SROMC bank */
  84         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
  85         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
  86         return smc911x_initialize(0, base_addr);
  87 #endif
  88         return 0;
  89 }
  90
  91 #ifdef CONFIG_DISPLAY_BOARDINFO
  92 int checkboard(void)
  93 {
  94         printf("\nBoard: SMDK5250\n");
  95         return 0;
  96 }
  97 #endif
  98
  99 #ifdef CONFIG_GENERIC_MMC
 100 int board_mmc_init(bd_t *bis)
 101 {
 102         int err, ret = 0, index, bus_width;
 103         u32 base;
 104
 105         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 106         if (err)
 107                 debug("SDMMC0 not configured\n");
 108         ret |= err;
 109
 110         /*EMMC: dwmmc Channel-0 with 8 bit bus width */
 111         index = 0;
 112         base =  samsung_get_base_mmc() + (0x10000 * index);
 113         bus_width = 8;
 114         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 115         if (err)
 116                 debug("dwmmc Channel-0 init failed\n");
 117         ret |= err;
 118
 119         err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
 120         if (err)
 121                 debug("SDMMC2 not configured\n");
 122         ret |= err;
 123
 124         /*SD: dwmmc Channel-2 with 4 bit bus width */
 125         index = 2;
 126         base = samsung_get_base_mmc() + (0x10000 * index);
 127         bus_width = 4;
 128         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 129         if (err)
 130                 debug("dwmmc Channel-2 init failed\n");
 131         ret |= err;
 132
 133         return ret;
 134 }
 135 #endif
 136
 137 void board_i2c_init(const void *blob)
 138 {
 139         int i;
 140
 141         for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
 142                 exynos_pinmux_config((PERIPH_ID_I2C0 + i),
 143                                      PINMUX_FLAG_NONE);
 144         }
 145 }
 146
 147 #if defined(CONFIG_POWER)
 148 #ifdef CONFIG_POWER_MAX77686
 149 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
 150 {
 151         u32 val;
 152         int ret = 0;
 153
 154         ret = pmic_reg_read(p, reg, &val);
 155         if (ret) {
 156                 debug("%s: PMIC %d register read failed\n", __func__, reg);
 157                 return -1;
 158         }
 159         val |= regval;
 160         ret = pmic_reg_write(p, reg, val);
 161         if (ret) {
 162                 debug("%s: PMIC %d register write failed\n", __func__, reg);
 163                 return -1;
 164         }
 165         return 0;
 166 }
 167
 168 static int max77686_init(void)
 169 {
 170         struct pmic *p;
 171
 172         if (pmic_init(I2C_PMIC))
 173                 return -1;
 174
 175         p = pmic_get("MAX77686_PMIC");
 176         if (!p)
 177                 return -ENODEV;
 178
 179         if (pmic_probe(p))
 180                 return -1;
 181
 182         if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
 183                 return -1;
 184
 185         if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
 186                             MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
 187                 return -1;
 188
 189         /* VDD_MIF */
 190         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
 191                            MAX77686_BUCK1OUT_1V)) {
 192                 debug("%s: PMIC %d register write failed\n", __func__,
 193                       MAX77686_REG_PMIC_BUCK1OUT);
 194                 return -1;
 195         }
 196
 197         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
 198                             MAX77686_BUCK1CTRL_EN))
 199                 return -1;
 200
 201         /* VDD_ARM */
 202         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
 203                            MAX77686_BUCK2DVS1_1_3V)) {
 204                 debug("%s: PMIC %d register write failed\n", __func__,
 205                       MAX77686_REG_PMIC_BUCK2DVS1);
 206                 return -1;
 207         }
 208
 209         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
 210                             MAX77686_BUCK2CTRL_ON))
 211                 return -1;
 212
 213         /* VDD_INT */
 214         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
 215                            MAX77686_BUCK3DVS1_1_0125V)) {
 216                 debug("%s: PMIC %d register write failed\n", __func__,
 217                       MAX77686_REG_PMIC_BUCK3DVS1);
 218                 return -1;
 219         }
 220
 221         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
 222                             MAX77686_BUCK3CTRL_ON))
 223                 return -1;
 224
 225         /* VDD_G3D */
 226         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
 227                            MAX77686_BUCK4DVS1_1_2V)) {
 228                 debug("%s: PMIC %d register write failed\n", __func__,
 229                       MAX77686_REG_PMIC_BUCK4DVS1);
 230                 return -1;
 231         }
 232
 233         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
 234                             MAX77686_BUCK3CTRL_ON))
 235                 return -1;
 236
 237         /* VDD_LDO2 */
 238         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
 239                             MAX77686_LD02CTRL1_1_5V | EN_LDO))
 240                 return -1;
 241
 242         /* VDD_LDO3 */
 243         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
 244                             MAX77686_LD03CTRL1_1_8V | EN_LDO))
 245                 return -1;
 246
 247         /* VDD_LDO5 */
 248         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
 249                             MAX77686_LD05CTRL1_1_8V | EN_LDO))
 250                 return -1;
 251
 252         /* VDD_LDO10 */
 253         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
 254                             MAX77686_LD10CTRL1_1_8V | EN_LDO))
 255                 return -1;
 256
 257         return 0;
 258 }
 259 #endif  /* CONFIG_POWER_MAX77686 */
 260
 261 int exynos_power_init(void)
 262 {
 263         int ret = 0;
 264
 265 #ifdef CONFIG_POWER_MAX77686
 266         ret = max77686_init();
 267 #endif
 268         return ret;
 269 }
 270 #endif  /* CONFIG_POWER */
 271
 272 #ifdef CONFIG_LCD
 273 void exynos_cfg_lcd_gpio(void)
 274 {
 275
 276         /* For Backlight */
 277         gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
 278         gpio_set_value(EXYNOS5_GPIO_B20, 1);
 279
 280         /* LCD power on */
 281         gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
 282         gpio_set_value(EXYNOS5_GPIO_X15, 1);
 283
 284         /* Set Hotplug detect for DP */
 285         gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
 286 }
 287
 288 void exynos_set_dp_phy(unsigned int onoff)
 289 {
 290         set_dp_phy_ctrl(onoff);
 291 }
 292
 293 vidinfo_t panel_info = {
 294         .vl_freq        = 60,
 295         .vl_col         = 2560,
 296         .vl_row         = 1600,
 297         .vl_width       = 2560,
 298         .vl_height      = 1600,
 299         .vl_clkp        = CONFIG_SYS_LOW,
 300         .vl_hsp         = CONFIG_SYS_LOW,
 301         .vl_vsp         = CONFIG_SYS_LOW,
 302         .vl_dp          = CONFIG_SYS_LOW,
 303         .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
 304
 305         /* wDP panel timing infomation */
 306         .vl_hspw        = 32,
 307         .vl_hbpd        = 80,
 308         .vl_hfpd        = 48,
 309
 310         .vl_vspw        = 6,
 311         .vl_vbpd        = 37,
 312         .vl_vfpd        = 3,
 313         .vl_cmd_allow_len = 0xf,
 314
 315         .win_id         = 3,
 316         .dual_lcd_enabled = 0,
 317
 318         .init_delay     = 0,
 319         .power_on_delay = 0,
 320         .reset_delay    = 0,
 321         .interface_mode = FIMD_RGB_INTERFACE,
 322         .dp_enabled     = 1,
 323 };
 324
 325 static struct edp_device_info edp_info = {
 326         .disp_info = {
 327                 .h_res = 2560,
 328                 .h_sync_width = 32,
 329                 .h_back_porch = 80,
 330                 .h_front_porch = 48,
 331                 .v_res = 1600,
 332                 .v_sync_width  = 6,
 333                 .v_back_porch = 37,
 334                 .v_front_porch = 3,
 335                 .v_sync_rate = 60,
 336         },
 337         .lt_info = {
 338                 .lt_status = DP_LT_NONE,
 339         },
 340         .video_info = {
 341                 .master_mode = 0,
 342                 .bist_mode = DP_DISABLE,
 343                 .bist_pattern = NO_PATTERN,
 344                 .h_sync_polarity = 0,
 345                 .v_sync_polarity = 0,
 346                 .interlaced = 0,
 347                 .color_space = COLOR_RGB,
 348                 .dynamic_range = VESA,
 349                 .ycbcr_coeff = COLOR_YCBCR601,
 350                 .color_depth = COLOR_8,
 351         },
 352 };
 353
 354 static struct exynos_dp_platform_data dp_platform_data = {
 355         .edp_dev_info   = &edp_info,
 356 };
 357
 358 void init_panel_info(vidinfo_t *vid)
 359 {
 360         vid->rgb_mode   = MODE_RGB_P;
 361         exynos_set_dp_platform_data(&dp_platform_data);
 362 }
 363 #endif