board/samsung/smdk5250/smdk5250.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <cros_ec.h>
   9 #include <fdtdec.h>
  10 #include <asm/io.h>
  11 #include <errno.h>
  12 #include <i2c.h>
  13 #include <lcd.h>
  14 #include <netdev.h>
  15 #include <spi.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/dwmmc.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/mmc.h>
  20 #include <asm/arch/pinmux.h>
  21 #include <asm/arch/power.h>
  22 #include <asm/arch/sromc.h>
  23 #include <asm/arch/dp_info.h>
  24 #include <power/pmic.h>
  25 #include <power/max77686_pmic.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_SOUND_MAX98095
  30 static void  board_enable_audio_codec(void)
  31 {
  32         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  33                                                 samsung_get_base_gpio_part1();
  34
  35         /* Enable MAX98095 Codec */
  36         s5p_gpio_direction_output(&gpio1->x1, 7, 1);
  37         s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
  38 }
  39 #endif
  40
  41 int exynos_init(void)
  42 {
  43 #ifdef CONFIG_SOUND_MAX98095
  44         board_enable_audio_codec();
  45 #endif
  46         return 0;
  47 }
  48
  49 int board_eth_init(bd_t *bis)
  50 {
  51 #ifdef CONFIG_SMC911X
  52         u32 smc_bw_conf, smc_bc_conf;
  53         struct fdt_sromc config;
  54         fdt_addr_t base_addr;
  55
  56         /* Non-FDT configuration - bank number and timing parameters*/
  57         config.bank = CONFIG_ENV_SROM_BANK;
  58         config.width = 2;
  59
  60         config.timing[FDT_SROM_TACS] = 0x01;
  61         config.timing[FDT_SROM_TCOS] = 0x01;
  62         config.timing[FDT_SROM_TACC] = 0x06;
  63         config.timing[FDT_SROM_TCOH] = 0x01;
  64         config.timing[FDT_SROM_TAH] = 0x0C;
  65         config.timing[FDT_SROM_TACP] = 0x09;
  66         config.timing[FDT_SROM_PMC] = 0x01;
  67         base_addr = CONFIG_SMC911X_BASE;
  68
  69         /* Ethernet needs data bus width of 16 bits */
  70         if (config.width != 2) {
  71                 debug("%s: Unsupported bus width %d\n", __func__,
  72                         config.width);
  73                 return -1;
  74         }
  75         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
  76                         | SROMC_BYTE_ENABLE(config.bank);
  77
  78         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
  79                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
  80                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
  81                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
  82                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
  83                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
  84                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
  85
  86         /* Select and configure the SROMC bank */
  87         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
  88         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
  89         return smc911x_initialize(0, base_addr);
  90 #endif
  91         return 0;
  92 }
  93
  94 #ifdef CONFIG_DISPLAY_BOARDINFO
  95 int checkboard(void)
  96 {
  97         printf("\nBoard: SMDK5250\n");
  98         return 0;
  99 }
 100 #endif
 101
 102 #ifdef CONFIG_GENERIC_MMC
 103 int board_mmc_init(bd_t *bis)
 104 {
 105         int err, ret = 0, index, bus_width;
 106         u32 base;
 107
 108         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 109         if (err)
 110                 debug("SDMMC0 not configured\n");
 111         ret |= err;
 112
 113         /*EMMC: dwmmc Channel-0 with 8 bit bus width */
 114         index = 0;
 115         base =  samsung_get_base_mmc() + (0x10000 * index);
 116         bus_width = 8;
 117         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 118         if (err)
 119                 debug("dwmmc Channel-0 init failed\n");
 120         ret |= err;
 121
 122         err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
 123         if (err)
 124                 debug("SDMMC2 not configured\n");
 125         ret |= err;
 126
 127         /*SD: dwmmc Channel-2 with 4 bit bus width */
 128         index = 2;
 129         base = samsung_get_base_mmc() + (0x10000 * index);
 130         bus_width = 4;
 131         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 132         if (err)
 133                 debug("dwmmc Channel-2 init failed\n");
 134         ret |= err;
 135
 136         return ret;
 137 }
 138 #endif
 139
 140 void board_i2c_init(const void *blob)
 141 {
 142         int i;
 143
 144         for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
 145                 exynos_pinmux_config((PERIPH_ID_I2C0 + i),
 146                                      PINMUX_FLAG_NONE);
 147         }
 148 }
 149
 150 #if defined(CONFIG_POWER)
 151 #ifdef CONFIG_POWER_MAX77686
 152 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
 153 {
 154         u32 val;
 155         int ret = 0;
 156
 157         ret = pmic_reg_read(p, reg, &val);
 158         if (ret) {
 159                 debug("%s: PMIC %d register read failed\n", __func__, reg);
 160                 return -1;
 161         }
 162         val |= regval;
 163         ret = pmic_reg_write(p, reg, val);
 164         if (ret) {
 165                 debug("%s: PMIC %d register write failed\n", __func__, reg);
 166                 return -1;
 167         }
 168         return 0;
 169 }
 170
 171 static int max77686_init(void)
 172 {
 173         struct pmic *p;
 174
 175         if (pmic_init(I2C_PMIC))
 176                 return -1;
 177
 178         p = pmic_get("MAX77686_PMIC");
 179         if (!p)
 180                 return -ENODEV;
 181
 182         if (pmic_probe(p))
 183                 return -1;
 184
 185         if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
 186                 return -1;
 187
 188         if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
 189                             MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
 190                 return -1;
 191
 192         /* VDD_MIF */
 193         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
 194                            MAX77686_BUCK1OUT_1V)) {
 195                 debug("%s: PMIC %d register write failed\n", __func__,
 196                       MAX77686_REG_PMIC_BUCK1OUT);
 197                 return -1;
 198         }
 199
 200         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
 201                             MAX77686_BUCK1CTRL_EN))
 202                 return -1;
 203
 204         /* VDD_ARM */
 205         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
 206                            MAX77686_BUCK2DVS1_1_3V)) {
 207                 debug("%s: PMIC %d register write failed\n", __func__,
 208                       MAX77686_REG_PMIC_BUCK2DVS1);
 209                 return -1;
 210         }
 211
 212         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
 213                             MAX77686_BUCK2CTRL_ON))
 214                 return -1;
 215
 216         /* VDD_INT */
 217         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
 218                            MAX77686_BUCK3DVS1_1_0125V)) {
 219                 debug("%s: PMIC %d register write failed\n", __func__,
 220                       MAX77686_REG_PMIC_BUCK3DVS1);
 221                 return -1;
 222         }
 223
 224         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
 225                             MAX77686_BUCK3CTRL_ON))
 226                 return -1;
 227
 228         /* VDD_G3D */
 229         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
 230                            MAX77686_BUCK4DVS1_1_2V)) {
 231                 debug("%s: PMIC %d register write failed\n", __func__,
 232                       MAX77686_REG_PMIC_BUCK4DVS1);
 233                 return -1;
 234         }
 235
 236         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
 237                             MAX77686_BUCK3CTRL_ON))
 238                 return -1;
 239
 240         /* VDD_LDO2 */
 241         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
 242                             MAX77686_LD02CTRL1_1_5V | EN_LDO))
 243                 return -1;
 244
 245         /* VDD_LDO3 */
 246         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
 247                             MAX77686_LD03CTRL1_1_8V | EN_LDO))
 248                 return -1;
 249
 250         /* VDD_LDO5 */
 251         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
 252                             MAX77686_LD05CTRL1_1_8V | EN_LDO))
 253                 return -1;
 254
 255         /* VDD_LDO10 */
 256         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
 257                             MAX77686_LD10CTRL1_1_8V | EN_LDO))
 258                 return -1;
 259
 260         return 0;
 261 }
 262 #endif  /* CONFIG_POWER_MAX77686 */
 263
 264 int exynos_power_init(void)
 265 {
 266         int ret = 0;
 267
 268 #ifdef CONFIG_POWER_MAX77686
 269         ret = max77686_init();
 270 #endif
 271         return ret;
 272 }
 273 #endif  /* CONFIG_POWER */
 274
 275 #ifdef CONFIG_LCD
 276 void exynos_cfg_lcd_gpio(void)
 277 {
 278         struct exynos5_gpio_part1 *gpio1 =
 279                 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 280
 281         /* For Backlight */
 282         s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
 283         s5p_gpio_set_value(&gpio1->b2, 0, 1);
 284
 285         /* LCD power on */
 286         s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
 287         s5p_gpio_set_value(&gpio1->x1, 5, 1);
 288
 289         /* Set Hotplug detect for DP */
 290         s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
 291 }
 292
 293 void exynos_set_dp_phy(unsigned int onoff)
 294 {
 295         set_dp_phy_ctrl(onoff);
 296 }
 297
 298 vidinfo_t panel_info = {
 299         .vl_freq        = 60,
 300         .vl_col         = 2560,
 301         .vl_row         = 1600,
 302         .vl_width       = 2560,
 303         .vl_height      = 1600,
 304         .vl_clkp        = CONFIG_SYS_LOW,
 305         .vl_hsp         = CONFIG_SYS_LOW,
 306         .vl_vsp         = CONFIG_SYS_LOW,
 307         .vl_dp          = CONFIG_SYS_LOW,
 308         .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
 309
 310         /* wDP panel timing infomation */
 311         .vl_hspw        = 32,
 312         .vl_hbpd        = 80,
 313         .vl_hfpd        = 48,
 314
 315         .vl_vspw        = 6,
 316         .vl_vbpd        = 37,
 317         .vl_vfpd        = 3,
 318         .vl_cmd_allow_len = 0xf,
 319
 320         .win_id         = 3,
 321         .dual_lcd_enabled = 0,
 322
 323         .init_delay     = 0,
 324         .power_on_delay = 0,
 325         .reset_delay    = 0,
 326         .interface_mode = FIMD_RGB_INTERFACE,
 327         .dp_enabled     = 1,
 328 };
 329
 330 static struct edp_device_info edp_info = {
 331         .disp_info = {
 332                 .h_res = 2560,
 333                 .h_sync_width = 32,
 334                 .h_back_porch = 80,
 335                 .h_front_porch = 48,
 336                 .v_res = 1600,
 337                 .v_sync_width  = 6,
 338                 .v_back_porch = 37,
 339                 .v_front_porch = 3,
 340                 .v_sync_rate = 60,
 341         },
 342         .lt_info = {
 343                 .lt_status = DP_LT_NONE,
 344         },
 345         .video_info = {
 346                 .master_mode = 0,
 347                 .bist_mode = DP_DISABLE,
 348                 .bist_pattern = NO_PATTERN,
 349                 .h_sync_polarity = 0,
 350                 .v_sync_polarity = 0,
 351                 .interlaced = 0,
 352                 .color_space = COLOR_RGB,
 353                 .dynamic_range = VESA,
 354                 .ycbcr_coeff = COLOR_YCBCR601,
 355                 .color_depth = COLOR_8,
 356         },
 357 };
 358
 359 static struct exynos_dp_platform_data dp_platform_data = {
 360         .edp_dev_info   = &edp_info,
 361 };
 362
 363 void init_panel_info(vidinfo_t *vid)
 364 {
 365         vid->rgb_mode   = MODE_RGB_P;
 366         exynos_set_dp_platform_data(&dp_platform_data);
 367 }
 368 #endif