Merge branch 'master' of git://git.denx.de/u-boot-arm
[karo-tx-uboot.git] / board / samsung / trats / trats.c
1 /*
2  * Copyright (C) 2011 Samsung Electronics
3  * Heungjun Kim <riverful.kim@samsung.com>
4  * Kyungmin Park <kyungmin.park@samsung.com>
5  * Donghwa Lee <dh09.lee@samsung.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #include <common.h>
11 #include <lcd.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/mmc.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/clk.h>
19 #include <asm/arch/mipi_dsim.h>
20 #include <asm/arch/watchdog.h>
21 #include <asm/arch/power.h>
22 #include <power/pmic.h>
23 #include <usb/s3c_udc.h>
24 #include <power/max8997_pmic.h>
25 #include <libtizen.h>
26 #include <power/max8997_muic.h>
27 #include <power/battery.h>
28 #include <power/max17042_fg.h>
29 #include <usb.h>
30 #include <usb_mass_storage.h>
31
32 #include "setup.h"
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 unsigned int board_rev;
37
38 #ifdef CONFIG_REVISION_TAG
39 u32 get_board_rev(void)
40 {
41         return board_rev;
42 }
43 #endif
44
45 static void check_hw_revision(void);
46 struct s3c_plat_otg_data s5pc210_otg_data;
47
48 int board_init(void)
49 {
50         gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
51
52         check_hw_revision();
53         printf("HW Revision:\t0x%x\n", board_rev);
54
55         return 0;
56 }
57
58 void i2c_init_board(void)
59 {
60         int err;
61         struct exynos4_gpio_part2 *gpio2 =
62                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
63
64         /* I2C_5 -> PMIC */
65         err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
66         if (err) {
67                 debug("I2C%d not configured\n", (I2C_5));
68                 return;
69         }
70
71         /* I2C_8 -> FG */
72         s5p_gpio_direction_output(&gpio2->y4, 0, 1);
73         s5p_gpio_direction_output(&gpio2->y4, 1, 1);
74 }
75
76 static void trats_low_power_mode(void)
77 {
78         struct exynos4_clock *clk =
79             (struct exynos4_clock *)samsung_get_base_clock();
80         struct exynos4_power *pwr =
81             (struct exynos4_power *)samsung_get_base_power();
82
83         /* Power down CORE1 */
84         /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
85         writel(0x0, &pwr->arm_core1_configuration);
86
87         /* Change the APLL frequency */
88         /* ENABLE (1 enable) | LOCKED (1 locked)  */
89         /* [31]              | [29]               */
90         /* FSEL      | MDIV          | PDIV            | SDIV */
91         /* [27]      | [25:16]       | [13:8]          | [2:0]      */
92         writel(0xa0c80604, &clk->apll_con0);
93
94         /* Change CPU0 clock divider */
95         /* CORE2_RATIO  | APLL_RATIO   | PCLK_DBG_RATIO | ATB_RATIO  */
96         /* [30:28]      | [26:24]      | [22:20]        | [18:16]    */
97         /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO   | CORE_RATIO */
98         /* [14:12]      | [10:8]       | [6:4]          | [2:0]      */
99         writel(0x00000100, &clk->div_cpu0);
100
101         /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
102         while (readl(&clk->div_stat_cpu0) & 0x1111111)
103                 continue;
104
105         /* Change clock divider ratio for DMC */
106         /* DMCP_RATIO                  | DMCD_RATIO  */
107         /* [22:20]                     | [18:16]     */
108         /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO   | ACP_RATIO */
109         /* [14:12]   | [10:8]     | [6:4]            | [2:0]     */
110         writel(0x13113117, &clk->div_dmc0);
111
112         /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
113         while (readl(&clk->div_stat_dmc0) & 0x11111111)
114                 continue;
115
116         /* Turn off unnecessary power domains */
117         writel(0x0, &pwr->xxti_configuration);  /* XXTI */
118         writel(0x0, &pwr->cam_configuration);   /* CAM */
119         writel(0x0, &pwr->tv_configuration);    /* TV */
120         writel(0x0, &pwr->mfc_configuration);   /* MFC */
121         writel(0x0, &pwr->g3d_configuration);   /* G3D */
122         writel(0x0, &pwr->gps_configuration);   /* GPS */
123         writel(0x0, &pwr->gps_alive_configuration);     /* GPS_ALIVE */
124
125         /* Turn off unnecessary clocks */
126         writel(0x0, &clk->gate_ip_cam); /* CAM */
127         writel(0x0, &clk->gate_ip_tv);          /* TV */
128         writel(0x0, &clk->gate_ip_mfc); /* MFC */
129         writel(0x0, &clk->gate_ip_g3d); /* G3D */
130         writel(0x0, &clk->gate_ip_image);       /* IMAGE */
131         writel(0x0, &clk->gate_ip_gps); /* GPS */
132 }
133
134 static int pmic_init_max8997(void)
135 {
136         struct pmic *p = pmic_get("MAX8997_PMIC");
137         int i = 0, ret = 0;
138         u32 val;
139
140         if (pmic_probe(p))
141                 return -1;
142
143         /* BUCK1 VARM: 1.2V */
144         val = (1200000 - 650000) / 25000;
145         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
146         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
147         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
148
149         /* BUCK2 VINT: 1.1V */
150         val = (1100000 - 650000) / 25000;
151         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
152         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
153         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
154
155
156         /* BUCK3 G3D: 1.1V - OFF */
157         ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
158         val &= ~ENBUCK;
159         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
160
161         val = (1100000 - 750000) / 50000;
162         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
163
164         /* BUCK4 CAMISP: 1.2V - OFF */
165         ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
166         val &= ~ENBUCK;
167         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
168
169         val = (1200000 - 650000) / 25000;
170         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
171
172         /* BUCK5 VMEM: 1.2V */
173         val = (1200000 - 650000) / 25000;
174         for (i = 0; i < 8; i++)
175                 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
176
177         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
178         ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
179
180         /* BUCK6 CAM AF: 2.8V */
181         /* No Voltage Setting Register */
182         /* GNSLCT 3.0X */
183         val = GNSLCT;
184         ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
185
186         /* BUCK7 VCC_SUB: 2.0V */
187         val = (2000000 - 750000) / 50000;
188         ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
189
190         /* LDO1 VADC: 3.3V */
191         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
192         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
193
194         /* LDO1 Disable active discharging */
195         ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
196         val &= ~LDO_ADE;
197         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
198
199         /* LDO2 VALIVE: 1.1V */
200         val = max8997_reg_ldo(1100000) | EN_LDO;
201         ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
202
203         /* LDO3 VUSB/MIPI: 1.1V */
204         val = max8997_reg_ldo(1100000) | DIS_LDO;       /* OFF */
205         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
206
207         /* LDO4 VMIPI: 1.8V */
208         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
209         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
210
211         /* LDO5 VHSIC: 1.2V */
212         val = max8997_reg_ldo(1200000) | DIS_LDO;       /* OFF */
213         ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
214
215         /* LDO6 VCC_1.8V_PDA: 1.8V */
216         val = max8997_reg_ldo(1800000) | EN_LDO;
217         ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
218
219         /* LDO7 CAM_ISP: 1.8V */
220         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
221         ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
222
223         /* LDO8 VDAC/VUSB: 3.3V */
224         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
225         ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
226
227         /* LDO9 VCC_2.8V_PDA: 2.8V */
228         val = max8997_reg_ldo(2800000) | EN_LDO;
229         ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
230
231         /* LDO10 VPLL: 1.1V */
232         val = max8997_reg_ldo(1100000) | EN_LDO;
233         ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
234
235         /* LDO11 TOUCH: 2.8V */
236         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
237         ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
238
239         /* LDO12 VTCAM: 1.8V */
240         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
241         ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
242
243         /* LDO13 VCC_3.0_LCD: 3.0V */
244         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
245         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
246
247         /* LDO14 MOTOR: 3.0V */
248         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
249         ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
250
251         /* LDO15 LED_A: 2.8V */
252         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
253         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
254
255         /* LDO16 CAM_SENSOR: 1.8V */
256         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
257         ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
258
259         /* LDO17 VTF: 2.8V */
260         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
261         ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
262
263         /* LDO18 TOUCH_LED 3.3V */
264         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
265         ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
266
267         /* LDO21 VDDQ: 1.2V */
268         val = max8997_reg_ldo(1200000) | EN_LDO;
269         ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
270
271         /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
272         val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
273                 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
274         ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
275
276         if (ret) {
277                 puts("MAX8997 PMIC setting error!\n");
278                 return -1;
279         }
280         return 0;
281 }
282
283 int power_init_board(void)
284 {
285         int chrg, ret;
286         struct power_battery *pb;
287         struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
288
289         /*
290          * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
291          * to logical I2C adapter 0
292          *
293          * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
294          * to logical I2C adapter 1
295          */
296         ret = pmic_init(I2C_5);
297         ret |= pmic_init_max8997();
298         ret |= power_fg_init(I2C_8);
299         ret |= power_muic_init(I2C_5);
300         ret |= power_bat_init(0);
301         if (ret)
302                 return ret;
303
304         p_fg = pmic_get("MAX17042_FG");
305         if (!p_fg) {
306                 puts("MAX17042_FG: Not found\n");
307                 return -ENODEV;
308         }
309
310         p_chrg = pmic_get("MAX8997_PMIC");
311         if (!p_chrg) {
312                 puts("MAX8997_PMIC: Not found\n");
313                 return -ENODEV;
314         }
315
316         p_muic = pmic_get("MAX8997_MUIC");
317         if (!p_muic) {
318                 puts("MAX8997_MUIC: Not found\n");
319                 return -ENODEV;
320         }
321
322         p_bat = pmic_get("BAT_TRATS");
323         if (!p_bat) {
324                 puts("BAT_TRATS: Not found\n");
325                 return -ENODEV;
326         }
327
328         p_fg->parent =  p_bat;
329         p_chrg->parent = p_bat;
330         p_muic->parent = p_bat;
331
332         p_bat->low_power_mode = trats_low_power_mode;
333         p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
334
335         pb = p_bat->pbat;
336         chrg = p_muic->chrg->chrg_type(p_muic);
337         debug("CHARGER TYPE: %d\n", chrg);
338
339         if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
340                 puts("No battery detected\n");
341                 return -1;
342         }
343
344         p_fg->fg->fg_battery_check(p_fg, p_bat);
345
346         if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
347                 puts("CHARGE Battery !\n");
348
349         return 0;
350 }
351
352 int dram_init(void)
353 {
354         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
355                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
356                 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
357                 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
358
359         return 0;
360 }
361
362 void dram_init_banksize(void)
363 {
364         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
365         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
366         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
367         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
368         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
369         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
370         gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
371         gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
372 }
373
374 static unsigned int get_hw_revision(void)
375 {
376         struct exynos4_gpio_part1 *gpio =
377                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
378         int hwrev = 0;
379         int i;
380
381         /* hw_rev[3:0] == GPE1[3:0] */
382         for (i = 0; i < 4; i++) {
383                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
384                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
385         }
386
387         udelay(1);
388
389         for (i = 0; i < 4; i++)
390                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
391
392         debug("hwrev 0x%x\n", hwrev);
393
394         return hwrev;
395 }
396
397 static void check_hw_revision(void)
398 {
399         int hwrev;
400
401         hwrev = get_hw_revision();
402
403         board_rev |= hwrev;
404 }
405
406 #ifdef CONFIG_DISPLAY_BOARDINFO
407 int checkboard(void)
408 {
409         puts("Board:\tTRATS\n");
410         return 0;
411 }
412 #endif
413
414 #ifdef CONFIG_GENERIC_MMC
415 int board_mmc_init(bd_t *bis)
416 {
417         struct exynos4_gpio_part2 *gpio =
418                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
419         int err;
420
421         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
422         s5p_gpio_direction_output(&gpio->k0, 2, 1);
423         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
424
425         /*
426          * MMC device init
427          * mmc0  : eMMC (8-bit buswidth)
428          * mmc2  : SD card (4-bit buswidth)
429          */
430         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
431         if (err)
432                 debug("SDMMC0 not configured\n");
433         else
434                 err = s5p_mmc_init(0, 8);
435
436         /* T-flash detect */
437         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
438         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
439
440         /*
441          * Check the T-flash  detect pin
442          * GPX3[4] T-flash detect pin
443          */
444         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
445                 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
446                 if (err)
447                         debug("SDMMC2 not configured\n");
448                 else
449                         err = s5p_mmc_init(2, 4);
450         }
451
452         return err;
453 }
454 #endif
455
456 #ifdef CONFIG_USB_GADGET
457 static int s5pc210_phy_control(int on)
458 {
459         int ret = 0;
460         u32 val = 0;
461         struct pmic *p = pmic_get("MAX8997_PMIC");
462         if (!p)
463                 return -ENODEV;
464
465         if (pmic_probe(p))
466                 return -1;
467
468         if (on) {
469                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
470                                       ENSAFEOUT1, LDO_ON);
471                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
472                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
473
474                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
475                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
476         } else {
477                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
478                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
479
480                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
481                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
482                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
483                                       ENSAFEOUT1, LDO_OFF);
484         }
485
486         if (ret) {
487                 puts("MAX8997 LDO setting error!\n");
488                 return -1;
489         }
490
491         return 0;
492 }
493
494 struct s3c_plat_otg_data s5pc210_otg_data = {
495         .phy_control    = s5pc210_phy_control,
496         .regs_phy       = EXYNOS4_USBPHY_BASE,
497         .regs_otg       = EXYNOS4_USBOTG_BASE,
498         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
499         .usb_flags      = PHY0_SLEEP,
500 };
501
502 int board_usb_init(int index, enum usb_init_type init)
503 {
504         debug("USB_udc_probe\n");
505         return s3c_udc_probe(&s5pc210_otg_data);
506 }
507
508 #ifdef CONFIG_USB_CABLE_CHECK
509 int usb_cable_connected(void)
510 {
511         struct pmic *muic = pmic_get("MAX8997_MUIC");
512         if (!muic)
513                 return 0;
514
515         return !!muic->chrg->chrg_type(muic);
516 }
517 #endif
518 #endif
519
520 static void pmic_reset(void)
521 {
522         struct exynos4_gpio_part2 *gpio =
523                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
524
525         s5p_gpio_direction_output(&gpio->x0, 7, 1);
526         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
527 }
528
529 static void board_clock_init(void)
530 {
531         struct exynos4_clock *clk =
532                 (struct exynos4_clock *)samsung_get_base_clock();
533
534         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
535         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
536         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
537         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
538
539         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
540         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
541         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
542         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
543         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
544         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
545         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
546         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
547         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
548         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
549         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
550         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
551
552         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
553         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
554         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
555         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
556         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
557         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
558         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
559         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
560         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
561         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
562         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
563         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
564
565         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
566         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
567         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
568         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
569         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
570         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
571         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
572         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
573         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
574         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
575         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
576         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
577 }
578
579 static void board_power_init(void)
580 {
581         struct exynos4_power *pwr =
582                 (struct exynos4_power *)samsung_get_base_power();
583
584         /* PS HOLD */
585         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
586
587         /* Set power down */
588         writel(0, (unsigned int)&pwr->cam_configuration);
589         writel(0, (unsigned int)&pwr->tv_configuration);
590         writel(0, (unsigned int)&pwr->mfc_configuration);
591         writel(0, (unsigned int)&pwr->g3d_configuration);
592         writel(0, (unsigned int)&pwr->lcd1_configuration);
593         writel(0, (unsigned int)&pwr->gps_configuration);
594         writel(0, (unsigned int)&pwr->gps_alive_configuration);
595
596         /* It is necessary to power down core 1 */
597         /* to successfully boot CPU1 in kernel */
598         writel(0, (unsigned int)&pwr->arm_core1_configuration);
599 }
600
601 static void board_uart_init(void)
602 {
603         struct exynos4_gpio_part1 *gpio1 =
604                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
605         struct exynos4_gpio_part2 *gpio2 =
606                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
607         int i;
608
609         /*
610          * UART2 GPIOs
611          * GPA1CON[0] = UART_2_RXD(2)
612          * GPA1CON[1] = UART_2_TXD(2)
613          * GPA1CON[2] = I2C_3_SDA (3)
614          * GPA1CON[3] = I2C_3_SCL (3)
615          */
616
617         for (i = 0; i < 4; i++) {
618                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
619                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
620         }
621
622         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
623         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
624         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
625 }
626
627 int board_early_init_f(void)
628 {
629         wdt_stop();
630         pmic_reset();
631         board_clock_init();
632         board_uart_init();
633         board_power_init();
634
635         return 0;
636 }
637
638 void exynos_reset_lcd(void)
639 {
640         struct exynos4_gpio_part2 *gpio2 =
641                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
642
643         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
644         udelay(10000);
645         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
646         udelay(10000);
647         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
648 }
649
650 static int lcd_power(void)
651 {
652         int ret = 0;
653         struct pmic *p = pmic_get("MAX8997_PMIC");
654         if (!p)
655                 return -ENODEV;
656
657         if (pmic_probe(p))
658                 return 0;
659
660         /* LDO15 voltage: 2.2v */
661         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
662         /* LDO13 voltage: 3.0v */
663         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
664
665         if (ret) {
666                 puts("MAX8997 LDO setting error!\n");
667                 return -1;
668         }
669
670         return 0;
671 }
672
673 static struct mipi_dsim_config dsim_config = {
674         .e_interface            = DSIM_VIDEO,
675         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
676         .e_pixel_format         = DSIM_24BPP_888,
677         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
678         .e_no_data_lane         = DSIM_DATA_LANE_4,
679         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
680         .hfp                    = 1,
681
682         .p                      = 3,
683         .m                      = 120,
684         .s                      = 1,
685
686         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
687         .pll_stable_time        = 500,
688
689         /* escape clk : 10MHz */
690         .esc_clk                = 20 * 1000000,
691
692         /* stop state holding counter after bta change count 0 ~ 0xfff */
693         .stop_holding_cnt       = 0x7ff,
694         /* bta timeout 0 ~ 0xff */
695         .bta_timeout            = 0xff,
696         /* lp rx timeout 0 ~ 0xffff */
697         .rx_timeout             = 0xffff,
698 };
699
700 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
701         .lcd_panel_info = NULL,
702         .dsim_config = &dsim_config,
703 };
704
705 static struct mipi_dsim_lcd_device mipi_lcd_device = {
706         .name   = "s6e8ax0",
707         .id     = -1,
708         .bus_id = 0,
709         .platform_data  = (void *)&s6e8ax0_platform_data,
710 };
711
712 static int mipi_power(void)
713 {
714         int ret = 0;
715         struct pmic *p = pmic_get("MAX8997_PMIC");
716         if (!p)
717                 return -ENODEV;
718
719         if (pmic_probe(p))
720                 return 0;
721
722         /* LDO3 voltage: 1.1v */
723         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
724         /* LDO4 voltage: 1.8v */
725         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
726
727         if (ret) {
728                 puts("MAX8997 LDO setting error!\n");
729                 return -1;
730         }
731
732         return 0;
733 }
734
735 vidinfo_t panel_info = {
736         .vl_freq        = 60,
737         .vl_col         = 720,
738         .vl_row         = 1280,
739         .vl_width       = 720,
740         .vl_height      = 1280,
741         .vl_clkp        = CONFIG_SYS_HIGH,
742         .vl_hsp         = CONFIG_SYS_LOW,
743         .vl_vsp         = CONFIG_SYS_LOW,
744         .vl_dp          = CONFIG_SYS_LOW,
745         .vl_bpix        = 5,    /* Bits per pixel, 2^5 = 32 */
746
747         /* s6e8ax0 Panel infomation */
748         .vl_hspw        = 5,
749         .vl_hbpd        = 10,
750         .vl_hfpd        = 10,
751
752         .vl_vspw        = 2,
753         .vl_vbpd        = 1,
754         .vl_vfpd        = 13,
755         .vl_cmd_allow_len = 0xf,
756
757         .win_id         = 3,
758         .dual_lcd_enabled = 0,
759
760         .init_delay     = 0,
761         .power_on_delay = 0,
762         .reset_delay    = 0,
763         .interface_mode = FIMD_RGB_INTERFACE,
764         .mipi_enabled   = 1,
765 };
766
767 void init_panel_info(vidinfo_t *vid)
768 {
769         vid->logo_on    = 1,
770         vid->resolution = HD_RESOLUTION,
771         vid->rgb_mode   = MODE_RGB_P,
772
773 #ifdef CONFIG_TIZEN
774         get_tizen_logo_info(vid);
775 #endif
776         mipi_lcd_device.reverse_panel = 1;
777
778         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
779         s6e8ax0_platform_data.lcd_power = lcd_power;
780         s6e8ax0_platform_data.mipi_power = mipi_power;
781         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
782         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
783         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
784         s6e8ax0_init();
785         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
786
787         setenv("lcdinfo", "lcd=s6e8ax0");
788 }