board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <lcd.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include <asm/arch/mmc.h>
  32 #include <asm/arch/pinmux.h>
  33 #include <asm/arch/clock.h>
  34 #include <asm/arch/clk.h>
  35 #include <asm/arch/mipi_dsim.h>
  36 #include <asm/arch/watchdog.h>
  37 #include <asm/arch/power.h>
  38 #include <pmic.h>
  39 #include <usb/s3c_udc.h>
  40 #include <max8997_pmic.h>
  41 #include <libtizen.h>
  42
  43 #include "setup.h"
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 unsigned int board_rev;
  48
  49 #ifdef CONFIG_REVISION_TAG
  50 u32 get_board_rev(void)
  51 {
  52         return board_rev;
  53 }
  54 #endif
  55
  56 static void check_hw_revision(void);
  57
  58 static int hwrevision(int rev)
  59 {
  60         return (board_rev & 0xf) == rev;
  61 }
  62
  63 struct s3c_plat_otg_data s5pc210_otg_data;
  64
  65 int board_init(void)
  66 {
  67         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  68
  69         check_hw_revision();
  70         printf("HW Revision:\t0x%x\n", board_rev);
  71
  72 #if defined(CONFIG_PMIC)
  73         pmic_init();
  74 #endif
  75
  76         return 0;
  77 }
  78
  79 void i2c_init_board(void)
  80 {
  81         struct exynos4_gpio_part1 *gpio1 =
  82                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
  83         struct exynos4_gpio_part2 *gpio2 =
  84                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  85
  86         /* I2C_5 -> PMIC */
  87         s5p_gpio_direction_output(&gpio1->b, 7, 1);
  88         s5p_gpio_direction_output(&gpio1->b, 6, 1);
  89         /* I2C_9 -> FG */
  90         s5p_gpio_direction_output(&gpio2->y4, 0, 1);
  91         s5p_gpio_direction_output(&gpio2->y4, 1, 1);
  92 }
  93
  94 int dram_init(void)
  95 {
  96         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
  97                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
  98                 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
  99                 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
 100
 101         return 0;
 102 }
 103
 104 void dram_init_banksize(void)
 105 {
 106         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 107         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 108         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 109         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 110         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 111         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
 112         gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 113         gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
 114 }
 115
 116 static unsigned int get_hw_revision(void)
 117 {
 118         struct exynos4_gpio_part1 *gpio =
 119                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 120         int hwrev = 0;
 121         int i;
 122
 123         /* hw_rev[3:0] == GPE1[3:0] */
 124         for (i = 0; i < 4; i++) {
 125                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
 126                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
 127         }
 128
 129         udelay(1);
 130
 131         for (i = 0; i < 4; i++)
 132                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
 133
 134         debug("hwrev 0x%x\n", hwrev);
 135
 136         return hwrev;
 137 }
 138
 139 static void check_hw_revision(void)
 140 {
 141         int hwrev;
 142
 143         hwrev = get_hw_revision();
 144
 145         board_rev |= hwrev;
 146 }
 147
 148 #ifdef CONFIG_DISPLAY_BOARDINFO
 149 int checkboard(void)
 150 {
 151         puts("Board:\tTRATS\n");
 152         return 0;
 153 }
 154 #endif
 155
 156 #ifdef CONFIG_GENERIC_MMC
 157 int board_mmc_init(bd_t *bis)
 158 {
 159         struct exynos4_gpio_part2 *gpio =
 160                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 161         int err;
 162
 163         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 164         s5p_gpio_direction_output(&gpio->k0, 2, 1);
 165         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 166
 167         /*
 168          * MMC device init
 169          * mmc0  : eMMC (8-bit buswidth)
 170          * mmc2  : SD card (4-bit buswidth)
 171          */
 172         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 173         if (err)
 174                 debug("SDMMC0 not configured\n");
 175         else
 176                 err = s5p_mmc_init(0, 8);
 177
 178         /* T-flash detect */
 179         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
 180         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
 181
 182         /*
 183          * Check the T-flash  detect pin
 184          * GPX3[4] T-flash detect pin
 185          */
 186         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
 187                 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
 188                 if (err)
 189                         debug("SDMMC2 not configured\n");
 190                 else
 191                         err = s5p_mmc_init(2, 4);
 192         }
 193
 194         return err;
 195 }
 196 #endif
 197
 198 #ifdef CONFIG_USB_GADGET
 199 static int s5pc210_phy_control(int on)
 200 {
 201         int ret = 0;
 202         u32 val = 0;
 203         struct pmic *p = get_pmic();
 204
 205         if (pmic_probe(p))
 206                 return -1;
 207
 208         if (on) {
 209                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 210                                       ENSAFEOUT1, LDO_ON);
 211                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 212                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
 213
 214                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 215                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
 216         } else {
 217                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 218                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
 219
 220                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 221                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
 222                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 223                                       ENSAFEOUT1, LDO_OFF);
 224         }
 225
 226         if (ret) {
 227                 puts("MAX8997 LDO setting error!\n");
 228                 return -1;
 229         }
 230
 231         return 0;
 232 }
 233
 234 struct s3c_plat_otg_data s5pc210_otg_data = {
 235         .phy_control    = s5pc210_phy_control,
 236         .regs_phy       = EXYNOS4_USBPHY_BASE,
 237         .regs_otg       = EXYNOS4_USBOTG_BASE,
 238         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 239         .usb_flags      = PHY0_SLEEP,
 240 };
 241
 242 void board_usb_init(void)
 243 {
 244         debug("USB_udc_probe\n");
 245         s3c_udc_probe(&s5pc210_otg_data);
 246 }
 247 #endif
 248
 249 static void pmic_reset(void)
 250 {
 251         struct exynos4_gpio_part2 *gpio =
 252                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 253
 254         s5p_gpio_direction_output(&gpio->x0, 7, 1);
 255         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
 256 }
 257
 258 static void board_clock_init(void)
 259 {
 260         struct exynos4_clock *clk =
 261                 (struct exynos4_clock *)samsung_get_base_clock();
 262
 263         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 264         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 265         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 266         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 267
 268         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 269         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 270         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 271         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 272         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 273         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 274         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 275         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 276         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 277         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 278         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 279         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 280
 281         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 282         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 283         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 284         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 285         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 286         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 287         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 288         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 289         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 290         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 291         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 292         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 293
 294         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 295         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 296         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 297         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 298         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 299         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 300         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 301         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 302         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 303         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 304         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 305         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 306 }
 307
 308 static void board_power_init(void)
 309 {
 310         struct exynos4_power *pwr =
 311                 (struct exynos4_power *)samsung_get_base_power();
 312
 313         /* PS HOLD */
 314         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 315
 316         /* Set power down */
 317         writel(0, (unsigned int)&pwr->cam_configuration);
 318         writel(0, (unsigned int)&pwr->tv_configuration);
 319         writel(0, (unsigned int)&pwr->mfc_configuration);
 320         writel(0, (unsigned int)&pwr->g3d_configuration);
 321         writel(0, (unsigned int)&pwr->lcd1_configuration);
 322         writel(0, (unsigned int)&pwr->gps_configuration);
 323         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 324
 325         /* It is necessary to power down core 1 */
 326         /* to successfully boot CPU1 in kernel */
 327         writel(0, (unsigned int)&pwr->arm_core1_configuration);
 328 }
 329
 330 static void board_uart_init(void)
 331 {
 332         struct exynos4_gpio_part1 *gpio1 =
 333                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 334         struct exynos4_gpio_part2 *gpio2 =
 335                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 336         int i;
 337
 338         /*
 339          * UART2 GPIOs
 340          * GPA1CON[0] = UART_2_RXD(2)
 341          * GPA1CON[1] = UART_2_TXD(2)
 342          * GPA1CON[2] = I2C_3_SDA (3)
 343          * GPA1CON[3] = I2C_3_SCL (3)
 344          */
 345
 346         for (i = 0; i < 4; i++) {
 347                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 348                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 349         }
 350
 351         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 352         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 353         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 354 }
 355
 356 int board_early_init_f(void)
 357 {
 358         wdt_stop();
 359         pmic_reset();
 360         board_clock_init();
 361         board_uart_init();
 362         board_power_init();
 363
 364         return 0;
 365 }
 366
 367 static void lcd_reset(void)
 368 {
 369         struct exynos4_gpio_part2 *gpio2 =
 370                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 371
 372         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 373         udelay(10000);
 374         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
 375         udelay(10000);
 376         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 377 }
 378
 379 static int lcd_power(void)
 380 {
 381         int ret = 0;
 382         struct pmic *p = get_pmic();
 383
 384         if (pmic_probe(p))
 385                 return 0;
 386
 387         /* LDO15 voltage: 2.2v */
 388         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 389         /* LDO13 voltage: 3.0v */
 390         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 391
 392         if (ret) {
 393                 puts("MAX8997 LDO setting error!\n");
 394                 return -1;
 395         }
 396
 397         return 0;
 398 }
 399
 400 static struct mipi_dsim_config dsim_config = {
 401         .e_interface            = DSIM_VIDEO,
 402         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
 403         .e_pixel_format         = DSIM_24BPP_888,
 404         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
 405         .e_no_data_lane         = DSIM_DATA_LANE_4,
 406         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 407         .hfp                    = 1,
 408
 409         .p                      = 3,
 410         .m                      = 120,
 411         .s                      = 1,
 412
 413         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 414         .pll_stable_time        = 500,
 415
 416         /* escape clk : 10MHz */
 417         .esc_clk                = 20 * 1000000,
 418
 419         /* stop state holding counter after bta change count 0 ~ 0xfff */
 420         .stop_holding_cnt       = 0x7ff,
 421         /* bta timeout 0 ~ 0xff */
 422         .bta_timeout            = 0xff,
 423         /* lp rx timeout 0 ~ 0xffff */
 424         .rx_timeout             = 0xffff,
 425 };
 426
 427 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
 428         .lcd_panel_info = NULL,
 429         .dsim_config = &dsim_config,
 430 };
 431
 432 static struct mipi_dsim_lcd_device mipi_lcd_device = {
 433         .name   = "s6e8ax0",
 434         .id     = -1,
 435         .bus_id = 0,
 436         .platform_data  = (void *)&s6e8ax0_platform_data,
 437 };
 438
 439 static int mipi_power(void)
 440 {
 441         int ret = 0;
 442         struct pmic *p = get_pmic();
 443
 444         if (pmic_probe(p))
 445                 return 0;
 446
 447         /* LDO3 voltage: 1.1v */
 448         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 449         /* LDO4 voltage: 1.8v */
 450         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 451
 452         if (ret) {
 453                 puts("MAX8997 LDO setting error!\n");
 454                 return -1;
 455         }
 456
 457         return 0;
 458 }
 459
 460 vidinfo_t panel_info = {
 461         .vl_freq        = 60,
 462         .vl_col         = 720,
 463         .vl_row         = 1280,
 464         .vl_width       = 720,
 465         .vl_height      = 1280,
 466         .vl_clkp        = CONFIG_SYS_HIGH,
 467         .vl_hsp         = CONFIG_SYS_LOW,
 468         .vl_vsp         = CONFIG_SYS_LOW,
 469         .vl_dp          = CONFIG_SYS_LOW,
 470         .vl_bpix        = 5,    /* Bits per pixel, 2^5 = 32 */
 471
 472         /* s6e8ax0 Panel infomation */
 473         .vl_hspw        = 5,
 474         .vl_hbpd        = 10,
 475         .vl_hfpd        = 10,
 476
 477         .vl_vspw        = 2,
 478         .vl_vbpd        = 1,
 479         .vl_vfpd        = 13,
 480         .vl_cmd_allow_len = 0xf,
 481
 482         .win_id         = 3,
 483         .cfg_gpio       = NULL,
 484         .backlight_on   = NULL,
 485         .lcd_power_on   = NULL, /* lcd_power_on in mipi dsi driver */
 486         .reset_lcd      = lcd_reset,
 487         .dual_lcd_enabled = 0,
 488
 489         .init_delay     = 0,
 490         .power_on_delay = 0,
 491         .reset_delay    = 0,
 492         .interface_mode = FIMD_RGB_INTERFACE,
 493         .mipi_enabled   = 1,
 494 };
 495
 496 void init_panel_info(vidinfo_t *vid)
 497 {
 498         vid->logo_on    = 1,
 499         vid->resolution = HD_RESOLUTION,
 500         vid->rgb_mode   = MODE_RGB_P,
 501
 502 #ifdef CONFIG_TIZEN
 503         get_tizen_logo_info(vid);
 504 #endif
 505
 506         if (hwrevision(2))
 507                 mipi_lcd_device.reverse_panel = 1;
 508
 509         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
 510         s6e8ax0_platform_data.lcd_power = lcd_power;
 511         s6e8ax0_platform_data.mipi_power = mipi_power;
 512         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
 513         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
 514         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
 515         s6e8ax0_init();
 516         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
 517
 518         setenv("lcdinfo", "lcd=s6e8ax0");
 519 }