board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <lcd.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include <asm/arch/mmc.h>
  32 #include <asm/arch/pinmux.h>
  33 #include <asm/arch/clock.h>
  34 #include <asm/arch/clk.h>
  35 #include <asm/arch/mipi_dsim.h>
  36 #include <asm/arch/watchdog.h>
  37 #include <asm/arch/power.h>
  38 #include <power/pmic.h>
  39 #include <usb/s3c_udc.h>
  40 #include <power/max8997_pmic.h>
  41 #include <libtizen.h>
  42 #include <power/max8997_muic.h>
  43 #include <power/battery.h>
  44 #include <power/max17042_fg.h>
  45 #include <usb_mass_storage.h>
  46
  47 #include "setup.h"
  48
  49 DECLARE_GLOBAL_DATA_PTR;
  50
  51 unsigned int board_rev;
  52
  53 #ifdef CONFIG_REVISION_TAG
  54 u32 get_board_rev(void)
  55 {
  56         return board_rev;
  57 }
  58 #endif
  59
  60 static void check_hw_revision(void);
  61 struct s3c_plat_otg_data s5pc210_otg_data;
  62
  63 int board_init(void)
  64 {
  65         gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
  66
  67         check_hw_revision();
  68         printf("HW Revision:\t0x%x\n", board_rev);
  69
  70         return 0;
  71 }
  72
  73 void i2c_init_board(void)
  74 {
  75         struct exynos4_gpio_part1 *gpio1 =
  76                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
  77         struct exynos4_gpio_part2 *gpio2 =
  78                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  79
  80         /* I2C_5 -> PMIC */
  81         s5p_gpio_direction_output(&gpio1->b, 7, 1);
  82         s5p_gpio_direction_output(&gpio1->b, 6, 1);
  83         /* I2C_9 -> FG */
  84         s5p_gpio_direction_output(&gpio2->y4, 0, 1);
  85         s5p_gpio_direction_output(&gpio2->y4, 1, 1);
  86 }
  87
  88 static void trats_low_power_mode(void)
  89 {
  90         struct exynos4_clock *clk =
  91             (struct exynos4_clock *)samsung_get_base_clock();
  92         struct exynos4_power *pwr =
  93             (struct exynos4_power *)samsung_get_base_power();
  94
  95         /* Power down CORE1 */
  96         /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
  97         writel(0x0, &pwr->arm_core1_configuration);
  98
  99         /* Change the APLL frequency */
 100         /* ENABLE (1 enable) | LOCKED (1 locked)  */
 101         /* [31]              | [29]               */
 102         /* FSEL      | MDIV          | PDIV            | SDIV */
 103         /* [27]      | [25:16]       | [13:8]          | [2:0]      */
 104         writel(0xa0c80604, &clk->apll_con0);
 105
 106         /* Change CPU0 clock divider */
 107         /* CORE2_RATIO  | APLL_RATIO   | PCLK_DBG_RATIO | ATB_RATIO  */
 108         /* [30:28]      | [26:24]      | [22:20]        | [18:16]    */
 109         /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO   | CORE_RATIO */
 110         /* [14:12]      | [10:8]       | [6:4]          | [2:0]      */
 111         writel(0x00000100, &clk->div_cpu0);
 112
 113         /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
 114         while (readl(&clk->div_stat_cpu0) & 0x1111111)
 115                 continue;
 116
 117         /* Change clock divider ratio for DMC */
 118         /* DMCP_RATIO                  | DMCD_RATIO  */
 119         /* [22:20]                     | [18:16]     */
 120         /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO   | ACP_RATIO */
 121         /* [14:12]   | [10:8]     | [6:4]            | [2:0]     */
 122         writel(0x13113117, &clk->div_dmc0);
 123
 124         /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
 125         while (readl(&clk->div_stat_dmc0) & 0x11111111)
 126                 continue;
 127
 128         /* Turn off unnecessary power domains */
 129         writel(0x0, &pwr->xxti_configuration);  /* XXTI */
 130         writel(0x0, &pwr->cam_configuration);   /* CAM */
 131         writel(0x0, &pwr->tv_configuration);    /* TV */
 132         writel(0x0, &pwr->mfc_configuration);   /* MFC */
 133         writel(0x0, &pwr->g3d_configuration);   /* G3D */
 134         writel(0x0, &pwr->gps_configuration);   /* GPS */
 135         writel(0x0, &pwr->gps_alive_configuration);     /* GPS_ALIVE */
 136
 137         /* Turn off unnecessary clocks */
 138         writel(0x0, &clk->gate_ip_cam); /* CAM */
 139         writel(0x0, &clk->gate_ip_tv);          /* TV */
 140         writel(0x0, &clk->gate_ip_mfc); /* MFC */
 141         writel(0x0, &clk->gate_ip_g3d); /* G3D */
 142         writel(0x0, &clk->gate_ip_image);       /* IMAGE */
 143         writel(0x0, &clk->gate_ip_gps); /* GPS */
 144 }
 145
 146 static int pmic_init_max8997(void)
 147 {
 148         struct pmic *p = pmic_get("MAX8997_PMIC");
 149         int i = 0, ret = 0;
 150         u32 val;
 151
 152         if (pmic_probe(p))
 153                 return -1;
 154
 155         /* BUCK1 VARM: 1.2V */
 156         val = (1200000 - 650000) / 25000;
 157         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
 158         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 159         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
 160
 161         /* BUCK2 VINT: 1.1V */
 162         val = (1100000 - 650000) / 25000;
 163         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
 164         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 165         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
 166
 167
 168         /* BUCK3 G3D: 1.1V - OFF */
 169         ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
 170         val &= ~ENBUCK;
 171         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
 172
 173         val = (1100000 - 750000) / 50000;
 174         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
 175
 176         /* BUCK4 CAMISP: 1.2V - OFF */
 177         ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
 178         val &= ~ENBUCK;
 179         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
 180
 181         val = (1200000 - 650000) / 25000;
 182         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
 183
 184         /* BUCK5 VMEM: 1.2V */
 185         val = (1200000 - 650000) / 25000;
 186         for (i = 0; i < 8; i++)
 187                 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
 188
 189         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 190         ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
 191
 192         /* BUCK6 CAM AF: 2.8V */
 193         /* No Voltage Setting Register */
 194         /* GNSLCT 3.0X */
 195         val = GNSLCT;
 196         ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
 197
 198         /* BUCK7 VCC_SUB: 2.0V */
 199         val = (2000000 - 750000) / 50000;
 200         ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
 201
 202         /* LDO1 VADC: 3.3V */
 203         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 204         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
 205
 206         /* LDO1 Disable active discharging */
 207         ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
 208         val &= ~LDO_ADE;
 209         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
 210
 211         /* LDO2 VALIVE: 1.1V */
 212         val = max8997_reg_ldo(1100000) | EN_LDO;
 213         ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
 214
 215         /* LDO3 VUSB/MIPI: 1.1V */
 216         val = max8997_reg_ldo(1100000) | DIS_LDO;       /* OFF */
 217         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
 218
 219         /* LDO4 VMIPI: 1.8V */
 220         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 221         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
 222
 223         /* LDO5 VHSIC: 1.2V */
 224         val = max8997_reg_ldo(1200000) | DIS_LDO;       /* OFF */
 225         ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
 226
 227         /* LDO6 VCC_1.8V_PDA: 1.8V */
 228         val = max8997_reg_ldo(1800000) | EN_LDO;
 229         ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
 230
 231         /* LDO7 CAM_ISP: 1.8V */
 232         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 233         ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
 234
 235         /* LDO8 VDAC/VUSB: 3.3V */
 236         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 237         ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
 238
 239         /* LDO9 VCC_2.8V_PDA: 2.8V */
 240         val = max8997_reg_ldo(2800000) | EN_LDO;
 241         ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
 242
 243         /* LDO10 VPLL: 1.1V */
 244         val = max8997_reg_ldo(1100000) | EN_LDO;
 245         ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
 246
 247         /* LDO11 TOUCH: 2.8V */
 248         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 249         ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
 250
 251         /* LDO12 VTCAM: 1.8V */
 252         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 253         ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
 254
 255         /* LDO13 VCC_3.0_LCD: 3.0V */
 256         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 257         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
 258
 259         /* LDO14 MOTOR: 3.0V */
 260         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 261         ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
 262
 263         /* LDO15 LED_A: 2.8V */
 264         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 265         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
 266
 267         /* LDO16 CAM_SENSOR: 1.8V */
 268         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 269         ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
 270
 271         /* LDO17 VTF: 2.8V */
 272         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 273         ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
 274
 275         /* LDO18 TOUCH_LED 3.3V */
 276         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 277         ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
 278
 279         /* LDO21 VDDQ: 1.2V */
 280         val = max8997_reg_ldo(1200000) | EN_LDO;
 281         ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
 282
 283         /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
 284         val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
 285                 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
 286         ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
 287
 288         if (ret) {
 289                 puts("MAX8997 PMIC setting error!\n");
 290                 return -1;
 291         }
 292         return 0;
 293 }
 294
 295 int power_init_board(void)
 296 {
 297         int chrg, ret;
 298         struct power_battery *pb;
 299         struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
 300
 301         ret = pmic_init(I2C_5);
 302         ret |= pmic_init_max8997();
 303         ret |= power_fg_init(I2C_9);
 304         ret |= power_muic_init(I2C_5);
 305         ret |= power_bat_init(0);
 306         if (ret)
 307                 return ret;
 308
 309         p_fg = pmic_get("MAX17042_FG");
 310         if (!p_fg) {
 311                 puts("MAX17042_FG: Not found\n");
 312                 return -ENODEV;
 313         }
 314
 315         p_chrg = pmic_get("MAX8997_PMIC");
 316         if (!p_chrg) {
 317                 puts("MAX8997_PMIC: Not found\n");
 318                 return -ENODEV;
 319         }
 320
 321         p_muic = pmic_get("MAX8997_MUIC");
 322         if (!p_muic) {
 323                 puts("MAX8997_MUIC: Not found\n");
 324                 return -ENODEV;
 325         }
 326
 327         p_bat = pmic_get("BAT_TRATS");
 328         if (!p_bat) {
 329                 puts("BAT_TRATS: Not found\n");
 330                 return -ENODEV;
 331         }
 332
 333         p_fg->parent =  p_bat;
 334         p_chrg->parent = p_bat;
 335         p_muic->parent = p_bat;
 336
 337         p_bat->low_power_mode = trats_low_power_mode;
 338         p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
 339
 340         pb = p_bat->pbat;
 341         chrg = p_muic->chrg->chrg_type(p_muic);
 342         debug("CHARGER TYPE: %d\n", chrg);
 343
 344         if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
 345                 puts("No battery detected\n");
 346                 return -1;
 347         }
 348
 349         p_fg->fg->fg_battery_check(p_fg, p_bat);
 350
 351         if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
 352                 puts("CHARGE Battery !\n");
 353
 354         return 0;
 355 }
 356
 357 int dram_init(void)
 358 {
 359         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
 360                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
 361                 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
 362                 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
 363
 364         return 0;
 365 }
 366
 367 void dram_init_banksize(void)
 368 {
 369         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 370         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 371         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 372         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 373         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 374         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
 375         gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 376         gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
 377 }
 378
 379 static unsigned int get_hw_revision(void)
 380 {
 381         struct exynos4_gpio_part1 *gpio =
 382                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 383         int hwrev = 0;
 384         int i;
 385
 386         /* hw_rev[3:0] == GPE1[3:0] */
 387         for (i = 0; i < 4; i++) {
 388                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
 389                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
 390         }
 391
 392         udelay(1);
 393
 394         for (i = 0; i < 4; i++)
 395                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
 396
 397         debug("hwrev 0x%x\n", hwrev);
 398
 399         return hwrev;
 400 }
 401
 402 static void check_hw_revision(void)
 403 {
 404         int hwrev;
 405
 406         hwrev = get_hw_revision();
 407
 408         board_rev |= hwrev;
 409 }
 410
 411 #ifdef CONFIG_DISPLAY_BOARDINFO
 412 int checkboard(void)
 413 {
 414         puts("Board:\tTRATS\n");
 415         return 0;
 416 }
 417 #endif
 418
 419 #ifdef CONFIG_GENERIC_MMC
 420 int board_mmc_init(bd_t *bis)
 421 {
 422         struct exynos4_gpio_part2 *gpio =
 423                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 424         int err;
 425
 426         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 427         s5p_gpio_direction_output(&gpio->k0, 2, 1);
 428         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 429
 430         /*
 431          * MMC device init
 432          * mmc0  : eMMC (8-bit buswidth)
 433          * mmc2  : SD card (4-bit buswidth)
 434          */
 435         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 436         if (err)
 437                 debug("SDMMC0 not configured\n");
 438         else
 439                 err = s5p_mmc_init(0, 8);
 440
 441         /* T-flash detect */
 442         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
 443         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
 444
 445         /*
 446          * Check the T-flash  detect pin
 447          * GPX3[4] T-flash detect pin
 448          */
 449         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
 450                 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
 451                 if (err)
 452                         debug("SDMMC2 not configured\n");
 453                 else
 454                         err = s5p_mmc_init(2, 4);
 455         }
 456
 457         return err;
 458 }
 459 #endif
 460
 461 #ifdef CONFIG_USB_GADGET
 462 static int s5pc210_phy_control(int on)
 463 {
 464         int ret = 0;
 465         u32 val = 0;
 466         struct pmic *p = pmic_get("MAX8997_PMIC");
 467         if (!p)
 468                 return -ENODEV;
 469
 470         if (pmic_probe(p))
 471                 return -1;
 472
 473         if (on) {
 474                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 475                                       ENSAFEOUT1, LDO_ON);
 476                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 477                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
 478
 479                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 480                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
 481         } else {
 482                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 483                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
 484
 485                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 486                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
 487                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 488                                       ENSAFEOUT1, LDO_OFF);
 489         }
 490
 491         if (ret) {
 492                 puts("MAX8997 LDO setting error!\n");
 493                 return -1;
 494         }
 495
 496         return 0;
 497 }
 498
 499 struct s3c_plat_otg_data s5pc210_otg_data = {
 500         .phy_control    = s5pc210_phy_control,
 501         .regs_phy       = EXYNOS4_USBPHY_BASE,
 502         .regs_otg       = EXYNOS4_USBOTG_BASE,
 503         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 504         .usb_flags      = PHY0_SLEEP,
 505 };
 506
 507 void board_usb_init(void)
 508 {
 509         debug("USB_udc_probe\n");
 510         s3c_udc_probe(&s5pc210_otg_data);
 511 }
 512 #endif
 513
 514 static void pmic_reset(void)
 515 {
 516         struct exynos4_gpio_part2 *gpio =
 517                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 518
 519         s5p_gpio_direction_output(&gpio->x0, 7, 1);
 520         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
 521 }
 522
 523 static void board_clock_init(void)
 524 {
 525         struct exynos4_clock *clk =
 526                 (struct exynos4_clock *)samsung_get_base_clock();
 527
 528         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 529         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 530         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 531         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 532
 533         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 534         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 535         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 536         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 537         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 538         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 539         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 540         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 541         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 542         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 543         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 544         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 545
 546         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 547         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 548         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 549         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 550         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 551         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 552         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 553         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 554         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 555         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 556         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 557         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 558
 559         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 560         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 561         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 562         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 563         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 564         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 565         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 566         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 567         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 568         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 569         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 570         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 571 }
 572
 573 static void board_power_init(void)
 574 {
 575         struct exynos4_power *pwr =
 576                 (struct exynos4_power *)samsung_get_base_power();
 577
 578         /* PS HOLD */
 579         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 580
 581         /* Set power down */
 582         writel(0, (unsigned int)&pwr->cam_configuration);
 583         writel(0, (unsigned int)&pwr->tv_configuration);
 584         writel(0, (unsigned int)&pwr->mfc_configuration);
 585         writel(0, (unsigned int)&pwr->g3d_configuration);
 586         writel(0, (unsigned int)&pwr->lcd1_configuration);
 587         writel(0, (unsigned int)&pwr->gps_configuration);
 588         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 589
 590         /* It is necessary to power down core 1 */
 591         /* to successfully boot CPU1 in kernel */
 592         writel(0, (unsigned int)&pwr->arm_core1_configuration);
 593 }
 594
 595 static void board_uart_init(void)
 596 {
 597         struct exynos4_gpio_part1 *gpio1 =
 598                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 599         struct exynos4_gpio_part2 *gpio2 =
 600                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 601         int i;
 602
 603         /*
 604          * UART2 GPIOs
 605          * GPA1CON[0] = UART_2_RXD(2)
 606          * GPA1CON[1] = UART_2_TXD(2)
 607          * GPA1CON[2] = I2C_3_SDA (3)
 608          * GPA1CON[3] = I2C_3_SCL (3)
 609          */
 610
 611         for (i = 0; i < 4; i++) {
 612                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 613                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 614         }
 615
 616         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 617         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 618         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 619 }
 620
 621 int board_early_init_f(void)
 622 {
 623         wdt_stop();
 624         pmic_reset();
 625         board_clock_init();
 626         board_uart_init();
 627         board_power_init();
 628
 629         return 0;
 630 }
 631
 632 void exynos_reset_lcd(void)
 633 {
 634         struct exynos4_gpio_part2 *gpio2 =
 635                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 636
 637         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 638         udelay(10000);
 639         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
 640         udelay(10000);
 641         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 642 }
 643
 644 static int lcd_power(void)
 645 {
 646         int ret = 0;
 647         struct pmic *p = pmic_get("MAX8997_PMIC");
 648         if (!p)
 649                 return -ENODEV;
 650
 651         if (pmic_probe(p))
 652                 return 0;
 653
 654         /* LDO15 voltage: 2.2v */
 655         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 656         /* LDO13 voltage: 3.0v */
 657         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 658
 659         if (ret) {
 660                 puts("MAX8997 LDO setting error!\n");
 661                 return -1;
 662         }
 663
 664         return 0;
 665 }
 666
 667 static struct mipi_dsim_config dsim_config = {
 668         .e_interface            = DSIM_VIDEO,
 669         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
 670         .e_pixel_format         = DSIM_24BPP_888,
 671         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
 672         .e_no_data_lane         = DSIM_DATA_LANE_4,
 673         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 674         .hfp                    = 1,
 675
 676         .p                      = 3,
 677         .m                      = 120,
 678         .s                      = 1,
 679
 680         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 681         .pll_stable_time        = 500,
 682
 683         /* escape clk : 10MHz */
 684         .esc_clk                = 20 * 1000000,
 685
 686         /* stop state holding counter after bta change count 0 ~ 0xfff */
 687         .stop_holding_cnt       = 0x7ff,
 688         /* bta timeout 0 ~ 0xff */
 689         .bta_timeout            = 0xff,
 690         /* lp rx timeout 0 ~ 0xffff */
 691         .rx_timeout             = 0xffff,
 692 };
 693
 694 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
 695         .lcd_panel_info = NULL,
 696         .dsim_config = &dsim_config,
 697 };
 698
 699 static struct mipi_dsim_lcd_device mipi_lcd_device = {
 700         .name   = "s6e8ax0",
 701         .id     = -1,
 702         .bus_id = 0,
 703         .platform_data  = (void *)&s6e8ax0_platform_data,
 704 };
 705
 706 static int mipi_power(void)
 707 {
 708         int ret = 0;
 709         struct pmic *p = pmic_get("MAX8997_PMIC");
 710         if (!p)
 711                 return -ENODEV;
 712
 713         if (pmic_probe(p))
 714                 return 0;
 715
 716         /* LDO3 voltage: 1.1v */
 717         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 718         /* LDO4 voltage: 1.8v */
 719         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 720
 721         if (ret) {
 722                 puts("MAX8997 LDO setting error!\n");
 723                 return -1;
 724         }
 725
 726         return 0;
 727 }
 728
 729 vidinfo_t panel_info = {
 730         .vl_freq        = 60,
 731         .vl_col         = 720,
 732         .vl_row         = 1280,
 733         .vl_width       = 720,
 734         .vl_height      = 1280,
 735         .vl_clkp        = CONFIG_SYS_HIGH,
 736         .vl_hsp         = CONFIG_SYS_LOW,
 737         .vl_vsp         = CONFIG_SYS_LOW,
 738         .vl_dp          = CONFIG_SYS_LOW,
 739         .vl_bpix        = 5,    /* Bits per pixel, 2^5 = 32 */
 740
 741         /* s6e8ax0 Panel infomation */
 742         .vl_hspw        = 5,
 743         .vl_hbpd        = 10,
 744         .vl_hfpd        = 10,
 745
 746         .vl_vspw        = 2,
 747         .vl_vbpd        = 1,
 748         .vl_vfpd        = 13,
 749         .vl_cmd_allow_len = 0xf,
 750
 751         .win_id         = 3,
 752         .dual_lcd_enabled = 0,
 753
 754         .init_delay     = 0,
 755         .power_on_delay = 0,
 756         .reset_delay    = 0,
 757         .interface_mode = FIMD_RGB_INTERFACE,
 758         .mipi_enabled   = 1,
 759 };
 760
 761 void init_panel_info(vidinfo_t *vid)
 762 {
 763         vid->logo_on    = 1,
 764         vid->resolution = HD_RESOLUTION,
 765         vid->rgb_mode   = MODE_RGB_P,
 766
 767 #ifdef CONFIG_TIZEN
 768         get_tizen_logo_info(vid);
 769 #endif
 770         mipi_lcd_device.reverse_panel = 1;
 771
 772         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
 773         s6e8ax0_platform_data.lcd_power = lcd_power;
 774         s6e8ax0_platform_data.mipi_power = mipi_power;
 775         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
 776         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
 777         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
 778         s6e8ax0_init();
 779         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
 780
 781         setenv("lcdinfo", "lcd=s6e8ax0");
 782 }
 783
 784 #ifdef CONFIG_USB_GADGET_MASS_STORAGE
 785 static int ums_read_sector(struct ums_device *ums_dev,
 786                            ulong start, lbaint_t blkcnt, void *buf)
 787 {
 788         if (ums_dev->mmc->block_dev.block_read(ums_dev->dev_num,
 789                         start + ums_dev->offset, blkcnt, buf) != blkcnt)
 790                 return -1;
 791
 792         return 0;
 793 }
 794
 795 static int ums_write_sector(struct ums_device *ums_dev,
 796                             ulong start, lbaint_t blkcnt, const void *buf)
 797 {
 798         if (ums_dev->mmc->block_dev.block_write(ums_dev->dev_num,
 799                         start + ums_dev->offset, blkcnt, buf) != blkcnt)
 800                 return -1;
 801
 802         return 0;
 803 }
 804
 805 static void ums_get_capacity(struct ums_device *ums_dev,
 806                              long long int *capacity)
 807 {
 808         long long int tmp_capacity;
 809
 810         tmp_capacity = (long long int) ((ums_dev->offset + ums_dev->part_size)
 811                                         * SECTOR_SIZE);
 812         *capacity = ums_dev->mmc->capacity - tmp_capacity;
 813 }
 814
 815 static struct ums_board_info ums_board = {
 816         .read_sector = ums_read_sector,
 817         .write_sector = ums_write_sector,
 818         .get_capacity = ums_get_capacity,
 819         .name = "TRATS UMS disk",
 820         .ums_dev = {
 821                 .mmc = NULL,
 822                 .dev_num = 0,
 823                 .offset = 0,
 824                 .part_size = 0.
 825         },
 826 };
 827
 828 struct ums_board_info *board_ums_init(unsigned int dev_num, unsigned int offset,
 829                                       unsigned int part_size)
 830 {
 831         struct mmc *mmc;
 832
 833         mmc = find_mmc_device(dev_num);
 834         if (!mmc)
 835                 return NULL;
 836
 837         ums_board.ums_dev.mmc = mmc;
 838         ums_board.ums_dev.dev_num = dev_num;
 839         ums_board.ums_dev.offset = offset;
 840         ums_board.ums_dev.part_size = part_size;
 841
 842         return &ums_board;
 843 }
 844 #endif