board/sunxi/board.c

   1 /*
   2  * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
   3  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4  *
   5  * (C) Copyright 2007-2011
   6  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   7  * Tom Cubie <tangliang@allwinnertech.com>
   8  *
   9  * Some board init for the Allwinner A10-evb board.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #ifdef CONFIG_AXP152_POWER
  16 #include <axp152.h>
  17 #endif
  18 #ifdef CONFIG_AXP209_POWER
  19 #include <axp209.h>
  20 #endif
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/dram.h>
  23 #include <asm/arch/gpio.h>
  24 #include <asm/arch/mmc.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 /* add board specific code here */
  29 int board_init(void)
  30 {
  31         int id_pfr1;
  32
  33         gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
  34
  35         asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
  36         debug("id_pfr1: 0x%08x\n", id_pfr1);
  37         /* Generic Timer Extension available? */
  38         if ((id_pfr1 >> 16) & 0xf) {
  39                 debug("Setting CNTFRQ\n");
  40                 /* CNTFRQ == 24 MHz */
  41                 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
  42         }
  43
  44         return 0;
  45 }
  46
  47 int dram_init(void)
  48 {
  49         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
  50
  51         return 0;
  52 }
  53
  54 #ifdef CONFIG_GENERIC_MMC
  55 static void mmc_pinmux_setup(int sdc)
  56 {
  57         unsigned int pin;
  58
  59         switch (sdc) {
  60         case 0:
  61                 /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
  62                 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
  63                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
  64                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  65                         sunxi_gpio_set_drv(pin, 2);
  66                 }
  67                 break;
  68
  69         case 1:
  70                 /* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
  71                 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
  72                         sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
  73                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  74                         sunxi_gpio_set_drv(pin, 2);
  75                 }
  76                 break;
  77
  78         case 2:
  79                 /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
  80                 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
  81                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
  82                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  83                         sunxi_gpio_set_drv(pin, 2);
  84                 }
  85                 break;
  86
  87         case 3:
  88                 /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
  89                 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
  90                         sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
  91                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  92                         sunxi_gpio_set_drv(pin, 2);
  93                 }
  94                 break;
  95
  96         default:
  97                 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
  98                 break;
  99         }
 100 }
 101
 102 int board_mmc_init(bd_t *bis)
 103 {
 104         mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
 105         sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
 106 #if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
 107         mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
 108         sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
 109 #endif
 110
 111         return 0;
 112 }
 113 #endif
 114
 115 void i2c_init_board(void)
 116 {
 117         sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
 118         sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
 119         clock_twi_onoff(0, 1);
 120 }
 121
 122 #ifdef CONFIG_SPL_BUILD
 123 void sunxi_board_init(void)
 124 {
 125         int power_failed = 0;
 126         unsigned long ramsize;
 127
 128 #ifdef CONFIG_AXP152_POWER
 129         power_failed = axp152_init();
 130         power_failed |= axp152_set_dcdc2(1400);
 131         power_failed |= axp152_set_dcdc3(1500);
 132         power_failed |= axp152_set_dcdc4(1250);
 133         power_failed |= axp152_set_ldo2(3000);
 134 #endif
 135 #ifdef CONFIG_AXP209_POWER
 136         power_failed |= axp209_init();
 137         power_failed |= axp209_set_dcdc2(1400);
 138         power_failed |= axp209_set_dcdc3(1250);
 139         power_failed |= axp209_set_ldo2(3000);
 140         power_failed |= axp209_set_ldo3(2800);
 141         power_failed |= axp209_set_ldo4(2800);
 142 #endif
 143
 144         printf("DRAM:");
 145         ramsize = sunxi_dram_init();
 146         printf(" %lu MiB\n", ramsize >> 20);
 147         if (!ramsize)
 148                 hang();
 149
 150         /*
 151          * Only clock up the CPU to full speed if we are reasonably
 152          * assured it's being powered with suitable core voltage
 153          */
 154         if (!power_failed)
 155                 clock_set_pll1(CONFIG_CLK_FULL_SPEED);
 156         else
 157                 printf("Failed to set core voltage! Can't set CPU frequency\n");
 158 }
 159 #endif