board/ti/omap5_uevm/evm.c

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  * Aneesh V       <aneesh@ti.com>
   5  * Steve Sakoman  <steve@sakoman.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #include <common.h>
  10 #include <palmas.h>
  11 #include <asm/arch/omap.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/arch/mmc_host_def.h>
  14 #include <tca642x.h>
  15 #include <usb.h>
  16 #include <linux/usb/gadget.h>
  17 #include <dwc3-uboot.h>
  18 #include <dwc3-omap-uboot.h>
  19 #include <ti-usb-phy-uboot.h>
  20
  21 #include "mux_data.h"
  22
  23 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
  24 #include <sata.h>
  25 #include <usb.h>
  26 #include <asm/gpio.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/ehci.h>
  29 #include <asm/ehci-omap.h>
  30 #include <asm/arch/sata.h>
  31
  32 #define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
  33 #define DIE_ID_REG_OFFSET       0x200
  34
  35 #endif
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 const struct omap_sysinfo sysinfo = {
  40         "Board: OMAP5432 uEVM\n"
  41 };
  42
  43 /**
  44  * @brief tca642x_init - uEVM default values for the GPIO expander
  45  * input reg, output reg, polarity reg, configuration reg
  46  */
  47 struct tca642x_bank_info tca642x_init[] = {
  48         { .input_reg = 0x00,
  49           .output_reg = 0x04,
  50           .polarity_reg = 0x00,
  51           .configuration_reg = 0x80 },
  52         { .input_reg = 0x00,
  53           .output_reg = 0x00,
  54           .polarity_reg = 0x00,
  55           .configuration_reg = 0xff },
  56         { .input_reg = 0x00,
  57           .output_reg = 0x00,
  58           .polarity_reg = 0x00,
  59           .configuration_reg = 0x40 },
  60 };
  61
  62 #ifdef CONFIG_USB_DWC3
  63 static struct dwc3_device usb_otg_ss = {
  64         .maximum_speed = USB_SPEED_SUPER,
  65         .base = OMAP5XX_USB_OTG_SS_BASE,
  66         .tx_fifo_resize = false,
  67         .index = 0,
  68 };
  69
  70 static struct dwc3_omap_device usb_otg_ss_glue = {
  71         .base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE,
  72         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  73         .index = 0,
  74 };
  75
  76 static struct ti_usb_phy_device usb_phy_device = {
  77         .pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL,
  78         .usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER,
  79         .usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER,
  80         .index = 0,
  81 };
  82
  83 int board_usb_init(int index, enum usb_init_type init)
  84 {
  85         if (index) {
  86                 printf("Invalid Controller Index\n");
  87                 return -EINVAL;
  88         }
  89
  90         if (init == USB_INIT_DEVICE) {
  91                 usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL;
  92                 usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  93         } else {
  94                 usb_otg_ss.dr_mode = USB_DR_MODE_HOST;
  95                 usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
  96         }
  97
  98         ti_usb_phy_uboot_init(&usb_phy_device);
  99         dwc3_omap_uboot_init(&usb_otg_ss_glue);
 100         dwc3_uboot_init(&usb_otg_ss);
 101
 102         return 0;
 103 }
 104
 105 int board_usb_cleanup(int index, enum usb_init_type init)
 106 {
 107         if (index) {
 108                 printf("Invalid Controller Index\n");
 109                 return -EINVAL;
 110         }
 111
 112         ti_usb_phy_uboot_exit(index);
 113         dwc3_uboot_exit(index);
 114         dwc3_omap_uboot_exit(index);
 115
 116         return 0;
 117 }
 118
 119 int usb_gadget_handle_interrupts(int index)
 120 {
 121         u32 status;
 122
 123         status = dwc3_omap_uboot_interrupt_status(index);
 124         if (status)
 125                 dwc3_uboot_handle_interrupt(index);
 126
 127         return 0;
 128 }
 129 #endif
 130
 131 /**
 132  * @brief board_init
 133  *
 134  * @return 0
 135  */
 136 int board_init(void)
 137 {
 138         gpmc_init();
 139         gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
 140         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 141
 142         tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
 143
 144         return 0;
 145 }
 146
 147 int board_eth_init(bd_t *bis)
 148 {
 149         return 0;
 150 }
 151
 152 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
 153 static void enable_host_clocks(void)
 154 {
 155         int auxclk;
 156         int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
 157                                 OPTFCLKEN_HSIC480M_P3_CLK |
 158                                 OPTFCLKEN_HSIC60M_P2_CLK |
 159                                 OPTFCLKEN_HSIC480M_P2_CLK |
 160                                 OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
 161
 162         /* Enable port 2 and 3 clocks*/
 163         setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
 164
 165         /* Enable port 2 and 3 usb host ports tll clocks*/
 166         setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
 167                         (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
 168 #ifdef CONFIG_USB_XHCI_OMAP
 169         /* Enable the USB OTG Super speed clocks */
 170         setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
 171                         (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
 172 #endif
 173
 174         auxclk = readl((*prcm)->scrm_auxclk1);
 175         /* Request auxilary clock */
 176         auxclk |= AUXCLK_ENABLE_MASK;
 177         writel(auxclk, (*prcm)->scrm_auxclk1);
 178 }
 179 #endif
 180
 181 /**
 182  * @brief misc_init_r - Configure EVM board specific configurations
 183  * such as power configurations, ethernet initialization as phase2 of
 184  * boot sequence
 185  *
 186  * @return 0
 187  */
 188 int misc_init_r(void)
 189 {
 190         int reg;
 191         u32 id[4];
 192
 193 #ifdef CONFIG_PALMAS_POWER
 194         palmas_init_settings();
 195 #endif
 196
 197         reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
 198
 199         id[0] = readl(reg);
 200         id[1] = readl(reg + 0x8);
 201         id[2] = readl(reg + 0xC);
 202         id[3] = readl(reg + 0x10);
 203         usb_fake_mac_from_die_id(id);
 204
 205         return 0;
 206 }
 207
 208 void set_muxconf_regs_essential(void)
 209 {
 210         do_set_mux((*ctrl)->control_padconf_core_base,
 211                    core_padconf_array_essential,
 212                    sizeof(core_padconf_array_essential) /
 213                    sizeof(struct pad_conf_entry));
 214
 215         do_set_mux((*ctrl)->control_padconf_wkup_base,
 216                    wkup_padconf_array_essential,
 217                    sizeof(wkup_padconf_array_essential) /
 218                    sizeof(struct pad_conf_entry));
 219 }
 220
 221 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 222 int board_mmc_init(bd_t *bis)
 223 {
 224         omap_mmc_init(0, 0, 0, -1, -1);
 225         omap_mmc_init(1, 0, 0, -1, -1);
 226         return 0;
 227 }
 228 #endif
 229
 230 #ifdef CONFIG_USB_EHCI
 231 static struct omap_usbhs_board_data usbhs_bdata = {
 232         .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
 233         .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
 234         .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
 235 };
 236
 237 int ehci_hcd_init(int index, enum usb_init_type init,
 238                 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 239 {
 240         int ret;
 241
 242         enable_host_clocks();
 243
 244         ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 245         if (ret < 0) {
 246                 puts("Failed to initialize ehci\n");
 247                 return ret;
 248         }
 249
 250         return 0;
 251 }
 252
 253 int ehci_hcd_stop(void)
 254 {
 255         int ret;
 256
 257         ret = omap_ehci_hcd_stop();
 258         return ret;
 259 }
 260
 261 void usb_hub_reset_devices(int port)
 262 {
 263         /* The LAN9730 needs to be reset after the port power has been set. */
 264         if (port == 3) {
 265                 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
 266                 udelay(10);
 267                 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
 268         }
 269 }
 270 #endif
 271
 272 #ifdef CONFIG_USB_XHCI_OMAP
 273 /**
 274  * @brief board_usb_init - Configure EVM board specific configurations
 275  * for the LDO's and clocks for the USB blocks.
 276  *
 277  * @return 0
 278  */
 279 int board_usb_init(int index, enum usb_init_type init)
 280 {
 281         int ret;
 282 #ifdef CONFIG_PALMAS_USB_SS_PWR
 283         ret = palmas_enable_ss_ldo();
 284 #endif
 285
 286         enable_host_clocks();
 287
 288         return 0;
 289 }
 290 #endif