Add TQ Systems TQMa6 board support
[karo-tx-uboot.git] / board / tqc / tqma6 / tqma6_mba6.c
1 /*
2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
3  * Author: Fabio Estevam <fabio.estevam@freescale.com>
4  *
5  * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
6  * Author: Markus Niebel <markus.niebel@tq-group.com>
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/errno.h>
18 #include <asm/gpio.h>
19 #include <asm/imx-common/mxc_i2c.h>
20
21 #include <common.h>
22 #include <fsl_esdhc.h>
23 #include <libfdt.h>
24 #include <malloc.h>
25 #include <i2c.h>
26 #include <micrel.h>
27 #include <miiphy.h>
28 #include <mmc.h>
29 #include <netdev.h>
30
31 #include "tqma6_bb.h"
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
37
38 #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
39         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
40
41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
42         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
43
44 #define GPIO_OUT_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
45         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
46
47 #define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
48         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
49
50 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
51         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
52
53 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
54         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
55         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
56
57 #if defined(CONFIG_MX6Q)
58
59 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII    0x02e0790
60 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM        0x02e07ac
61
62 #elif defined(CONFIG_MX6S)
63
64 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII    0x02e0768
65 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM        0x02e0788
66
67 #else
68
69 #error "need to define target CPU"
70
71 #endif
72
73 #define ENET_RX_PAD_CTRL        (PAD_CTL_DSE_34ohm)
74 #define ENET_TX_PAD_CTRL        (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
75 #define ENET_CLK_PAD_CTRL       (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
76                                  PAD_CTL_DSE_34ohm)
77 #define ENET_MDIO_PAD_CTRL      (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
78                                  PAD_CTL_DSE_60ohm)
79
80 /* disable on die termination for RGMII */
81 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE        0x00000000
82 /* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
83 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V       0x00080000
84 /* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
85 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V       0x000C0000
86
87 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25)
88
89 static iomux_v3_cfg_t const mba6_enet_pads[] = {
90         NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO,      ENET_MDIO_PAD_CTRL),
91         NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC,        ENET_MDIO_PAD_CTRL),
92
93         NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC,      ENET_TX_PAD_CTRL),
94         NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0,      ENET_TX_PAD_CTRL),
95         NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1,      ENET_TX_PAD_CTRL),
96         NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2,      ENET_TX_PAD_CTRL),
97         NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3,      ENET_TX_PAD_CTRL),
98         NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL,
99                      ENET_TX_PAD_CTRL),
100         NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL),
101         /*
102          * these pins are also used for config strapping by phy
103          */
104         NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0,      ENET_RX_PAD_CTRL),
105         NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1,      ENET_RX_PAD_CTRL),
106         NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2,      ENET_RX_PAD_CTRL),
107         NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3,      ENET_RX_PAD_CTRL),
108         NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC,      ENET_RX_PAD_CTRL),
109         NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL,
110                      ENET_RX_PAD_CTRL),
111         /* KSZ9031 PHY Reset */
112         NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25,   GPIO_OUT_PAD_CTRL),
113 };
114
115 static void mba6_setup_iomuxc_enet(void)
116 {
117         __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
118                      (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
119         __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
120                      (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
121
122         imx_iomux_v3_setup_multiple_pads(mba6_enet_pads,
123                                          ARRAY_SIZE(mba6_enet_pads));
124
125         /* Reset PHY */
126         gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
127         /* Need delay 10ms after power on according to KSZ9031 spec */
128         udelay(1000 * 10);
129         gpio_set_value(ENET_PHY_RESET_GPIO, 1);
130         /*
131          * KSZ9031 manual: 100 usec wait time after reset before communication
132          * over MDIO
133          * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
134          * reset before the phy sees a high level
135          */
136         udelay(200);
137 }
138
139 static iomux_v3_cfg_t const mba6_uart2_pads[] = {
140         NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
141         NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
142 };
143
144 static void mba6_setup_iomuxc_uart(void)
145 {
146         imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
147                                          ARRAY_SIZE(mba6_uart2_pads));
148 }
149
150 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
151 #define USDHC2_WP_GPIO  IMX_GPIO_NR(1, 2)
152
153 int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
154 {
155         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
156         int ret = 0;
157
158         if (cfg->esdhc_base == USDHC2_BASE_ADDR)
159                 ret = !gpio_get_value(USDHC2_CD_GPIO);
160
161         return ret;
162 }
163
164 int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
165 {
166         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
167         int ret = 0;
168
169         if (cfg->esdhc_base == USDHC2_BASE_ADDR)
170                 ret = gpio_get_value(USDHC2_WP_GPIO);
171
172         return ret;
173 }
174
175 static struct fsl_esdhc_cfg mba6_usdhc_cfg = {
176         .esdhc_base = USDHC2_BASE_ADDR,
177         .max_bus_width = 4,
178 };
179
180 static iomux_v3_cfg_t const mba6_usdhc2_pads[] = {
181         NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK,          USDHC_CLK_PAD_CTRL),
182         NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD,          USDHC_PAD_CTRL),
183         NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0,       USDHC_PAD_CTRL),
184         NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1,       USDHC_PAD_CTRL),
185         NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2,       USDHC_PAD_CTRL),
186         NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3,       USDHC_PAD_CTRL),
187         /* CD */
188         NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04,        GPIO_IN_PAD_CTRL),
189         /* WP */
190         NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02,        GPIO_IN_PAD_CTRL),
191 };
192
193 int tqma6_bb_board_mmc_init(bd_t *bis)
194 {
195         imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads,
196                                          ARRAY_SIZE(mba6_usdhc2_pads));
197         gpio_direction_input(USDHC2_CD_GPIO);
198         gpio_direction_input(USDHC2_WP_GPIO);
199
200         mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
201         if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg))
202                 puts("Warning: failed to initialize SD\n");
203
204         return 0;
205 }
206
207 static struct i2c_pads_info mba6_i2c1_pads = {
208 /* I2C1: MBa6x */
209         .scl = {
210                 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL,
211                                          I2C_PAD_CTRL),
212                 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27,
213                                           I2C_PAD_CTRL),
214                 .gp = IMX_GPIO_NR(5, 27)
215         },
216         .sda = {
217                 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA,
218                                          I2C_PAD_CTRL),
219                 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26,
220                                           I2C_PAD_CTRL),
221                 .gp = IMX_GPIO_NR(5, 26)
222         }
223 };
224
225 static void mba6_setup_i2c(void)
226 {
227         /* use logical index for bus, e.g. I2C1 -> 0 */
228         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
229 }
230
231
232 static iomux_v3_cfg_t const mba6_ecspi1_pads[] = {
233         NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL),
234         NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL),
235 };
236
237 static unsigned const mba6_ecspi1_cs[] = {
238         IMX_GPIO_NR(3, 24),
239         IMX_GPIO_NR(3, 25),
240 };
241
242 static void mba6_setup_iomuxc_spi(void)
243 {
244         unsigned i;
245
246         for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i)
247                 gpio_direction_output(mba6_ecspi1_cs[i], 1);
248         imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads,
249                                          ARRAY_SIZE(mba6_ecspi1_pads));
250 }
251
252 int board_phy_config(struct phy_device *phydev)
253 {
254 /*
255  * optimized pad skew values depends on CPU variant on the TQMa6x module:
256  * i.MX6Q/D or i.MX6DL/S
257  */
258 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
259 #define MBA6X_KSZ9031_CTRL_SKEW 0x0032
260 #define MBA6X_KSZ9031_CLK_SKEW  0x03ff
261 #define MBA6X_KSZ9031_RX_SKEW   0x3333
262 #define MBA6X_KSZ9031_TX_SKEW   0x2036
263 #elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
264 #define MBA6X_KSZ9031_CTRL_SKEW 0x0030
265 #define MBA6X_KSZ9031_CLK_SKEW  0x03ff
266 #define MBA6X_KSZ9031_RX_SKEW   0x3333
267 #define MBA6X_KSZ9031_TX_SKEW   0x2052
268 #else
269 #error
270 #endif
271         /* min rx/tx ctrl delay */
272         ksz9031_phy_extended_write(phydev, 2,
273                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
274                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
275                                    MBA6X_KSZ9031_CTRL_SKEW);
276         /* min rx delay */
277         ksz9031_phy_extended_write(phydev, 2,
278                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
279                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
280                                    MBA6X_KSZ9031_RX_SKEW);
281         /* max tx delay */
282         ksz9031_phy_extended_write(phydev, 2,
283                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
284                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
285                                    MBA6X_KSZ9031_TX_SKEW);
286         /* rx/tx clk skew */
287         ksz9031_phy_extended_write(phydev, 2,
288                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
289                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
290                                    MBA6X_KSZ9031_CLK_SKEW);
291
292         phydev->drv->config(phydev);
293
294         return 0;
295 }
296
297 int board_eth_init(bd_t *bis)
298 {
299         uint32_t base = IMX_FEC_BASE;
300         struct mii_dev *bus = NULL;
301         struct phy_device *phydev = NULL;
302         int ret;
303
304         bus = fec_get_miibus(base, -1);
305         if (!bus)
306                 return 0;
307         /* scan phy */
308         phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
309                                         PHY_INTERFACE_MODE_RGMII);
310
311         if (!phydev) {
312                 free(bus);
313                 puts("No phy found\n");
314                 return 0;
315         }
316         ret  = fec_probe(bis, -1, base, bus, phydev);
317         if (ret) {
318                 puts("FEC MXC: probe failed\n");
319                 free(phydev);
320                 free(bus);
321         }
322
323         return 0;
324 }
325
326 int tqma6_bb_board_early_init_f(void)
327 {
328         mba6_setup_iomuxc_uart();
329
330         return 0;
331 }
332
333 int tqma6_bb_board_init(void)
334 {
335         mba6_setup_i2c();
336         mba6_setup_iomuxc_spi();
337         /* do it here - to have reset completed */
338         mba6_setup_iomuxc_enet();
339
340         return 0;
341 }
342
343 int tqma6_bb_board_late_init(void)
344 {
345         return 0;
346 }
347
348 const char *tqma6_bb_get_boardname(void)
349 {
350         return "MBa6x";
351 }
352
353 /*
354  * Device Tree Support
355  */
356 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
357 void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
358 {
359  /* TBD */
360 }
361 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */