2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/sys_proto.h>
13 DECLARE_GLOBAL_DATA_PTR;
18 /* It can be done differently */
19 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
20 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
21 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
22 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
30 idcode = zynq_slcr_get_idcode();
33 case XILINX_ZYNQ_7010:
36 case XILINX_ZYNQ_7020:
39 case XILINX_ZYNQ_7030:
42 case XILINX_ZYNQ_7045:
52 fpga_add(fpga_xilinx, &fpga);
60 int board_eth_init(bd_t *bis)
64 #ifdef CONFIG_XILINX_AXIEMAC
65 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
66 XILINX_AXIDMA_BASEADDR);
68 #ifdef CONFIG_XILINX_EMACLITE
71 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
74 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
77 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
81 #if defined(CONFIG_ZYNQ_GEM)
82 # if defined(CONFIG_ZYNQ_GEM0)
83 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
84 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
86 # if defined(CONFIG_ZYNQ_GEM1)
87 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
88 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
96 int board_mmc_init(bd_t *bd)
100 #if defined(CONFIG_ZYNQ_SDHCI)
101 # if defined(CONFIG_ZYNQ_SDHCI0)
102 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
104 # if defined(CONFIG_ZYNQ_SDHCI1)
105 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
114 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;