board/xilinx/zynqmp/zynqmp.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <netdev.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/io.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 int board_init(void)
  17 {
  18         return 0;
  19 }
  20
  21 int board_early_init_r(void)
  22 {
  23         u32 val;
  24
  25         val = readl(&crlapb_base->timestamp_ref_ctrl);
  26         val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  27         writel(val, &crlapb_base->timestamp_ref_ctrl);
  28
  29         /* Program freq register in System counter and enable system counter */
  30         writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
  31         writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
  32                ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
  33                &iou_scntr->counter_control_register);
  34
  35         return 0;
  36 }
  37
  38 int dram_init(void)
  39 {
  40         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  41
  42         return 0;
  43 }
  44
  45 int timer_init(void)
  46 {
  47         return 0;
  48 }
  49
  50 void reset_cpu(ulong addr)
  51 {
  52 }
  53
  54 int board_eth_init(bd_t *bis)
  55 {
  56         u32 ret = 0;
  57
  58 #if defined(CONFIG_ZYNQ_GEM)
  59 # if defined(CONFIG_ZYNQ_GEM0)
  60         ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
  61                                                 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
  62 # endif
  63 # if defined(CONFIG_ZYNQ_GEM1)
  64         ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
  65                                                 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
  66 # endif
  67 # if defined(CONFIG_ZYNQ_GEM2)
  68         ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2,
  69                                                 CONFIG_ZYNQ_GEM_PHY_ADDR2, 0);
  70 # endif
  71 # if defined(CONFIG_ZYNQ_GEM3)
  72         ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3,
  73                                                 CONFIG_ZYNQ_GEM_PHY_ADDR3, 0);
  74 # endif
  75 #endif
  76         return ret;
  77 }
  78
  79 #ifdef CONFIG_CMD_MMC
  80 int board_mmc_init(bd_t *bd)
  81 {
  82         int ret = 0;
  83
  84         u32 ver = zynqmp_get_silicon_version();
  85
  86         if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
  87 #if defined(CONFIG_ZYNQ_SDHCI)
  88 # if defined(CONFIG_ZYNQ_SDHCI0)
  89                 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
  90 # endif
  91 # if defined(CONFIG_ZYNQ_SDHCI1)
  92                 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
  93 # endif
  94 #endif
  95         }
  96
  97         return ret;
  98 }
  99 #endif
 100
 101 int board_late_init(void)
 102 {
 103         u32 reg = 0;
 104         u8 bootmode;
 105
 106         reg = readl(&crlapb_base->boot_mode);
 107         bootmode = reg & BOOT_MODES_MASK;
 108
 109         switch (bootmode) {
 110         case SD_MODE:
 111         case EMMC_MODE:
 112                 setenv("modeboot", "sdboot");
 113                 break;
 114         default:
 115                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 116                 break;
 117         }
 118
 119         return 0;
 120 }