drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19
  20 unsigned int picos_to_mclk(unsigned int picos);
  21
  22 /*
  23  * Determine Rtt value.
  24  *
  25  * This should likely be either board or controller specific.
  26  *
  27  * Rtt(nominal) - DDR2:
  28  *      0 = Rtt disabled
  29  *      1 = 75 ohm
  30  *      2 = 150 ohm
  31  *      3 = 50 ohm
  32  * Rtt(nominal) - DDR3:
  33  *      0 = Rtt disabled
  34  *      1 = 60 ohm
  35  *      2 = 120 ohm
  36  *      3 = 40 ohm
  37  *      4 = 20 ohm
  38  *      5 = 30 ohm
  39  *
  40  * FIXME: Apparently 8641 needs a value of 2
  41  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  42  *
  43  * FIXME: There was some effort down this line earlier:
  44  *
  45  *      unsigned int i;
  46  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  47  *              if (popts->dimmslot[i].num_valid_cs
  48  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  49  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  50  *                      rtt = 2;
  51  *                      break;
  52  *              }
  53  *      }
  54  */
  55 static inline int fsl_ddr_get_rtt(void)
  56 {
  57         int rtt;
  58
  59 #if defined(CONFIG_SYS_FSL_DDR1)
  60         rtt = 0;
  61 #elif defined(CONFIG_SYS_FSL_DDR2)
  62         rtt = 3;
  63 #else
  64         rtt = 0;
  65 #endif
  66
  67         return rtt;
  68 }
  69
  70 #ifdef CONFIG_SYS_FSL_DDR4
  71 /*
  72  * compute CAS write latency according to DDR4 spec
  73  * CWL = 9 for <= 1600MT/s
  74  *       10 for <= 1866MT/s
  75  *       11 for <= 2133MT/s
  76  *       12 for <= 2400MT/s
  77  *       14 for <= 2667MT/s
  78  *       16 for <= 2933MT/s
  79  *       18 for higher
  80  */
  81 static inline unsigned int compute_cas_write_latency(void)
  82 {
  83         unsigned int cwl;
  84         const unsigned int mclk_ps = get_memory_clk_period_ps();
  85         if (mclk_ps >= 1250)
  86                 cwl = 9;
  87         else if (mclk_ps >= 1070)
  88                 cwl = 10;
  89         else if (mclk_ps >= 935)
  90                 cwl = 11;
  91         else if (mclk_ps >= 833)
  92                 cwl = 12;
  93         else if (mclk_ps >= 750)
  94                 cwl = 14;
  95         else if (mclk_ps >= 681)
  96                 cwl = 16;
  97         else
  98                 cwl = 18;
  99
 100         return cwl;
 101 }
 102 #else
 103 /*
 104  * compute the CAS write latency according to DDR3 spec
 105  * CWL = 5 if tCK >= 2.5ns
 106  *       6 if 2.5ns > tCK >= 1.875ns
 107  *       7 if 1.875ns > tCK >= 1.5ns
 108  *       8 if 1.5ns > tCK >= 1.25ns
 109  *       9 if 1.25ns > tCK >= 1.07ns
 110  *       10 if 1.07ns > tCK >= 0.935ns
 111  *       11 if 0.935ns > tCK >= 0.833ns
 112  *       12 if 0.833ns > tCK >= 0.75ns
 113  */
 114 static inline unsigned int compute_cas_write_latency(void)
 115 {
 116         unsigned int cwl;
 117         const unsigned int mclk_ps = get_memory_clk_period_ps();
 118
 119         if (mclk_ps >= 2500)
 120                 cwl = 5;
 121         else if (mclk_ps >= 1875)
 122                 cwl = 6;
 123         else if (mclk_ps >= 1500)
 124                 cwl = 7;
 125         else if (mclk_ps >= 1250)
 126                 cwl = 8;
 127         else if (mclk_ps >= 1070)
 128                 cwl = 9;
 129         else if (mclk_ps >= 935)
 130                 cwl = 10;
 131         else if (mclk_ps >= 833)
 132                 cwl = 11;
 133         else if (mclk_ps >= 750)
 134                 cwl = 12;
 135         else {
 136                 cwl = 12;
 137                 printf("Warning: CWL is out of range\n");
 138         }
 139         return cwl;
 140 }
 141 #endif
 142
 143 /* Chip Select Configuration (CSn_CONFIG) */
 144 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 145                                const memctl_options_t *popts,
 146                                const dimm_params_t *dimm_params)
 147 {
 148         unsigned int cs_n_en = 0; /* Chip Select enable */
 149         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 150         unsigned int intlv_ctl = 0; /* Interleaving control */
 151         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 152         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 153         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 154         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 155         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 156         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 157         int go_config = 0;
 158 #ifdef CONFIG_SYS_FSL_DDR4
 159         unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
 160 #else
 161         unsigned int n_banks_per_sdram_device;
 162 #endif
 163
 164         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 165         switch (i) {
 166         case 0:
 167                 if (dimm_params[dimm_number].n_ranks > 0) {
 168                         go_config = 1;
 169                         /* These fields only available in CS0_CONFIG */
 170                         if (!popts->memctl_interleaving)
 171                                 break;
 172                         switch (popts->memctl_interleaving_mode) {
 173                         case FSL_DDR_256B_INTERLEAVING:
 174                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 175                         case FSL_DDR_PAGE_INTERLEAVING:
 176                         case FSL_DDR_BANK_INTERLEAVING:
 177                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 178                                 intlv_en = popts->memctl_interleaving;
 179                                 intlv_ctl = popts->memctl_interleaving_mode;
 180                                 break;
 181                         default:
 182                                 break;
 183                         }
 184                 }
 185                 break;
 186         case 1:
 187                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 188                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 189                         go_config = 1;
 190                 break;
 191         case 2:
 192                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 193                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 194                         go_config = 1;
 195                 break;
 196         case 3:
 197                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 198                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 199                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 200                         go_config = 1;
 201                 break;
 202         default:
 203                 break;
 204         }
 205         if (go_config) {
 206                 cs_n_en = 1;
 207                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 208                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 209                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 210 #ifdef CONFIG_SYS_FSL_DDR4
 211                 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
 212                 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
 213 #else
 214                 n_banks_per_sdram_device
 215                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 216                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 217 #endif
 218                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 219                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 220         }
 221         ddr->cs[i].config = (0
 222                 | ((cs_n_en & 0x1) << 31)
 223                 | ((intlv_en & 0x3) << 29)
 224                 | ((intlv_ctl & 0xf) << 24)
 225                 | ((ap_n_en & 0x1) << 23)
 226
 227                 /* XXX: some implementation only have 1 bit starting at left */
 228                 | ((odt_rd_cfg & 0x7) << 20)
 229
 230                 /* XXX: Some implementation only have 1 bit starting at left */
 231                 | ((odt_wr_cfg & 0x7) << 16)
 232
 233                 | ((ba_bits_cs_n & 0x3) << 14)
 234                 | ((row_bits_cs_n & 0x7) << 8)
 235 #ifdef CONFIG_SYS_FSL_DDR4
 236                 | ((bg_bits_cs_n & 0x3) << 4)
 237 #endif
 238                 | ((col_bits_cs_n & 0x7) << 0)
 239                 );
 240         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 241 }
 242
 243 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 244 /* FIXME: 8572 */
 245 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 246 {
 247         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 248
 249         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 250         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 251 }
 252
 253 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 254
 255 #if !defined(CONFIG_SYS_FSL_DDR1)
 256 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 257 {
 258 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 259         if (dimm_params[0].n_ranks == 4)
 260                 return 1;
 261 #endif
 262
 263 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 264         if ((dimm_params[0].n_ranks == 2) &&
 265                 (dimm_params[1].n_ranks == 2))
 266                 return 1;
 267
 268 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 269         if (dimm_params[0].n_ranks == 4)
 270                 return 1;
 271 #endif
 272 #endif
 273         return 0;
 274 }
 275
 276 /*
 277  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 278  *
 279  * Avoid writing for DDR I.  The new PQ38 DDR controller
 280  * dreams up non-zero default values to be backwards compatible.
 281  */
 282 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 283                                 const memctl_options_t *popts,
 284                                 const dimm_params_t *dimm_params)
 285 {
 286         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 287         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 288         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 289         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 290         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 291
 292         /* Active powerdown exit timing (tXARD and tXARDS). */
 293         unsigned char act_pd_exit_mclk;
 294         /* Precharge powerdown exit timing (tXP). */
 295         unsigned char pre_pd_exit_mclk;
 296         /* ODT powerdown exit timing (tAXPD). */
 297         unsigned char taxpd_mclk = 0;
 298         /* Mode register set cycle time (tMRD). */
 299         unsigned char tmrd_mclk;
 300
 301 #ifdef CONFIG_SYS_FSL_DDR4
 302         /* tXP=max(4nCK, 6ns) */
 303         int txp = max((get_memory_clk_period_ps() * 4), 6000); /* unit=ps */
 304         trwt_mclk = 2;
 305         twrt_mclk = 1;
 306         act_pd_exit_mclk = picos_to_mclk(txp);
 307         pre_pd_exit_mclk = act_pd_exit_mclk;
 308         /*
 309          * MRS_CYC = max(tMRD, tMOD)
 310          * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 311          */
 312         tmrd_mclk = max(24, picos_to_mclk(15000));
 313 #elif defined(CONFIG_SYS_FSL_DDR3)
 314         /*
 315          * (tXARD and tXARDS). Empirical?
 316          * The DDR3 spec has not tXARD,
 317          * we use the tXP instead of it.
 318          * tXP=max(3nCK, 7.5ns) for DDR3.
 319          * spec has not the tAXPD, we use
 320          * tAXPD=1, need design to confirm.
 321          */
 322         int txp = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 323         unsigned int data_rate = get_ddr_freq(0);
 324         tmrd_mclk = 4;
 325         /* set the turnaround time */
 326
 327         /*
 328          * for single quad-rank DIMM and two dual-rank DIMMs
 329          * to avoid ODT overlap
 330          */
 331         if (avoid_odt_overlap(dimm_params)) {
 332                 twwt_mclk = 2;
 333                 trrt_mclk = 1;
 334         }
 335         /* for faster clock, need more time for data setup */
 336         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 337
 338         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 339                 twrt_mclk = 1;
 340
 341         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 342                 act_pd_exit_mclk = 1;
 343                 pre_pd_exit_mclk = 1;
 344                 taxpd_mclk = 1;
 345         } else {
 346                 /* act_pd_exit_mclk = tXARD, see above */
 347                 act_pd_exit_mclk = picos_to_mclk(txp);
 348                 /* Mode register MR0[A12] is '1' - fast exit */
 349                 pre_pd_exit_mclk = act_pd_exit_mclk;
 350                 taxpd_mclk = 1;
 351         }
 352 #else /* CONFIG_SYS_FSL_DDR2 */
 353         /*
 354          * (tXARD and tXARDS). Empirical?
 355          * tXARD = 2 for DDR2
 356          * tXP=2
 357          * tAXPD=8
 358          */
 359         act_pd_exit_mclk = 2;
 360         pre_pd_exit_mclk = 2;
 361         taxpd_mclk = 8;
 362         tmrd_mclk = 2;
 363 #endif
 364
 365         if (popts->trwt_override)
 366                 trwt_mclk = popts->trwt;
 367
 368         ddr->timing_cfg_0 = (0
 369                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 370                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 371                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 372                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 373                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 374                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 375                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 376                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 377                 );
 378         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 379 }
 380 #endif  /* defined(CONFIG_SYS_FSL_DDR2) */
 381
 382 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 383 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 384                                const memctl_options_t *popts,
 385                                const common_timing_params_t *common_dimm,
 386                                unsigned int cas_latency,
 387                                unsigned int additive_latency)
 388 {
 389         /* Extended precharge to activate interval (tRP) */
 390         unsigned int ext_pretoact = 0;
 391         /* Extended Activate to precharge interval (tRAS) */
 392         unsigned int ext_acttopre = 0;
 393         /* Extended activate to read/write interval (tRCD) */
 394         unsigned int ext_acttorw = 0;
 395         /* Extended refresh recovery time (tRFC) */
 396         unsigned int ext_refrec;
 397         /* Extended MCAS latency from READ cmd */
 398         unsigned int ext_caslat = 0;
 399         /* Extended additive latency */
 400         unsigned int ext_add_lat = 0;
 401         /* Extended last data to precharge interval (tWR) */
 402         unsigned int ext_wrrec = 0;
 403         /* Control Adjust */
 404         unsigned int cntl_adj = 0;
 405
 406         ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
 407         ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
 408         ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
 409         ext_caslat = (2 * cas_latency - 1) >> 4;
 410         ext_add_lat = additive_latency >> 4;
 411 #ifdef CONFIG_SYS_FSL_DDR4
 412         ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
 413 #else
 414         ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
 415         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 416 #endif
 417         ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
 418                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 419
 420         ddr->timing_cfg_3 = (0
 421                 | ((ext_pretoact & 0x1) << 28)
 422                 | ((ext_acttopre & 0x3) << 24)
 423                 | ((ext_acttorw & 0x1) << 22)
 424                 | ((ext_refrec & 0x1F) << 16)
 425                 | ((ext_caslat & 0x3) << 12)
 426                 | ((ext_add_lat & 0x1) << 10)
 427                 | ((ext_wrrec & 0x1) << 8)
 428                 | ((cntl_adj & 0x7) << 0)
 429                 );
 430         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 431 }
 432
 433 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 434 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 435                                const memctl_options_t *popts,
 436                                const common_timing_params_t *common_dimm,
 437                                unsigned int cas_latency)
 438 {
 439         /* Precharge-to-activate interval (tRP) */
 440         unsigned char pretoact_mclk;
 441         /* Activate to precharge interval (tRAS) */
 442         unsigned char acttopre_mclk;
 443         /*  Activate to read/write interval (tRCD) */
 444         unsigned char acttorw_mclk;
 445         /* CASLAT */
 446         unsigned char caslat_ctrl;
 447         /*  Refresh recovery time (tRFC) ; trfc_low */
 448         unsigned char refrec_ctrl;
 449         /* Last data to precharge minimum interval (tWR) */
 450         unsigned char wrrec_mclk;
 451         /* Activate-to-activate interval (tRRD) */
 452         unsigned char acttoact_mclk;
 453         /* Last write data pair to read command issue interval (tWTR) */
 454         unsigned char wrtord_mclk;
 455 #ifdef CONFIG_SYS_FSL_DDR4
 456         /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
 457         static const u8 wrrec_table[] = {
 458                 10, 10, 10, 10, 10,
 459                 10, 10, 10, 10, 10,
 460                 12, 12, 14, 14, 16,
 461                 16, 18, 18, 20, 20,
 462                 24, 24, 24, 24};
 463 #else
 464         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 465         static const u8 wrrec_table[] = {
 466                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 467 #endif
 468
 469         pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
 470         acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
 471         acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
 472
 473         /*
 474          * Translate CAS Latency to a DDR controller field value:
 475          *
 476          *      CAS Lat DDR I   DDR II  Ctrl
 477          *      Clocks  SPD Bit SPD Bit Value
 478          *      ------- ------- ------- -----
 479          *      1.0     0               0001
 480          *      1.5     1               0010
 481          *      2.0     2       2       0011
 482          *      2.5     3               0100
 483          *      3.0     4       3       0101
 484          *      3.5     5               0110
 485          *      4.0             4       0111
 486          *      4.5                     1000
 487          *      5.0             5       1001
 488          */
 489 #if defined(CONFIG_SYS_FSL_DDR1)
 490         caslat_ctrl = (cas_latency + 1) & 0x07;
 491 #elif defined(CONFIG_SYS_FSL_DDR2)
 492         caslat_ctrl = 2 * cas_latency - 1;
 493 #else
 494         /*
 495          * if the CAS latency more than 8 cycle,
 496          * we need set extend bit for it at
 497          * TIMING_CFG_3[EXT_CASLAT]
 498          */
 499         if (fsl_ddr_get_version() <= 0x40400)
 500                 caslat_ctrl = 2 * cas_latency - 1;
 501         else
 502                 caslat_ctrl = (cas_latency - 1) << 1;
 503 #endif
 504
 505 #ifdef CONFIG_SYS_FSL_DDR4
 506         refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
 507         wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
 508         acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4);
 509         wrtord_mclk = max(2, picos_to_mclk(2500));
 510         if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 511                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 512         else
 513                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 514 #else
 515         refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
 516         wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
 517         acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
 518         wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
 519         if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 520                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 521         else
 522                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 523 #endif
 524         if (popts->otf_burst_chop_en)
 525                 wrrec_mclk += 2;
 526
 527         /*
 528          * JEDEC has min requirement for tRRD
 529          */
 530 #if defined(CONFIG_SYS_FSL_DDR3)
 531         if (acttoact_mclk < 4)
 532                 acttoact_mclk = 4;
 533 #endif
 534         /*
 535          * JEDEC has some min requirements for tWTR
 536          */
 537 #if defined(CONFIG_SYS_FSL_DDR2)
 538         if (wrtord_mclk < 2)
 539                 wrtord_mclk = 2;
 540 #elif defined(CONFIG_SYS_FSL_DDR3)
 541         if (wrtord_mclk < 4)
 542                 wrtord_mclk = 4;
 543 #endif
 544         if (popts->otf_burst_chop_en)
 545                 wrtord_mclk += 2;
 546
 547         ddr->timing_cfg_1 = (0
 548                 | ((pretoact_mclk & 0x0F) << 28)
 549                 | ((acttopre_mclk & 0x0F) << 24)
 550                 | ((acttorw_mclk & 0xF) << 20)
 551                 | ((caslat_ctrl & 0xF) << 16)
 552                 | ((refrec_ctrl & 0xF) << 12)
 553                 | ((wrrec_mclk & 0x0F) << 8)
 554                 | ((acttoact_mclk & 0x0F) << 4)
 555                 | ((wrtord_mclk & 0x0F) << 0)
 556                 );
 557         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 558 }
 559
 560 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 561 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 562                                const memctl_options_t *popts,
 563                                const common_timing_params_t *common_dimm,
 564                                unsigned int cas_latency,
 565                                unsigned int additive_latency)
 566 {
 567         /* Additive latency */
 568         unsigned char add_lat_mclk;
 569         /* CAS-to-preamble override */
 570         unsigned short cpo;
 571         /* Write latency */
 572         unsigned char wr_lat;
 573         /*  Read to precharge (tRTP) */
 574         unsigned char rd_to_pre;
 575         /* Write command to write data strobe timing adjustment */
 576         unsigned char wr_data_delay;
 577         /* Minimum CKE pulse width (tCKE) */
 578         unsigned char cke_pls;
 579         /* Window for four activates (tFAW) */
 580         unsigned short four_act;
 581
 582         /* FIXME add check that this must be less than acttorw_mclk */
 583         add_lat_mclk = additive_latency;
 584         cpo = popts->cpo_override;
 585
 586 #if defined(CONFIG_SYS_FSL_DDR1)
 587         /*
 588          * This is a lie.  It should really be 1, but if it is
 589          * set to 1, bits overlap into the old controller's
 590          * otherwise unused ACSM field.  If we leave it 0, then
 591          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 592          */
 593         wr_lat = 0;
 594 #elif defined(CONFIG_SYS_FSL_DDR2)
 595         wr_lat = cas_latency - 1;
 596 #else
 597         wr_lat = compute_cas_write_latency();
 598 #endif
 599
 600 #ifdef CONFIG_SYS_FSL_DDR4
 601         rd_to_pre = picos_to_mclk(7500);
 602 #else
 603         rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
 604 #endif
 605         /*
 606          * JEDEC has some min requirements for tRTP
 607          */
 608 #if defined(CONFIG_SYS_FSL_DDR2)
 609         if (rd_to_pre  < 2)
 610                 rd_to_pre  = 2;
 611 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 612         if (rd_to_pre < 4)
 613                 rd_to_pre = 4;
 614 #endif
 615         if (popts->otf_burst_chop_en)
 616                 rd_to_pre += 2; /* according to UM */
 617
 618         wr_data_delay = popts->write_data_delay;
 619 #ifdef CONFIG_SYS_FSL_DDR4
 620         cpo = 0;
 621         cke_pls = max(3, picos_to_mclk(5000));
 622 #else
 623         cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
 624 #endif
 625
 626         four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
 627
 628         ddr->timing_cfg_2 = (0
 629                 | ((add_lat_mclk & 0xf) << 28)
 630                 | ((cpo & 0x1f) << 23)
 631                 | ((wr_lat & 0xf) << 19)
 632                 | ((wr_lat & 0x10) << 14)
 633                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 634                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 635                 | ((cke_pls & 0x7) << 6)
 636                 | ((four_act & 0x3f) << 0)
 637                 );
 638         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 639 }
 640
 641 /* DDR SDRAM Register Control Word */
 642 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 643                                const memctl_options_t *popts,
 644                                const common_timing_params_t *common_dimm)
 645 {
 646         if (common_dimm->all_dimms_registered &&
 647             !common_dimm->all_dimms_unbuffered) {
 648                 if (popts->rcw_override) {
 649                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 650                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 651                 } else {
 652                         ddr->ddr_sdram_rcw_1 =
 653                                 common_dimm->rcw[0] << 28 | \
 654                                 common_dimm->rcw[1] << 24 | \
 655                                 common_dimm->rcw[2] << 20 | \
 656                                 common_dimm->rcw[3] << 16 | \
 657                                 common_dimm->rcw[4] << 12 | \
 658                                 common_dimm->rcw[5] << 8 | \
 659                                 common_dimm->rcw[6] << 4 | \
 660                                 common_dimm->rcw[7];
 661                         ddr->ddr_sdram_rcw_2 =
 662                                 common_dimm->rcw[8] << 28 | \
 663                                 common_dimm->rcw[9] << 24 | \
 664                                 common_dimm->rcw[10] << 20 | \
 665                                 common_dimm->rcw[11] << 16 | \
 666                                 common_dimm->rcw[12] << 12 | \
 667                                 common_dimm->rcw[13] << 8 | \
 668                                 common_dimm->rcw[14] << 4 | \
 669                                 common_dimm->rcw[15];
 670                 }
 671                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 672                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 673         }
 674 }
 675
 676 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 677 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 678                                const memctl_options_t *popts,
 679                                const common_timing_params_t *common_dimm)
 680 {
 681         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 682         unsigned int sren;              /* Self refresh enable (during sleep) */
 683         unsigned int ecc_en;            /* ECC enable. */
 684         unsigned int rd_en;             /* Registered DIMM enable */
 685         unsigned int sdram_type;        /* Type of SDRAM */
 686         unsigned int dyn_pwr;           /* Dynamic power management mode */
 687         unsigned int dbw;               /* DRAM dta bus width */
 688         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 689         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 690         unsigned int threet_en;         /* Enable 3T timing */
 691         unsigned int twot_en;           /* Enable 2T timing */
 692         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 693         unsigned int x32_en = 0;        /* x32 enable */
 694         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 695         unsigned int hse;               /* Global half strength override */
 696         unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
 697         unsigned int mem_halt = 0;      /* memory controller halt */
 698         unsigned int bi = 0;            /* Bypass initialization */
 699
 700         mem_en = 1;
 701         sren = popts->self_refresh_in_sleep;
 702         if (common_dimm->all_dimms_ecc_capable) {
 703                 /* Allow setting of ECC only if all DIMMs are ECC. */
 704                 ecc_en = popts->ecc_mode;
 705         } else {
 706                 ecc_en = 0;
 707         }
 708
 709         if (common_dimm->all_dimms_registered &&
 710             !common_dimm->all_dimms_unbuffered) {
 711                 rd_en = 1;
 712                 twot_en = 0;
 713         } else {
 714                 rd_en = 0;
 715                 twot_en = popts->twot_en;
 716         }
 717
 718         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 719
 720         dyn_pwr = popts->dynamic_power;
 721         dbw = popts->data_bus_width;
 722         /* 8-beat burst enable DDR-III case
 723          * we must clear it when use the on-the-fly mode,
 724          * must set it when use the 32-bits bus mode.
 725          */
 726         if ((sdram_type == SDRAM_TYPE_DDR3) ||
 727             (sdram_type == SDRAM_TYPE_DDR4)) {
 728                 if (popts->burst_length == DDR_BL8)
 729                         eight_be = 1;
 730                 if (popts->burst_length == DDR_OTF)
 731                         eight_be = 0;
 732                 if (dbw == 0x1)
 733                         eight_be = 1;
 734         }
 735
 736         threet_en = popts->threet_en;
 737         ba_intlv_ctl = popts->ba_intlv_ctl;
 738         hse = popts->half_strength_driver_enable;
 739
 740         /* set when ddr bus width < 64 */
 741         acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
 742
 743         ddr->ddr_sdram_cfg = (0
 744                         | ((mem_en & 0x1) << 31)
 745                         | ((sren & 0x1) << 30)
 746                         | ((ecc_en & 0x1) << 29)
 747                         | ((rd_en & 0x1) << 28)
 748                         | ((sdram_type & 0x7) << 24)
 749                         | ((dyn_pwr & 0x1) << 21)
 750                         | ((dbw & 0x3) << 19)
 751                         | ((eight_be & 0x1) << 18)
 752                         | ((ncap & 0x1) << 17)
 753                         | ((threet_en & 0x1) << 16)
 754                         | ((twot_en & 0x1) << 15)
 755                         | ((ba_intlv_ctl & 0x7F) << 8)
 756                         | ((x32_en & 0x1) << 5)
 757                         | ((pchb8 & 0x1) << 4)
 758                         | ((hse & 0x1) << 3)
 759                         | ((acc_ecc_en & 0x1) << 2)
 760                         | ((mem_halt & 0x1) << 1)
 761                         | ((bi & 0x1) << 0)
 762                         );
 763         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 764 }
 765
 766 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 767 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 768                                const memctl_options_t *popts,
 769                                const unsigned int unq_mrs_en)
 770 {
 771         unsigned int frc_sr = 0;        /* Force self refresh */
 772         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 773         unsigned int odt_cfg = 0;       /* ODT configuration */
 774         unsigned int num_pr;            /* Number of posted refreshes */
 775         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 776         unsigned int x4_en = 0;         /* x4 DRAM enable */
 777         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 778         unsigned int ap_en;             /* Address Parity Enable */
 779         unsigned int d_init;            /* DRAM data initialization */
 780         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 781         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 782         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 783         int i;
 784 #ifndef CONFIG_SYS_FSL_DDR4
 785         unsigned int dll_rst_dis = 1;   /* DLL reset disable */
 786         unsigned int dqs_cfg;           /* DQS configuration */
 787
 788         dqs_cfg = popts->dqs_config;
 789 #endif
 790         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 791                 if (popts->cs_local_opts[i].odt_rd_cfg
 792                         || popts->cs_local_opts[i].odt_wr_cfg) {
 793                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 794                         break;
 795                 }
 796         }
 797
 798         num_pr = 1;     /* Make this configurable */
 799
 800         /*
 801          * 8572 manual says
 802          *     {TIMING_CFG_1[PRETOACT]
 803          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 804          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 805          *      << DDR_SDRAM_INTERVAL[REFINT]
 806          */
 807 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 808         obc_cfg = popts->otf_burst_chop_en;
 809 #else
 810         obc_cfg = 0;
 811 #endif
 812
 813 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 814         slow = get_ddr_freq(0) < 1249000000;
 815 #endif
 816
 817         if (popts->registered_dimm_en) {
 818                 rcw_en = 1;
 819                 ap_en = popts->ap_en;
 820         } else {
 821                 ap_en = 0;
 822         }
 823
 824         x4_en = popts->x4_en ? 1 : 0;
 825
 826 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 827         /* Use the DDR controller to auto initialize memory. */
 828         d_init = popts->ecc_init_using_memctl;
 829         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 830         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 831 #else
 832         /* Memory will be initialized via DMA, or not at all. */
 833         d_init = 0;
 834 #endif
 835
 836 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 837         md_en = popts->mirrored_dimm;
 838 #endif
 839         qd_en = popts->quad_rank_present ? 1 : 0;
 840         ddr->ddr_sdram_cfg_2 = (0
 841                 | ((frc_sr & 0x1) << 31)
 842                 | ((sr_ie & 0x1) << 30)
 843 #ifndef CONFIG_SYS_FSL_DDR4
 844                 | ((dll_rst_dis & 0x1) << 29)
 845                 | ((dqs_cfg & 0x3) << 26)
 846 #endif
 847                 | ((odt_cfg & 0x3) << 21)
 848                 | ((num_pr & 0xf) << 12)
 849                 | ((slow & 1) << 11)
 850                 | (x4_en << 10)
 851                 | (qd_en << 9)
 852                 | (unq_mrs_en << 8)
 853                 | ((obc_cfg & 0x1) << 6)
 854                 | ((ap_en & 0x1) << 5)
 855                 | ((d_init & 0x1) << 4)
 856                 | ((rcw_en & 0x1) << 2)
 857                 | ((md_en & 0x1) << 0)
 858                 );
 859         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 860 }
 861
 862 #ifdef CONFIG_SYS_FSL_DDR4
 863 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 864 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 865                                 const memctl_options_t *popts,
 866                                 const common_timing_params_t *common_dimm,
 867                                 const unsigned int unq_mrs_en)
 868 {
 869         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 870         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 871         int i;
 872         unsigned int wr_crc = 0;        /* Disable */
 873         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 874         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 875         unsigned int cwl = compute_cas_write_latency() - 9;
 876         unsigned int mpr = 0;   /* serial */
 877         unsigned int wc_lat;
 878         const unsigned int mclk_ps = get_memory_clk_period_ps();
 879
 880         if (popts->rtt_override)
 881                 rtt_wr = popts->rtt_wr_override_value;
 882         else
 883                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 884
 885         if (common_dimm->extended_op_srt)
 886                 srt = common_dimm->extended_op_srt;
 887
 888         esdmode2 = (0
 889                 | ((wr_crc & 0x1) << 12)
 890                 | ((rtt_wr & 0x3) << 9)
 891                 | ((srt & 0x3) << 6)
 892                 | ((cwl & 0x7) << 3));
 893
 894         if (mclk_ps >= 1250)
 895                 wc_lat = 0;
 896         else if (mclk_ps >= 833)
 897                 wc_lat = 1;
 898         else
 899                 wc_lat = 2;
 900
 901         esdmode3 = (0
 902                 | ((mpr & 0x3) << 11)
 903                 | ((wc_lat & 0x3) << 9));
 904
 905         ddr->ddr_sdram_mode_2 = (0
 906                                  | ((esdmode2 & 0xFFFF) << 16)
 907                                  | ((esdmode3 & 0xFFFF) << 0)
 908                                  );
 909         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 910
 911         if (unq_mrs_en) {       /* unique mode registers are supported */
 912                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 913                         if (popts->rtt_override)
 914                                 rtt_wr = popts->rtt_wr_override_value;
 915                         else
 916                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 917
 918                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 919                         esdmode2 |= (rtt_wr & 0x3) << 9;
 920                         switch (i) {
 921                         case 1:
 922                                 ddr->ddr_sdram_mode_4 = (0
 923                                         | ((esdmode2 & 0xFFFF) << 16)
 924                                         | ((esdmode3 & 0xFFFF) << 0)
 925                                         );
 926                                 break;
 927                         case 2:
 928                                 ddr->ddr_sdram_mode_6 = (0
 929                                         | ((esdmode2 & 0xFFFF) << 16)
 930                                         | ((esdmode3 & 0xFFFF) << 0)
 931                                         );
 932                                 break;
 933                         case 3:
 934                                 ddr->ddr_sdram_mode_8 = (0
 935                                         | ((esdmode2 & 0xFFFF) << 16)
 936                                         | ((esdmode3 & 0xFFFF) << 0)
 937                                         );
 938                                 break;
 939                         }
 940                 }
 941                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 942                       ddr->ddr_sdram_mode_4);
 943                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 944                       ddr->ddr_sdram_mode_6);
 945                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 946                       ddr->ddr_sdram_mode_8);
 947         }
 948 }
 949 #elif defined(CONFIG_SYS_FSL_DDR3)
 950 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 951 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 952                                 const memctl_options_t *popts,
 953                                 const common_timing_params_t *common_dimm,
 954                                 const unsigned int unq_mrs_en)
 955 {
 956         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 957         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 958         int i;
 959         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 960         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 961         unsigned int asr = 0;   /* auto self-refresh disable */
 962         unsigned int cwl = compute_cas_write_latency() - 5;
 963         unsigned int pasr = 0;  /* partial array self refresh disable */
 964
 965         if (popts->rtt_override)
 966                 rtt_wr = popts->rtt_wr_override_value;
 967         else
 968                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 969
 970         if (common_dimm->extended_op_srt)
 971                 srt = common_dimm->extended_op_srt;
 972
 973         esdmode2 = (0
 974                 | ((rtt_wr & 0x3) << 9)
 975                 | ((srt & 0x1) << 7)
 976                 | ((asr & 0x1) << 6)
 977                 | ((cwl & 0x7) << 3)
 978                 | ((pasr & 0x7) << 0));
 979         ddr->ddr_sdram_mode_2 = (0
 980                                  | ((esdmode2 & 0xFFFF) << 16)
 981                                  | ((esdmode3 & 0xFFFF) << 0)
 982                                  );
 983         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 984
 985         if (unq_mrs_en) {       /* unique mode registers are supported */
 986                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 987                         if (popts->rtt_override)
 988                                 rtt_wr = popts->rtt_wr_override_value;
 989                         else
 990                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 991
 992                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 993                         esdmode2 |= (rtt_wr & 0x3) << 9;
 994                         switch (i) {
 995                         case 1:
 996                                 ddr->ddr_sdram_mode_4 = (0
 997                                         | ((esdmode2 & 0xFFFF) << 16)
 998                                         | ((esdmode3 & 0xFFFF) << 0)
 999                                         );
1000                                 break;
1001                         case 2:
1002                                 ddr->ddr_sdram_mode_6 = (0
1003                                         | ((esdmode2 & 0xFFFF) << 16)
1004                                         | ((esdmode3 & 0xFFFF) << 0)
1005                                         );
1006                                 break;
1007                         case 3:
1008                                 ddr->ddr_sdram_mode_8 = (0
1009                                         | ((esdmode2 & 0xFFFF) << 16)
1010                                         | ((esdmode3 & 0xFFFF) << 0)
1011                                         );
1012                                 break;
1013                         }
1014                 }
1015                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1016                         ddr->ddr_sdram_mode_4);
1017                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1018                         ddr->ddr_sdram_mode_6);
1019                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1020                         ddr->ddr_sdram_mode_8);
1021         }
1022 }
1023
1024 #else /* for DDR2 and DDR1 */
1025 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1026 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
1027                                 const memctl_options_t *popts,
1028                                 const common_timing_params_t *common_dimm,
1029                                 const unsigned int unq_mrs_en)
1030 {
1031         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1032         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1033
1034         ddr->ddr_sdram_mode_2 = (0
1035                                  | ((esdmode2 & 0xFFFF) << 16)
1036                                  | ((esdmode3 & 0xFFFF) << 0)
1037                                  );
1038         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1039 }
1040 #endif
1041
1042 #ifdef CONFIG_SYS_FSL_DDR4
1043 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1044 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1045                                 const memctl_options_t *popts,
1046                                 const common_timing_params_t *common_dimm,
1047                                 const unsigned int unq_mrs_en)
1048 {
1049         int i;
1050         unsigned short esdmode4 = 0;    /* Extended SDRAM mode 4 */
1051         unsigned short esdmode5;        /* Extended SDRAM mode 5 */
1052
1053         esdmode5 = 0x00000400;          /* Data mask enabled */
1054
1055         ddr->ddr_sdram_mode_9 = (0
1056                                  | ((esdmode4 & 0xffff) << 16)
1057                                  | ((esdmode5 & 0xffff) << 0)
1058                                 );
1059         debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1060         if (unq_mrs_en) {       /* unique mode registers are supported */
1061                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1062                         switch (i) {
1063                         case 1:
1064                                 ddr->ddr_sdram_mode_11 = (0
1065                                         | ((esdmode4 & 0xFFFF) << 16)
1066                                         | ((esdmode5 & 0xFFFF) << 0)
1067                                         );
1068                                 break;
1069                         case 2:
1070                                 ddr->ddr_sdram_mode_13 = (0
1071                                         | ((esdmode4 & 0xFFFF) << 16)
1072                                         | ((esdmode5 & 0xFFFF) << 0)
1073                                         );
1074                                 break;
1075                         case 3:
1076                                 ddr->ddr_sdram_mode_15 = (0
1077                                         | ((esdmode4 & 0xFFFF) << 16)
1078                                         | ((esdmode5 & 0xFFFF) << 0)
1079                                         );
1080                                 break;
1081                         }
1082                 }
1083                 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1084                       ddr->ddr_sdram_mode_11);
1085                 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1086                       ddr->ddr_sdram_mode_13);
1087                 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1088                       ddr->ddr_sdram_mode_15);
1089         }
1090 }
1091
1092 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1093 static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
1094                                 const memctl_options_t *popts,
1095                                 const common_timing_params_t *common_dimm,
1096                                 const unsigned int unq_mrs_en)
1097 {
1098         int i;
1099         unsigned short esdmode6 = 0;    /* Extended SDRAM mode 6 */
1100         unsigned short esdmode7 = 0;    /* Extended SDRAM mode 7 */
1101         unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
1102
1103         esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1104
1105         ddr->ddr_sdram_mode_10 = (0
1106                                  | ((esdmode6 & 0xffff) << 16)
1107                                  | ((esdmode7 & 0xffff) << 0)
1108                                 );
1109         debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1110         if (unq_mrs_en) {       /* unique mode registers are supported */
1111                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1112                         switch (i) {
1113                         case 1:
1114                                 ddr->ddr_sdram_mode_12 = (0
1115                                         | ((esdmode6 & 0xFFFF) << 16)
1116                                         | ((esdmode7 & 0xFFFF) << 0)
1117                                         );
1118                                 break;
1119                         case 2:
1120                                 ddr->ddr_sdram_mode_14 = (0
1121                                         | ((esdmode6 & 0xFFFF) << 16)
1122                                         | ((esdmode7 & 0xFFFF) << 0)
1123                                         );
1124                                 break;
1125                         case 3:
1126                                 ddr->ddr_sdram_mode_16 = (0
1127                                         | ((esdmode6 & 0xFFFF) << 16)
1128                                         | ((esdmode7 & 0xFFFF) << 0)
1129                                         );
1130                                 break;
1131                         }
1132                 }
1133                 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1134                       ddr->ddr_sdram_mode_12);
1135                 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1136                       ddr->ddr_sdram_mode_14);
1137                 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1138                       ddr->ddr_sdram_mode_16);
1139         }
1140 }
1141
1142 #endif
1143
1144 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1145 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
1146                                const memctl_options_t *popts,
1147                                const common_timing_params_t *common_dimm)
1148 {
1149         unsigned int refint;    /* Refresh interval */
1150         unsigned int bstopre;   /* Precharge interval */
1151
1152         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
1153
1154         bstopre = popts->bstopre;
1155
1156         /* refint field used 0x3FFF in earlier controllers */
1157         ddr->ddr_sdram_interval = (0
1158                                    | ((refint & 0xFFFF) << 16)
1159                                    | ((bstopre & 0x3FFF) << 0)
1160                                    );
1161         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1162 }
1163
1164 #ifdef CONFIG_SYS_FSL_DDR4
1165 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1166 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1167                                const memctl_options_t *popts,
1168                                const common_timing_params_t *common_dimm,
1169                                unsigned int cas_latency,
1170                                unsigned int additive_latency,
1171                                const unsigned int unq_mrs_en)
1172 {
1173         int i;
1174         unsigned short esdmode;         /* Extended SDRAM mode */
1175         unsigned short sdmode;          /* SDRAM mode */
1176
1177         /* Mode Register - MR1 */
1178         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1179         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1180         unsigned int rtt;
1181         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1182         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1183         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1184         unsigned int dll_en = 1;        /* DLL Enable  1=Enable (Normal),
1185                                                        0=Disable (Test/Debug) */
1186
1187         /* Mode Register - MR0 */
1188         unsigned int wr = 0;    /* Write Recovery */
1189         unsigned int dll_rst;   /* DLL Reset */
1190         unsigned int mode;      /* Normal=0 or Test=1 */
1191         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1192         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1193         unsigned int bt;
1194         unsigned int bl;        /* BL: Burst Length */
1195
1196         unsigned int wr_mclk;
1197         /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1198         static const u8 wr_table[] = {
1199                 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1200         /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1201         static const u8 cas_latency_table[] = {
1202                 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1203                 9, 9, 10, 10, 11, 11};
1204
1205         if (popts->rtt_override)
1206                 rtt = popts->rtt_override_value;
1207         else
1208                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1209
1210         if (additive_latency == (cas_latency - 1))
1211                 al = 1;
1212         if (additive_latency == (cas_latency - 2))
1213                 al = 2;
1214
1215         if (popts->quad_rank_present)
1216                 dic = 1;        /* output driver impedance 240/7 ohm */
1217
1218         /*
1219          * The esdmode value will also be used for writing
1220          * MR1 during write leveling for DDR3, although the
1221          * bits specifically related to the write leveling
1222          * scheme will be handled automatically by the DDR
1223          * controller. so we set the wrlvl_en = 0 here.
1224          */
1225         esdmode = (0
1226                 | ((qoff & 0x1) << 12)
1227                 | ((tdqs_en & 0x1) << 11)
1228                 | ((rtt & 0x7) << 8)
1229                 | ((wrlvl_en & 0x1) << 7)
1230                 | ((al & 0x3) << 3)
1231                 | ((dic & 0x3) << 1)   /* DIC field is split */
1232                 | ((dll_en & 0x1) << 0)
1233                 );
1234
1235         /*
1236          * DLL control for precharge PD
1237          * 0=slow exit DLL off (tXPDLL)
1238          * 1=fast exit DLL on (tXP)
1239          */
1240
1241         wr_mclk = picos_to_mclk(common_dimm->twr_ps);
1242         if (wr_mclk <= 24) {
1243                 wr = wr_table[wr_mclk - 10];
1244         } else {
1245                 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1246                        wr_mclk);
1247         }
1248
1249         dll_rst = 0;    /* dll no reset */
1250         mode = 0;       /* normal mode */
1251
1252         /* look up table to get the cas latency bits */
1253         if (cas_latency >= 9 && cas_latency <= 24)
1254                 caslat = cas_latency_table[cas_latency - 9];
1255         else
1256                 printf("Error: unsupported cas latency for mode register\n");
1257
1258         bt = 0; /* Nibble sequential */
1259
1260         switch (popts->burst_length) {
1261         case DDR_BL8:
1262                 bl = 0;
1263                 break;
1264         case DDR_OTF:
1265                 bl = 1;
1266                 break;
1267         case DDR_BC4:
1268                 bl = 2;
1269                 break;
1270         default:
1271                 printf("Error: invalid burst length of %u specified. ",
1272                        popts->burst_length);
1273                 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1274                 bl = 1;
1275                 break;
1276         }
1277
1278         sdmode = (0
1279                   | ((wr & 0x7) << 9)
1280                   | ((dll_rst & 0x1) << 8)
1281                   | ((mode & 0x1) << 7)
1282                   | (((caslat >> 1) & 0x7) << 4)
1283                   | ((bt & 0x1) << 3)
1284                   | ((caslat & 1) << 2)
1285                   | ((bl & 0x3) << 0)
1286                   );
1287
1288         ddr->ddr_sdram_mode = (0
1289                                | ((esdmode & 0xFFFF) << 16)
1290                                | ((sdmode & 0xFFFF) << 0)
1291                                );
1292
1293         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1294
1295         if (unq_mrs_en) {       /* unique mode registers are supported */
1296                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1297                         if (popts->rtt_override)
1298                                 rtt = popts->rtt_override_value;
1299                         else
1300                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1301
1302                         esdmode &= 0xF8FF;      /* clear bit 10,9,8 for rtt */
1303                         esdmode |= (rtt & 0x7) << 8;
1304                         switch (i) {
1305                         case 1:
1306                                 ddr->ddr_sdram_mode_3 = (0
1307                                        | ((esdmode & 0xFFFF) << 16)
1308                                        | ((sdmode & 0xFFFF) << 0)
1309                                        );
1310                                 break;
1311                         case 2:
1312                                 ddr->ddr_sdram_mode_5 = (0
1313                                        | ((esdmode & 0xFFFF) << 16)
1314                                        | ((sdmode & 0xFFFF) << 0)
1315                                        );
1316                                 break;
1317                         case 3:
1318                                 ddr->ddr_sdram_mode_7 = (0
1319                                        | ((esdmode & 0xFFFF) << 16)
1320                                        | ((sdmode & 0xFFFF) << 0)
1321                                        );
1322                                 break;
1323                         }
1324                 }
1325                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1326                       ddr->ddr_sdram_mode_3);
1327                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1328                       ddr->ddr_sdram_mode_5);
1329                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1330                       ddr->ddr_sdram_mode_5);
1331         }
1332 }
1333
1334 #elif defined(CONFIG_SYS_FSL_DDR3)
1335 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1336 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1337                                const memctl_options_t *popts,
1338                                const common_timing_params_t *common_dimm,
1339                                unsigned int cas_latency,
1340                                unsigned int additive_latency,
1341                                const unsigned int unq_mrs_en)
1342 {
1343         int i;
1344         unsigned short esdmode;         /* Extended SDRAM mode */
1345         unsigned short sdmode;          /* SDRAM mode */
1346
1347         /* Mode Register - MR1 */
1348         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1349         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1350         unsigned int rtt;
1351         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1352         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1353         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1354         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1355                                                        1=Disable (Test/Debug) */
1356
1357         /* Mode Register - MR0 */
1358         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
1359         unsigned int wr = 0;    /* Write Recovery */
1360         unsigned int dll_rst;   /* DLL Reset */
1361         unsigned int mode;      /* Normal=0 or Test=1 */
1362         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1363         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1364         unsigned int bt;
1365         unsigned int bl;        /* BL: Burst Length */
1366
1367         unsigned int wr_mclk;
1368         /*
1369          * DDR_SDRAM_MODE doesn't support 9,11,13,15
1370          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1371          * for this table
1372          */
1373         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1374
1375         if (popts->rtt_override)
1376                 rtt = popts->rtt_override_value;
1377         else
1378                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1379
1380         if (additive_latency == (cas_latency - 1))
1381                 al = 1;
1382         if (additive_latency == (cas_latency - 2))
1383                 al = 2;
1384
1385         if (popts->quad_rank_present)
1386                 dic = 1;        /* output driver impedance 240/7 ohm */
1387
1388         /*
1389          * The esdmode value will also be used for writing
1390          * MR1 during write leveling for DDR3, although the
1391          * bits specifically related to the write leveling
1392          * scheme will be handled automatically by the DDR
1393          * controller. so we set the wrlvl_en = 0 here.
1394          */
1395         esdmode = (0
1396                 | ((qoff & 0x1) << 12)
1397                 | ((tdqs_en & 0x1) << 11)
1398                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1399                 | ((wrlvl_en & 0x1) << 7)
1400                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1401                 | ((dic & 0x2) << 4)   /* DIC field is split */
1402                 | ((al & 0x3) << 3)
1403                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1404                 | ((dic & 0x1) << 1)   /* DIC field is split */
1405                 | ((dll_en & 0x1) << 0)
1406                 );
1407
1408         /*
1409          * DLL control for precharge PD
1410          * 0=slow exit DLL off (tXPDLL)
1411          * 1=fast exit DLL on (tXP)
1412          */
1413         dll_on = 1;
1414
1415         wr_mclk = picos_to_mclk(common_dimm->twr_ps);
1416         if (wr_mclk <= 16) {
1417                 wr = wr_table[wr_mclk - 5];
1418         } else {
1419                 printf("Error: unsupported write recovery for mode register "
1420                        "wr_mclk = %d\n", wr_mclk);
1421         }
1422
1423         dll_rst = 0;    /* dll no reset */
1424         mode = 0;       /* normal mode */
1425
1426         /* look up table to get the cas latency bits */
1427         if (cas_latency >= 5 && cas_latency <= 16) {
1428                 unsigned char cas_latency_table[] = {
1429                         0x2,    /* 5 clocks */
1430                         0x4,    /* 6 clocks */
1431                         0x6,    /* 7 clocks */
1432                         0x8,    /* 8 clocks */
1433                         0xa,    /* 9 clocks */
1434                         0xc,    /* 10 clocks */
1435                         0xe,    /* 11 clocks */
1436                         0x1,    /* 12 clocks */
1437                         0x3,    /* 13 clocks */
1438                         0x5,    /* 14 clocks */
1439                         0x7,    /* 15 clocks */
1440                         0x9,    /* 16 clocks */
1441                 };
1442                 caslat = cas_latency_table[cas_latency - 5];
1443         } else {
1444                 printf("Error: unsupported cas latency for mode register\n");
1445         }
1446
1447         bt = 0; /* Nibble sequential */
1448
1449         switch (popts->burst_length) {
1450         case DDR_BL8:
1451                 bl = 0;
1452                 break;
1453         case DDR_OTF:
1454                 bl = 1;
1455                 break;
1456         case DDR_BC4:
1457                 bl = 2;
1458                 break;
1459         default:
1460                 printf("Error: invalid burst length of %u specified. "
1461                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1462                         popts->burst_length);
1463                 bl = 1;
1464                 break;
1465         }
1466
1467         sdmode = (0
1468                   | ((dll_on & 0x1) << 12)
1469                   | ((wr & 0x7) << 9)
1470                   | ((dll_rst & 0x1) << 8)
1471                   | ((mode & 0x1) << 7)
1472                   | (((caslat >> 1) & 0x7) << 4)
1473                   | ((bt & 0x1) << 3)
1474                   | ((caslat & 1) << 2)
1475                   | ((bl & 0x3) << 0)
1476                   );
1477
1478         ddr->ddr_sdram_mode = (0
1479                                | ((esdmode & 0xFFFF) << 16)
1480                                | ((sdmode & 0xFFFF) << 0)
1481                                );
1482
1483         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1484
1485         if (unq_mrs_en) {       /* unique mode registers are supported */
1486                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1487                         if (popts->rtt_override)
1488                                 rtt = popts->rtt_override_value;
1489                         else
1490                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1491
1492                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1493                         esdmode |= (0
1494                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1495                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1496                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1497                                 );
1498                         switch (i) {
1499                         case 1:
1500                                 ddr->ddr_sdram_mode_3 = (0
1501                                        | ((esdmode & 0xFFFF) << 16)
1502                                        | ((sdmode & 0xFFFF) << 0)
1503                                        );
1504                                 break;
1505                         case 2:
1506                                 ddr->ddr_sdram_mode_5 = (0
1507                                        | ((esdmode & 0xFFFF) << 16)
1508                                        | ((sdmode & 0xFFFF) << 0)
1509                                        );
1510                                 break;
1511                         case 3:
1512                                 ddr->ddr_sdram_mode_7 = (0
1513                                        | ((esdmode & 0xFFFF) << 16)
1514                                        | ((sdmode & 0xFFFF) << 0)
1515                                        );
1516                                 break;
1517                         }
1518                 }
1519                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1520                         ddr->ddr_sdram_mode_3);
1521                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1522                         ddr->ddr_sdram_mode_5);
1523                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1524                         ddr->ddr_sdram_mode_5);
1525         }
1526 }
1527
1528 #else /* !CONFIG_SYS_FSL_DDR3 */
1529
1530 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1531 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1532                                const memctl_options_t *popts,
1533                                const common_timing_params_t *common_dimm,
1534                                unsigned int cas_latency,
1535                                unsigned int additive_latency,
1536                                const unsigned int unq_mrs_en)
1537 {
1538         unsigned short esdmode;         /* Extended SDRAM mode */
1539         unsigned short sdmode;          /* SDRAM mode */
1540
1541         /*
1542          * FIXME: This ought to be pre-calculated in a
1543          * technology-specific routine,
1544          * e.g. compute_DDR2_mode_register(), and then the
1545          * sdmode and esdmode passed in as part of common_dimm.
1546          */
1547
1548         /* Extended Mode Register */
1549         unsigned int mrs = 0;           /* Mode Register Set */
1550         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1551         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1552         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1553         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1554                                            0x7=OCD default state */
1555         unsigned int rtt;
1556         unsigned int al;                /* Posted CAS# additive latency (AL) */
1557         unsigned int ods = 0;           /* Output Drive Strength:
1558                                                 0 = Full strength (18ohm)
1559                                                 1 = Reduced strength (4ohm) */
1560         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1561                                                        1=Disable (Test/Debug) */
1562
1563         /* Mode Register (MR) */
1564         unsigned int mr;        /* Mode Register Definition */
1565         unsigned int pd;        /* Power-Down Mode */
1566         unsigned int wr;        /* Write Recovery */
1567         unsigned int dll_res;   /* DLL Reset */
1568         unsigned int mode;      /* Normal=0 or Test=1 */
1569         unsigned int caslat = 0;/* CAS# latency */
1570         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1571         unsigned int bt;
1572         unsigned int bl;        /* BL: Burst Length */
1573
1574         dqs_en = !popts->dqs_config;
1575         rtt = fsl_ddr_get_rtt();
1576
1577         al = additive_latency;
1578
1579         esdmode = (0
1580                 | ((mrs & 0x3) << 14)
1581                 | ((outputs & 0x1) << 12)
1582                 | ((rdqs_en & 0x1) << 11)
1583                 | ((dqs_en & 0x1) << 10)
1584                 | ((ocd & 0x7) << 7)
1585                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1586                 | ((al & 0x7) << 3)
1587                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1588                 | ((ods & 0x1) << 1)
1589                 | ((dll_en & 0x1) << 0)
1590                 );
1591
1592         mr = 0;          /* FIXME: CHECKME */
1593
1594         /*
1595          * 0 = Fast Exit (Normal)
1596          * 1 = Slow Exit (Low Power)
1597          */
1598         pd = 0;
1599
1600 #if defined(CONFIG_SYS_FSL_DDR1)
1601         wr = 0;       /* Historical */
1602 #elif defined(CONFIG_SYS_FSL_DDR2)
1603         wr = picos_to_mclk(common_dimm->twr_ps);
1604 #endif
1605         dll_res = 0;
1606         mode = 0;
1607
1608 #if defined(CONFIG_SYS_FSL_DDR1)
1609         if (1 <= cas_latency && cas_latency <= 4) {
1610                 unsigned char mode_caslat_table[4] = {
1611                         0x5,    /* 1.5 clocks */
1612                         0x2,    /* 2.0 clocks */
1613                         0x6,    /* 2.5 clocks */
1614                         0x3     /* 3.0 clocks */
1615                 };
1616                 caslat = mode_caslat_table[cas_latency - 1];
1617         } else {
1618                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1619         }
1620 #elif defined(CONFIG_SYS_FSL_DDR2)
1621         caslat = cas_latency;
1622 #endif
1623         bt = 0;
1624
1625         switch (popts->burst_length) {
1626         case DDR_BL4:
1627                 bl = 2;
1628                 break;
1629         case DDR_BL8:
1630                 bl = 3;
1631                 break;
1632         default:
1633                 printf("Error: invalid burst length of %u specified. "
1634                         " Defaulting to 4 beats.\n",
1635                         popts->burst_length);
1636                 bl = 2;
1637                 break;
1638         }
1639
1640         sdmode = (0
1641                   | ((mr & 0x3) << 14)
1642                   | ((pd & 0x1) << 12)
1643                   | ((wr & 0x7) << 9)
1644                   | ((dll_res & 0x1) << 8)
1645                   | ((mode & 0x1) << 7)
1646                   | ((caslat & 0x7) << 4)
1647                   | ((bt & 0x1) << 3)
1648                   | ((bl & 0x7) << 0)
1649                   );
1650
1651         ddr->ddr_sdram_mode = (0
1652                                | ((esdmode & 0xFFFF) << 16)
1653                                | ((sdmode & 0xFFFF) << 0)
1654                                );
1655         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1656 }
1657 #endif
1658
1659 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1660 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1661 {
1662         unsigned int init_value;        /* Initialization value */
1663
1664 #ifdef CONFIG_MEM_INIT_VALUE
1665         init_value = CONFIG_MEM_INIT_VALUE;
1666 #else
1667         init_value = 0xDEADBEEF;
1668 #endif
1669         ddr->ddr_data_init = init_value;
1670 }
1671
1672 /*
1673  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1674  * The old controller on the 8540/60 doesn't have this register.
1675  * Hope it's OK to set it (to 0) anyway.
1676  */
1677 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1678                                          const memctl_options_t *popts)
1679 {
1680         unsigned int clk_adjust;        /* Clock adjust */
1681
1682         clk_adjust = popts->clk_adjust;
1683         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1684         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1685 }
1686
1687 /* DDR Initialization Address (DDR_INIT_ADDR) */
1688 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1689 {
1690         unsigned int init_addr = 0;     /* Initialization address */
1691
1692         ddr->ddr_init_addr = init_addr;
1693 }
1694
1695 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1696 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1697 {
1698         unsigned int uia = 0;   /* Use initialization address */
1699         unsigned int init_ext_addr = 0; /* Initialization address */
1700
1701         ddr->ddr_init_ext_addr = (0
1702                                   | ((uia & 0x1) << 31)
1703                                   | (init_ext_addr & 0xF)
1704                                   );
1705 }
1706
1707 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1708 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1709                                 const memctl_options_t *popts)
1710 {
1711         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1712         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1713         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1714         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1715         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1716
1717 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1718         if (popts->burst_length == DDR_BL8) {
1719                 /* We set BL/2 for fixed BL8 */
1720                 rrt = 0;        /* BL/2 clocks */
1721                 wwt = 0;        /* BL/2 clocks */
1722         } else {
1723                 /* We need to set BL/2 + 2 to BC4 and OTF */
1724                 rrt = 2;        /* BL/2 + 2 clocks */
1725                 wwt = 2;        /* BL/2 + 2 clocks */
1726         }
1727 #endif
1728
1729 #ifdef CONFIG_SYS_FSL_DDR4
1730         dll_lock = 2;   /* tDLLK = 1024 clocks */
1731 #elif defined(CONFIG_SYS_FSL_DDR3)
1732         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1733 #endif
1734         ddr->timing_cfg_4 = (0
1735                              | ((rwt & 0xf) << 28)
1736                              | ((wrt & 0xf) << 24)
1737                              | ((rrt & 0xf) << 20)
1738                              | ((wwt & 0xf) << 16)
1739                              | (dll_lock & 0x3)
1740                              );
1741         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1742 }
1743
1744 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1745 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1746 {
1747         unsigned int rodt_on = 0;       /* Read to ODT on */
1748         unsigned int rodt_off = 0;      /* Read to ODT off */
1749         unsigned int wodt_on = 0;       /* Write to ODT on */
1750         unsigned int wodt_off = 0;      /* Write to ODT off */
1751
1752 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1753         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1754                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1755         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1756         if (cas_latency >= wr_lat)
1757                 rodt_on = cas_latency - wr_lat + 1;
1758         rodt_off = 4;   /*  4 clocks */
1759         wodt_on = 1;    /*  1 clocks */
1760         wodt_off = 4;   /*  4 clocks */
1761 #endif
1762
1763         ddr->timing_cfg_5 = (0
1764                              | ((rodt_on & 0x1f) << 24)
1765                              | ((rodt_off & 0x7) << 20)
1766                              | ((wodt_on & 0x1f) << 12)
1767                              | ((wodt_off & 0x7) << 8)
1768                              );
1769         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1770 }
1771
1772 #ifdef CONFIG_SYS_FSL_DDR4
1773 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1774 {
1775         unsigned int hs_caslat = 0;
1776         unsigned int hs_wrlat = 0;
1777         unsigned int hs_wrrec = 0;
1778         unsigned int hs_clkadj = 0;
1779         unsigned int hs_wrlvl_start = 0;
1780
1781         ddr->timing_cfg_6 = (0
1782                              | ((hs_caslat & 0x1f) << 24)
1783                              | ((hs_wrlat & 0x1f) << 19)
1784                              | ((hs_wrrec & 0x1f) << 12)
1785                              | ((hs_clkadj & 0x1f) << 6)
1786                              | ((hs_wrlvl_start & 0x1f) << 0)
1787                             );
1788         debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1789 }
1790
1791 static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
1792                         const common_timing_params_t *common_dimm)
1793 {
1794         unsigned int txpr, tcksre, tcksrx;
1795         unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1796
1797         txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000));
1798         tcksre = max(5, picos_to_mclk(10000));
1799         tcksrx = max(5, picos_to_mclk(10000));
1800         par_lat = 0;
1801         cs_to_cmd = 0;
1802
1803         if (txpr <= 200)
1804                 cke_rst = 0;
1805         else if (txpr <= 256)
1806                 cke_rst = 1;
1807         else if (txpr <= 512)
1808                 cke_rst = 2;
1809         else
1810                 cke_rst = 3;
1811
1812         if (tcksre <= 19)
1813                 cksre = tcksre - 5;
1814         else
1815                 cksre = 15;
1816
1817         if (tcksrx <= 19)
1818                 cksrx = tcksrx - 5;
1819         else
1820                 cksrx = 15;
1821
1822         ddr->timing_cfg_7 = (0
1823                              | ((cke_rst & 0x3) << 28)
1824                              | ((cksre & 0xf) << 24)
1825                              | ((cksrx & 0xf) << 20)
1826                              | ((par_lat & 0xf) << 16)
1827                              | ((cs_to_cmd & 0xf) << 4)
1828                             );
1829         debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1830 }
1831
1832 static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
1833                              const memctl_options_t *popts,
1834                              const common_timing_params_t *common_dimm,
1835                              unsigned int cas_latency)
1836 {
1837         unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1838         unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
1839         unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
1840         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1841                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1842
1843         rwt_bg = cas_latency + 2 + 4 - wr_lat;
1844         if (rwt_bg < tccdl)
1845                 rwt_bg = tccdl - rwt_bg;
1846         else
1847                 rwt_bg = 0;
1848
1849         wrt_bg = wr_lat + 4 + 1 - cas_latency;
1850         if (wrt_bg < tccdl)
1851                 wrt_bg = tccdl - wrt_bg;
1852         else
1853                 wrt_bg = 0;
1854
1855         if (popts->burst_length == DDR_BL8) {
1856                 rrt_bg = tccdl - 4;
1857                 wwt_bg = tccdl - 4;
1858         } else {
1859                 rrt_bg = tccdl - 2;
1860                 wwt_bg = tccdl - 4;
1861         }
1862
1863         acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
1864         wrtord_bg = max(4, picos_to_mclk(7500));
1865         if (popts->otf_burst_chop_en)
1866                 wrtord_bg += 2;
1867
1868         pre_all_rec = 0;
1869
1870         ddr->timing_cfg_8 = (0
1871                              | ((rwt_bg & 0xf) << 28)
1872                              | ((wrt_bg & 0xf) << 24)
1873                              | ((rrt_bg & 0xf) << 20)
1874                              | ((wwt_bg & 0xf) << 16)
1875                              | ((acttoact_bg & 0xf) << 12)
1876                              | ((wrtord_bg & 0xf) << 8)
1877                              | ((pre_all_rec & 0x1f) << 0)
1878                             );
1879
1880         debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
1881 }
1882
1883 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
1884 {
1885         ddr->timing_cfg_9 = 0;
1886         debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
1887 }
1888
1889 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
1890                                const dimm_params_t *dimm_params)
1891 {
1892         ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
1893                         ((dimm_params->dq_mapping[1] & 0x3F) << 20) |
1894                         ((dimm_params->dq_mapping[2] & 0x3F) << 14) |
1895                         ((dimm_params->dq_mapping[3] & 0x3F) << 8) |
1896                         ((dimm_params->dq_mapping[4] & 0x3F) << 2);
1897
1898         ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
1899                         ((dimm_params->dq_mapping[6] & 0x3F) << 20) |
1900                         ((dimm_params->dq_mapping[7] & 0x3F) << 14) |
1901                         ((dimm_params->dq_mapping[10] & 0x3F) << 8) |
1902                         ((dimm_params->dq_mapping[11] & 0x3F) << 2);
1903
1904         ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
1905                         ((dimm_params->dq_mapping[13] & 0x3F) << 20) |
1906                         ((dimm_params->dq_mapping[14] & 0x3F) << 14) |
1907                         ((dimm_params->dq_mapping[15] & 0x3F) << 8) |
1908                         ((dimm_params->dq_mapping[16] & 0x3F) << 2);
1909
1910         ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
1911                         ((dimm_params->dq_mapping[8] & 0x3F) << 20) |
1912                         ((dimm_params->dq_mapping[9] & 0x3F) << 14) |
1913                         dimm_params->dq_mapping_ors;
1914
1915         debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
1916         debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
1917         debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
1918         debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
1919 }
1920 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
1921                                const memctl_options_t *popts)
1922 {
1923         int rd_pre;
1924
1925         rd_pre = popts->quad_rank_present ? 1 : 0;
1926
1927         ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
1928
1929         debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
1930 }
1931 #endif  /* CONFIG_SYS_FSL_DDR4 */
1932
1933 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1934 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1935 {
1936         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1937         /* Normal Operation Full Calibration Time (tZQoper) */
1938         unsigned int zqoper = 0;
1939         /* Normal Operation Short Calibration Time (tZQCS) */
1940         unsigned int zqcs = 0;
1941 #ifdef CONFIG_SYS_FSL_DDR4
1942         unsigned int zqcs_init;
1943 #endif
1944
1945         if (zq_en) {
1946 #ifdef CONFIG_SYS_FSL_DDR4
1947                 zqinit = 10;    /* 1024 clocks */
1948                 zqoper = 9;     /* 512 clocks */
1949                 zqcs = 7;       /* 128 clocks */
1950                 zqcs_init = 5;  /* 1024 refresh sequences */
1951 #else
1952                 zqinit = 9;     /* 512 clocks */
1953                 zqoper = 8;     /* 256 clocks */
1954                 zqcs = 6;       /* 64 clocks */
1955 #endif
1956         }
1957
1958         ddr->ddr_zq_cntl = (0
1959                             | ((zq_en & 0x1) << 31)
1960                             | ((zqinit & 0xF) << 24)
1961                             | ((zqoper & 0xF) << 16)
1962                             | ((zqcs & 0xF) << 8)
1963 #ifdef CONFIG_SYS_FSL_DDR4
1964                             | ((zqcs_init & 0xF) << 0)
1965 #endif
1966                             );
1967         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1968 }
1969
1970 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1971 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1972                                 const memctl_options_t *popts)
1973 {
1974         /*
1975          * First DQS pulse rising edge after margining mode
1976          * is programmed (tWL_MRD)
1977          */
1978         unsigned int wrlvl_mrd = 0;
1979         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1980         unsigned int wrlvl_odten = 0;
1981         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1982         unsigned int wrlvl_dqsen = 0;
1983         /* WRLVL_SMPL: Write leveling sample time */
1984         unsigned int wrlvl_smpl = 0;
1985         /* WRLVL_WLR: Write leveling repeition time */
1986         unsigned int wrlvl_wlr = 0;
1987         /* WRLVL_START: Write leveling start time */
1988         unsigned int wrlvl_start = 0;
1989
1990         /* suggest enable write leveling for DDR3 due to fly-by topology */
1991         if (wrlvl_en) {
1992                 /* tWL_MRD min = 40 nCK, we set it 64 */
1993                 wrlvl_mrd = 0x6;
1994                 /* tWL_ODTEN 128 */
1995                 wrlvl_odten = 0x7;
1996                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1997                 wrlvl_dqsen = 0x5;
1998                 /*
1999                  * Write leveling sample time at least need 6 clocks
2000                  * higher than tWLO to allow enough time for progagation
2001                  * delay and sampling the prime data bits.
2002                  */
2003                 wrlvl_smpl = 0xf;
2004                 /*
2005                  * Write leveling repetition time
2006                  * at least tWLO + 6 clocks clocks
2007                  * we set it 64
2008                  */
2009                 wrlvl_wlr = 0x6;
2010                 /*
2011                  * Write leveling start time
2012                  * The value use for the DQS_ADJUST for the first sample
2013                  * when write leveling is enabled. It probably needs to be
2014                  * overriden per platform.
2015                  */
2016                 wrlvl_start = 0x8;
2017                 /*
2018                  * Override the write leveling sample and start time
2019                  * according to specific board
2020                  */
2021                 if (popts->wrlvl_override) {
2022                         wrlvl_smpl = popts->wrlvl_sample;
2023                         wrlvl_start = popts->wrlvl_start;
2024                 }
2025         }
2026
2027         ddr->ddr_wrlvl_cntl = (0
2028                                | ((wrlvl_en & 0x1) << 31)
2029                                | ((wrlvl_mrd & 0x7) << 24)
2030                                | ((wrlvl_odten & 0x7) << 20)
2031                                | ((wrlvl_dqsen & 0x7) << 16)
2032                                | ((wrlvl_smpl & 0xf) << 12)
2033                                | ((wrlvl_wlr & 0x7) << 8)
2034                                | ((wrlvl_start & 0x1F) << 0)
2035                                );
2036         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2037         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2038         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2039         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2040         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2041
2042 }
2043
2044 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2045 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2046 {
2047         /* Self Refresh Idle Threshold */
2048         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2049 }
2050
2051 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2052 {
2053         if (popts->addr_hash) {
2054                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
2055                 puts("Address hashing enabled.\n");
2056         }
2057 }
2058
2059 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2060 {
2061         ddr->ddr_cdr1 = popts->ddr_cdr1;
2062         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2063 }
2064
2065 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2066 {
2067         ddr->ddr_cdr2 = popts->ddr_cdr2;
2068         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2069 }
2070
2071 unsigned int
2072 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2073 {
2074         unsigned int res = 0;
2075
2076         /*
2077          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2078          * not set at the same time.
2079          */
2080         if (ddr->ddr_sdram_cfg & 0x10000000
2081             && ddr->ddr_sdram_cfg & 0x00008000) {
2082                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2083                                 " should not be set at the same time.\n");
2084                 res++;
2085         }
2086
2087         return res;
2088 }
2089
2090 unsigned int
2091 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
2092                                fsl_ddr_cfg_regs_t *ddr,
2093                                const common_timing_params_t *common_dimm,
2094                                const dimm_params_t *dimm_params,
2095                                unsigned int dbw_cap_adj,
2096                                unsigned int size_only)
2097 {
2098         unsigned int i;
2099         unsigned int cas_latency;
2100         unsigned int additive_latency;
2101         unsigned int sr_it;
2102         unsigned int zq_en;
2103         unsigned int wrlvl_en;
2104         unsigned int ip_rev = 0;
2105         unsigned int unq_mrs_en = 0;
2106         int cs_en = 1;
2107
2108         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2109
2110         if (common_dimm == NULL) {
2111                 printf("Error: subset DIMM params struct null pointer\n");
2112                 return 1;
2113         }
2114
2115         /*
2116          * Process overrides first.
2117          *
2118          * FIXME: somehow add dereated caslat to this
2119          */
2120         cas_latency = (popts->cas_latency_override)
2121                 ? popts->cas_latency_override_value
2122                 : common_dimm->lowest_common_spd_caslat;
2123
2124         additive_latency = (popts->additive_latency_override)
2125                 ? popts->additive_latency_override_value
2126                 : common_dimm->additive_latency;
2127
2128         sr_it = (popts->auto_self_refresh_en)
2129                 ? popts->sr_it
2130                 : 0;
2131         /* ZQ calibration */
2132         zq_en = (popts->zq_en) ? 1 : 0;
2133         /* write leveling */
2134         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2135
2136         /* Chip Select Memory Bounds (CSn_BNDS) */
2137         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2138                 unsigned long long ea, sa;
2139                 unsigned int cs_per_dimm
2140                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2141                 unsigned int dimm_number
2142                         = i / cs_per_dimm;
2143                 unsigned long long rank_density
2144                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2145
2146                 if (dimm_params[dimm_number].n_ranks == 0) {
2147                         debug("Skipping setup of CS%u "
2148                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2149                         continue;
2150                 }
2151                 if (popts->memctl_interleaving) {
2152                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2153                         case FSL_DDR_CS0_CS1_CS2_CS3:
2154                                 break;
2155                         case FSL_DDR_CS0_CS1:
2156                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2157                                 if (i > 1)
2158                                         cs_en = 0;
2159                                 break;
2160                         case FSL_DDR_CS2_CS3:
2161                         default:
2162                                 if (i > 0)
2163                                         cs_en = 0;
2164                                 break;
2165                         }
2166                         sa = common_dimm->base_address;
2167                         ea = sa + common_dimm->total_mem - 1;
2168                 } else if (!popts->memctl_interleaving) {
2169                         /*
2170                          * If memory interleaving between controllers is NOT
2171                          * enabled, the starting address for each memory
2172                          * controller is distinct.  However, because rank
2173                          * interleaving is enabled, the starting and ending
2174                          * addresses of the total memory on that memory
2175                          * controller needs to be programmed into its
2176                          * respective CS0_BNDS.
2177                          */
2178                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2179                         case FSL_DDR_CS0_CS1_CS2_CS3:
2180                                 sa = common_dimm->base_address;
2181                                 ea = sa + common_dimm->total_mem - 1;
2182                                 break;
2183                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2184                                 if ((i >= 2) && (dimm_number == 0)) {
2185                                         sa = dimm_params[dimm_number].base_address +
2186                                               2 * rank_density;
2187                                         ea = sa + 2 * rank_density - 1;
2188                                 } else {
2189                                         sa = dimm_params[dimm_number].base_address;
2190                                         ea = sa + 2 * rank_density - 1;
2191                                 }
2192                                 break;
2193                         case FSL_DDR_CS0_CS1:
2194                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2195                                         sa = dimm_params[dimm_number].base_address;
2196                                         ea = sa + rank_density - 1;
2197                                         if (i != 1)
2198                                                 sa += (i % cs_per_dimm) * rank_density;
2199                                         ea += (i % cs_per_dimm) * rank_density;
2200                                 } else {
2201                                         sa = 0;
2202                                         ea = 0;
2203                                 }
2204                                 if (i == 0)
2205                                         ea += rank_density;
2206                                 break;
2207                         case FSL_DDR_CS2_CS3:
2208                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2209                                         sa = dimm_params[dimm_number].base_address;
2210                                         ea = sa + rank_density - 1;
2211                                         if (i != 3)
2212                                                 sa += (i % cs_per_dimm) * rank_density;
2213                                         ea += (i % cs_per_dimm) * rank_density;
2214                                 } else {
2215                                         sa = 0;
2216                                         ea = 0;
2217                                 }
2218                                 if (i == 2)
2219                                         ea += (rank_density >> dbw_cap_adj);
2220                                 break;
2221                         default:  /* No bank(chip-select) interleaving */
2222                                 sa = dimm_params[dimm_number].base_address;
2223                                 ea = sa + rank_density - 1;
2224                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2225                                         sa += (i % cs_per_dimm) * rank_density;
2226                                         ea += (i % cs_per_dimm) * rank_density;
2227                                 } else {
2228                                         sa = 0;
2229                                         ea = 0;
2230                                 }
2231                                 break;
2232                         }
2233                 }
2234
2235                 sa >>= 24;
2236                 ea >>= 24;
2237
2238                 if (cs_en) {
2239                         ddr->cs[i].bnds = (0
2240                                 | ((sa & 0xffff) << 16) /* starting address */
2241                                 | ((ea & 0xffff) << 0)  /* ending address */
2242                                 );
2243                 } else {
2244                         /* setting bnds to 0xffffffff for inactive CS */
2245                         ddr->cs[i].bnds = 0xffffffff;
2246                 }
2247
2248                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2249                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2250                 set_csn_config_2(i, ddr);
2251         }
2252
2253         /*
2254          * In the case we only need to compute the ddr sdram size, we only need
2255          * to set csn registers, so return from here.
2256          */
2257         if (size_only)
2258                 return 0;
2259
2260         set_ddr_eor(ddr, popts);
2261
2262 #if !defined(CONFIG_SYS_FSL_DDR1)
2263         set_timing_cfg_0(ddr, popts, dimm_params);
2264 #endif
2265
2266         set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
2267                          additive_latency);
2268         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
2269         set_timing_cfg_2(ddr, popts, common_dimm,
2270                                 cas_latency, additive_latency);
2271
2272         set_ddr_cdr1(ddr, popts);
2273         set_ddr_cdr2(ddr, popts);
2274         set_ddr_sdram_cfg(ddr, popts, common_dimm);
2275         ip_rev = fsl_ddr_get_version();
2276         if (ip_rev > 0x40400)
2277                 unq_mrs_en = 1;
2278
2279         if (ip_rev > 0x40700)
2280                 ddr->debug[18] = popts->cswl_override;
2281
2282         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
2283         set_ddr_sdram_mode(ddr, popts, common_dimm,
2284                                 cas_latency, additive_latency, unq_mrs_en);
2285         set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
2286 #ifdef CONFIG_SYS_FSL_DDR4
2287         set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2288         set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
2289 #endif
2290         set_ddr_sdram_interval(ddr, popts, common_dimm);
2291         set_ddr_data_init(ddr);
2292         set_ddr_sdram_clk_cntl(ddr, popts);
2293         set_ddr_init_addr(ddr);
2294         set_ddr_init_ext_addr(ddr);
2295         set_timing_cfg_4(ddr, popts);
2296         set_timing_cfg_5(ddr, cas_latency);
2297 #ifdef CONFIG_SYS_FSL_DDR4
2298         set_ddr_sdram_cfg_3(ddr, popts);
2299         set_timing_cfg_6(ddr);
2300         set_timing_cfg_7(ddr, common_dimm);
2301         set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
2302         set_timing_cfg_9(ddr);
2303         set_ddr_dq_mapping(ddr, dimm_params);
2304 #endif
2305
2306         set_ddr_zq_cntl(ddr, zq_en);
2307         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2308
2309         set_ddr_sr_cntr(ddr, sr_it);
2310
2311         set_ddr_sdram_rcw(ddr, popts, common_dimm);
2312
2313 #ifdef CONFIG_SYS_FSL_DDR_EMU
2314         /* disble DDR training for emulator */
2315         ddr->debug[2] = 0x00000400;
2316         ddr->debug[4] = 0xff800000;
2317 #endif
2318 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2319         if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2320                 ddr->debug[2] |= 0x00000200;    /* set bit 22 */
2321 #endif
2322
2323         return check_fsl_memctl_config_regs(ddr);
2324 }