2 * i2c driver for Freescale i.MX series
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/errno.h>
25 DECLARE_GLOBAL_DATA_PTR;
45 #define I2CR_IIEN (1 << 6)
46 #define I2CR_MSTA (1 << 5)
47 #define I2CR_MTX (1 << 4)
48 #define I2CR_TX_NO_AK (1 << 3)
49 #define I2CR_RSTA (1 << 2)
51 #define I2SR_ICF (1 << 7)
52 #define I2SR_IBB (1 << 5)
53 #define I2SR_IAL (1 << 4)
54 #define I2SR_IIF (1 << 1)
55 #define I2SR_RX_NO_AK (1 << 0)
58 #define I2CR_IEN (0 << 7)
59 #define I2CR_IDIS (1 << 7)
60 #define I2SR_IIF_CLEAR (1 << 1)
62 #define I2CR_IEN (1 << 7)
63 #define I2CR_IDIS (0 << 7)
64 #define I2SR_IIF_CLEAR (0 << 1)
67 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
68 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
72 static u16 i2c_clk_div[60][2] = {
73 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
74 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
75 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
76 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
77 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
78 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
79 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
80 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
81 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
82 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
83 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
84 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
85 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
86 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
87 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
90 static u16 i2c_clk_div[50][2] = {
91 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
92 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
93 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
94 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
95 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
96 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
97 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
98 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
99 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
100 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
101 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
102 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
103 { 3072, 0x1E }, { 3840, 0x1F }
108 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
109 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
111 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
112 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
114 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
115 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
117 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
118 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
121 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
122 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
124 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
125 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
127 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
128 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
130 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
131 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
136 * Calculate and set proper clock divider
138 static uint8_t i2c_imx_get_clk(unsigned int rate)
140 unsigned int i2c_clk_rate;
144 #if defined(CONFIG_SOC_MX31)
145 struct clock_control_regs *sc_regs =
146 (struct clock_control_regs *)CCM_BASE;
148 /* start the required I2C clock */
149 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
153 /* Divider value calculation */
154 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
155 div = (i2c_clk_rate + rate - 1) / rate;
156 if (div < i2c_clk_div[0][0])
158 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
159 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
161 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
164 /* Store divider value */
171 static int bus_i2c_set_bus_speed(void *base, int speed)
173 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
174 u8 clk_idx = i2c_imx_get_clk(speed);
175 u8 idx = i2c_clk_div[clk_idx][1];
180 /* Store divider value */
181 writeb(idx, &i2c_regs->ifdr);
184 writeb(I2CR_IDIS, &i2c_regs->i2cr);
185 writeb(0, &i2c_regs->i2sr);
189 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
190 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
191 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
193 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
197 ulong start_time = get_timer(0);
199 sr = readb(&i2c_regs->i2sr);
202 writeb(sr | I2SR_IAL, &i2c_regs->i2sr);
204 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
206 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
207 __func__, sr, readb(&i2c_regs->i2cr), state);
210 if ((sr & (state >> 8)) == (unsigned char)state)
213 elapsed = get_timer(start_time);
214 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
217 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
218 sr, readb(&i2c_regs->i2cr), state);
222 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
226 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
227 writeb(byte, &i2c_regs->i2dr);
228 ret = wait_for_sr_state(i2c_regs, ST_IIF);
231 if (ret & I2SR_RX_NO_AK)
237 * Stop I2C transaction
239 static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
242 unsigned int temp = readb(&i2c_regs->i2cr);
244 temp &= ~(I2CR_MSTA | I2CR_MTX);
245 writeb(temp, &i2c_regs->i2cr);
246 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
248 printf("%s:trigger stop failed\n", __func__);
252 * Send start signal, chip address and
253 * write register address
255 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
256 uchar chip, uint addr, int alen)
261 /* Enable I2C controller */
263 if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
265 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
267 writeb(I2CR_IEN, &i2c_regs->i2cr);
268 /* Wait for controller to be stable */
271 if (readb(&i2c_regs->iadr) == (chip << 1))
272 writeb((chip << 1) ^ 2, &i2c_regs->iadr);
273 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
274 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
278 /* Start I2C transaction */
279 temp = readb(&i2c_regs->i2cr);
281 writeb(temp, &i2c_regs->i2cr);
283 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
287 temp |= I2CR_MTX | I2CR_TX_NO_AK;
288 writeb(temp, &i2c_regs->i2cr);
290 /* write slave address */
291 ret = tx_byte(i2c_regs, chip << 1);
296 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
303 static int i2c_idle_bus(void *base);
305 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
306 uchar chip, uint addr, int alen)
310 for (retry = 0; retry < 3; retry++) {
311 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
314 i2c_imx_stop(i2c_regs);
318 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
320 if (ret != -ERESTART)
321 /* Disable controller */
322 writeb(I2CR_IDIS, &i2c_regs->i2cr);
324 if (i2c_idle_bus(i2c_regs) < 0)
327 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
332 * Read data from I2C device
334 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
340 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
345 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
349 temp = readb(&i2c_regs->i2cr);
351 writeb(temp, &i2c_regs->i2cr);
353 ret = tx_byte(i2c_regs, (chip << 1) | 1);
355 i2c_imx_stop(i2c_regs);
359 /* setup bus to read data */
360 temp = readb(&i2c_regs->i2cr);
361 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
363 temp |= I2CR_TX_NO_AK;
364 writeb(temp, &i2c_regs->i2cr);
365 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
366 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
369 for (i = 0; i < len; i++) {
370 ret = wait_for_sr_state(i2c_regs, ST_IIF);
372 i2c_imx_stop(i2c_regs);
377 * It must generate STOP before read I2DR to prevent
378 * controller from generating another clock cycle
380 if (i == (len - 1)) {
381 i2c_imx_stop(i2c_regs);
382 } else if (i == (len - 2)) {
383 temp = readb(&i2c_regs->i2cr);
384 temp |= I2CR_TX_NO_AK;
385 writeb(temp, &i2c_regs->i2cr);
387 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
388 buf[i] = readb(&i2c_regs->i2dr);
390 i2c_imx_stop(i2c_regs);
395 * Write data to I2C device
397 int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
398 const uchar *buf, int len)
402 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
407 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
411 for (i = 0; i < len; i++) {
412 ret = tx_byte(i2c_regs, buf[i]);
416 i2c_imx_stop(i2c_regs);
420 static void * const i2c_bases[] = {
421 #if defined(CONFIG_SOC_MX25)
422 (void *)IMX_I2C_BASE,
423 (void *)IMX_I2C2_BASE,
424 (void *)IMX_I2C3_BASE
425 #elif defined(CONFIG_SOC_MX27)
426 (void *)IMX_I2C1_BASE,
427 (void *)IMX_I2C2_BASE
428 #elif defined(CONFIG_SOC_MX31) || defined(CONFIG_SOC_MX35) || \
429 defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || \
430 defined(CONFIG_SOC_MX6) || defined(CONFIG_LS102XA)
431 (void *)I2C1_BASE_ADDR,
432 (void *)I2C2_BASE_ADDR,
433 (void *)I2C3_BASE_ADDR
434 #elif defined(CONFIG_SOC_VF610)
435 (void *)I2C0_BASE_ADDR
436 #elif defined(CONFIG_FSL_LSCH3)
437 (void *)I2C1_BASE_ADDR,
438 (void *)I2C2_BASE_ADDR,
439 (void *)I2C3_BASE_ADDR,
440 (void *)I2C4_BASE_ADDR
442 #error "architecture not supported"
449 int (*idle_bus_fn)(void *p);
453 unsigned curr_i2c_bus;
454 struct i2c_parms i2c_data[ARRAY_SIZE(i2c_bases)];
457 void *i2c_get_base(struct i2c_adapter *adap)
459 return i2c_bases[adap->hwadapnr];
462 static struct i2c_parms *i2c_get_parms(void *base)
464 struct sram_data *srdata = (void *)gd->srdata;
466 struct i2c_parms *p = srdata->i2c_data;
467 while (i < ARRAY_SIZE(srdata->i2c_data)) {
473 printf("Invalid I2C base: %p\n", base);
477 static int i2c_idle_bus(void *base)
479 struct i2c_parms *p = i2c_get_parms(base);
480 if (p && p->idle_bus_fn)
481 return p->idle_bus_fn(p->idle_bus_data);
485 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
486 uint addr, int alen, uint8_t *buffer,
489 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
492 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
493 uint addr, int alen, uint8_t *buffer,
496 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
500 * Test if a chip at a given address responds (probe the chip)
502 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
504 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
507 void bus_i2c_init(void *base, int speed, int unused,
508 int (*idle_bus_fn)(void *p), void *idle_bus_data)
510 struct sram_data *srdata = (void *)gd->srdata;
512 struct i2c_parms *p = srdata->i2c_data;
516 if (!p->base || (p->base == base)) {
519 p->idle_bus_fn = idle_bus_fn;
520 p->idle_bus_data = idle_bus_data;
526 if (i >= ARRAY_SIZE(srdata->i2c_data))
529 bus_i2c_set_bus_speed(base, speed);
535 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
537 bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
543 static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
545 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
549 * Register mxc i2c adapters
551 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
552 mxc_i2c_read, mxc_i2c_write,
553 mxc_i2c_set_bus_speed,
554 CONFIG_SYS_MXC_I2C1_SPEED,
555 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
556 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
557 mxc_i2c_read, mxc_i2c_write,
558 mxc_i2c_set_bus_speed,
559 CONFIG_SYS_MXC_I2C2_SPEED,
560 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
561 #ifdef CONFIG_SYS_I2C_MXC_I2C3
562 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
563 mxc_i2c_read, mxc_i2c_write,
564 mxc_i2c_set_bus_speed,
565 CONFIG_SYS_MXC_I2C3_SPEED,
566 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
568 #ifdef CONFIG_SYS_I2C_MXC_I2C4
569 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
570 mxc_i2c_read, mxc_i2c_write,
571 mxc_i2c_set_bus_speed,
572 CONFIG_SYS_MXC_I2C4_SPEED,
573 CONFIG_SYS_MXC_I2C4_SLAVE, 3)