2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
20 #include <linux/list.h>
22 #include "mmc_private.h"
24 static const unsigned int sd_au_size[] = {
25 0, SZ_16K / 512, SZ_32K / 512,
26 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
27 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
28 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
29 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
32 #ifndef CONFIG_DM_MMC_OPS
33 __weak int board_mmc_getwp(struct mmc *mmc)
38 int mmc_getwp(struct mmc *mmc)
42 wp = board_mmc_getwp(mmc);
45 if (mmc->cfg->ops->getwp)
46 wp = mmc->cfg->ops->getwp(mmc);
54 __weak int board_mmc_getcd(struct mmc *mmc)
60 #ifdef CONFIG_MMC_TRACE
61 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
63 printf("CMD_SEND:%d\n", cmd->cmdidx);
64 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
67 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
73 printf("\t\tRET\t\t\t %d\n", ret);
75 switch (cmd->resp_type) {
77 printf("\t\tMMC_RSP_NONE\n");
80 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
84 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
88 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
90 printf("\t\t \t\t 0x%08X \n",
92 printf("\t\t \t\t 0x%08X \n",
94 printf("\t\t \t\t 0x%08X \n",
97 printf("\t\t\t\t\tDUMPING DATA\n");
98 for (i = 0; i < 4; i++) {
100 printf("\t\t\t\t\t%03d - ", i*4);
101 ptr = (u8 *)&cmd->response[i];
103 for (j = 0; j < 4; j++)
104 printf("%02X ", *ptr--);
109 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
113 printf("\t\tERROR MMC rsp not supported\n");
119 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
123 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
124 printf("CURR STATE:%d\n", status);
128 #ifndef CONFIG_DM_MMC_OPS
129 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
133 mmmc_trace_before_send(mmc, cmd);
134 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
135 mmmc_trace_after_send(mmc, cmd, ret);
141 int mmc_send_status(struct mmc *mmc, int timeout)
146 const int max_tries = 5000;
148 cmd.cmdidx = MMC_CMD_SEND_STATUS;
149 cmd.resp_type = MMC_RSP_R1;
150 if (!mmc_host_is_spi(mmc))
151 cmd.cmdarg = mmc->rca << 16;
154 err = mmc_send_cmd(mmc, &cmd, NULL);
156 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
157 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
160 else if (cmd.response[0] & MMC_STATUS_MASK) {
161 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
162 printf("Status Error: 0x%08X\n",
170 printf("(e)MMC is busy; please wait... ");
171 if (retries++ > max_tries)
184 mmc_trace_state(mmc, &cmd);
186 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
187 printf("Timeout waiting for card ready\n");
195 int mmc_set_blocklen(struct mmc *mmc, int len)
202 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
203 cmd.resp_type = MMC_RSP_R1;
206 return mmc_send_cmd(mmc, &cmd, NULL);
209 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
213 struct mmc_data data;
216 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
218 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
220 if (mmc->high_capacity)
223 cmd.cmdarg = start * mmc->read_bl_len;
225 cmd.resp_type = MMC_RSP_R1;
228 data.blocks = blkcnt;
229 data.blocksize = mmc->read_bl_len;
230 data.flags = MMC_DATA_READ;
232 if (mmc_send_cmd(mmc, &cmd, &data))
236 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
238 cmd.resp_type = MMC_RSP_R1b;
239 if (mmc_send_cmd(mmc, &cmd, NULL)) {
240 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
241 printf("mmc fail to send stop cmd\n");
251 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
253 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
258 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
260 int dev_num = block_dev->devnum;
262 lbaint_t cur, blocks_todo = blkcnt;
267 struct mmc *mmc = find_mmc_device(dev_num);
271 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
275 if ((start + blkcnt) > block_dev->lba) {
276 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
277 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
278 start + blkcnt, block_dev->lba);
283 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
284 debug("%s: Failed to set blocklen\n", __func__);
289 cur = (blocks_todo > mmc->cfg->b_max) ?
290 mmc->cfg->b_max : blocks_todo;
291 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
292 debug("%s: Failed to read blocks\n", __func__);
297 dst += cur * mmc->read_bl_len;
298 } while (blocks_todo > 0);
303 static int mmc_go_idle(struct mmc *mmc)
310 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
312 cmd.resp_type = MMC_RSP_NONE;
314 err = mmc_send_cmd(mmc, &cmd, NULL);
324 static int sd_send_op_cond(struct mmc *mmc)
331 cmd.cmdidx = MMC_CMD_APP_CMD;
332 cmd.resp_type = MMC_RSP_R1;
335 err = mmc_send_cmd(mmc, &cmd, NULL);
340 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
341 cmd.resp_type = MMC_RSP_R3;
344 * Most cards do not answer if some reserved bits
345 * in the ocr are set. However, Some controller
346 * can set bit 7 (reserved for low voltages), but
347 * how to manage low voltages SD card is not yet
350 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
351 (mmc->cfg->voltages & 0xff8000);
353 if (mmc->version == SD_VERSION_2)
354 cmd.cmdarg |= OCR_HCS;
356 err = mmc_send_cmd(mmc, &cmd, NULL);
361 if (cmd.response[0] & OCR_BUSY)
370 if (mmc->version != SD_VERSION_2)
371 mmc->version = SD_VERSION_1_0;
373 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
374 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
375 cmd.resp_type = MMC_RSP_R3;
378 err = mmc_send_cmd(mmc, &cmd, NULL);
384 mmc->ocr = cmd.response[0];
386 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
392 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
397 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
398 cmd.resp_type = MMC_RSP_R3;
400 if (use_arg && !mmc_host_is_spi(mmc))
401 cmd.cmdarg = OCR_HCS |
402 (mmc->cfg->voltages &
403 (mmc->ocr & OCR_VOLTAGE_MASK)) |
404 (mmc->ocr & OCR_ACCESS_MODE);
406 err = mmc_send_cmd(mmc, &cmd, NULL);
409 mmc->ocr = cmd.response[0];
413 static int mmc_send_op_cond(struct mmc *mmc)
417 /* Some cards seem to need this */
420 /* Asking the card for its capabilities */
421 for (i = 0; i < 2; i++) {
422 err = mmc_send_op_cond_iter(mmc, i != 0);
426 /* exit if not busy (flag seems to be inverted) */
427 if (mmc->ocr & OCR_BUSY)
430 mmc->op_cond_pending = 1;
434 static int mmc_complete_op_cond(struct mmc *mmc)
437 int timeout = 10 * CONFIG_SYS_HZ;
441 mmc->op_cond_pending = 0;
442 if (!(mmc->ocr & OCR_BUSY)) {
443 /* Some cards seem to need this */
446 start = get_timer(0);
448 err = mmc_send_op_cond_iter(mmc, 1);
451 if (mmc->ocr & OCR_BUSY)
453 if (get_timer(start) > timeout)
459 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
460 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
461 cmd.resp_type = MMC_RSP_R3;
464 err = mmc_send_cmd(mmc, &cmd, NULL);
469 mmc->ocr = cmd.response[0];
472 mmc->version = MMC_VERSION_UNKNOWN;
474 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
481 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
484 struct mmc_data data;
487 /* Get the Card Status Register */
488 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
489 cmd.resp_type = MMC_RSP_R1;
492 data.dest = (char *)ext_csd;
494 data.blocksize = MMC_MAX_BLOCK_LEN;
495 data.flags = MMC_DATA_READ;
497 err = mmc_send_cmd(mmc, &cmd, &data);
502 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
508 cmd.cmdidx = MMC_CMD_SWITCH;
509 cmd.resp_type = MMC_RSP_R1b;
510 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
514 ret = mmc_send_cmd(mmc, &cmd, NULL);
516 /* Waiting for the ready status */
518 ret = mmc_send_status(mmc, timeout);
523 static int mmc_change_freq(struct mmc *mmc)
525 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
531 if (mmc_host_is_spi(mmc))
534 /* Only version 4 supports high-speed */
535 if (mmc->version < MMC_VERSION_4)
538 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
540 err = mmc_send_ext_csd(mmc, ext_csd);
545 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
547 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
552 /* Now check to see that it worked */
553 err = mmc_send_ext_csd(mmc, ext_csd);
558 /* No high-speed support */
559 if (!ext_csd[EXT_CSD_HS_TIMING])
562 /* High Speed is set, there are two types: 52MHz and 26MHz */
563 if (cardtype & EXT_CSD_CARD_TYPE_52) {
564 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
565 mmc->card_caps |= MMC_MODE_DDR_52MHz;
566 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
568 mmc->card_caps |= MMC_MODE_HS;
574 static int mmc_set_capacity(struct mmc *mmc, int part_num)
578 mmc->capacity = mmc->capacity_user;
582 mmc->capacity = mmc->capacity_boot;
585 mmc->capacity = mmc->capacity_rpmb;
591 mmc->capacity = mmc->capacity_gp[part_num - 4];
597 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
602 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
606 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
607 (mmc->part_config & ~PART_ACCESS_MASK)
608 | (part_num & PART_ACCESS_MASK));
611 * Set the capacity if the switch succeeded or was intended
612 * to return to representing the raw device.
614 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
615 ret = mmc_set_capacity(mmc, part_num);
616 mmc_get_blk_desc(mmc)->hwpart = part_num;
622 int mmc_hwpart_config(struct mmc *mmc,
623 const struct mmc_hwpart_conf *conf,
624 enum mmc_hwpart_conf_mode mode)
630 u32 max_enh_size_mult;
631 u32 tot_enh_size_mult = 0;
634 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
636 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
639 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
640 printf("eMMC >= 4.4 required for enhanced user data area\n");
644 if (!(mmc->part_support & PART_SUPPORT)) {
645 printf("Card does not support partitioning\n");
649 if (!mmc->hc_wp_grp_size) {
650 printf("Card does not define HC WP group size\n");
654 /* check partition alignment and total enhanced size */
655 if (conf->user.enh_size) {
656 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
657 conf->user.enh_start % mmc->hc_wp_grp_size) {
658 printf("User data enhanced area not HC WP group "
662 part_attrs |= EXT_CSD_ENH_USR;
663 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
664 if (mmc->high_capacity) {
665 enh_start_addr = conf->user.enh_start;
667 enh_start_addr = (conf->user.enh_start << 9);
673 tot_enh_size_mult += enh_size_mult;
675 for (pidx = 0; pidx < 4; pidx++) {
676 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
677 printf("GP%i partition not HC WP group size "
678 "aligned\n", pidx+1);
681 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
682 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
683 part_attrs |= EXT_CSD_ENH_GP(pidx);
684 tot_enh_size_mult += gp_size_mult[pidx];
688 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
689 printf("Card does not support enhanced attribute\n");
693 err = mmc_send_ext_csd(mmc, ext_csd);
698 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
699 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
700 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
701 if (tot_enh_size_mult > max_enh_size_mult) {
702 printf("Total enhanced size exceeds maximum (%u > %u)\n",
703 tot_enh_size_mult, max_enh_size_mult);
707 /* The default value of EXT_CSD_WR_REL_SET is device
708 * dependent, the values can only be changed if the
709 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
710 * changed only once and before partitioning is completed. */
711 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
712 if (conf->user.wr_rel_change) {
713 if (conf->user.wr_rel_set)
714 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
716 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
718 for (pidx = 0; pidx < 4; pidx++) {
719 if (conf->gp_part[pidx].wr_rel_change) {
720 if (conf->gp_part[pidx].wr_rel_set)
721 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
723 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
727 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
728 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
729 puts("Card does not support host controlled partition write "
730 "reliability settings\n");
734 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
735 EXT_CSD_PARTITION_SETTING_COMPLETED) {
736 printf("Card already partitioned\n");
740 if (mode == MMC_HWPART_CONF_CHECK)
743 /* Partitioning requires high-capacity size definitions */
744 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
745 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
746 EXT_CSD_ERASE_GROUP_DEF, 1);
751 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
753 /* update erase group size to be high-capacity */
754 mmc->erase_grp_size =
755 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
759 /* all OK, write the configuration */
760 for (i = 0; i < 4; i++) {
761 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
762 EXT_CSD_ENH_START_ADDR+i,
763 (enh_start_addr >> (i*8)) & 0xFF);
767 for (i = 0; i < 3; i++) {
768 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
769 EXT_CSD_ENH_SIZE_MULT+i,
770 (enh_size_mult >> (i*8)) & 0xFF);
774 for (pidx = 0; pidx < 4; pidx++) {
775 for (i = 0; i < 3; i++) {
776 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
777 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
778 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
783 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
784 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
788 if (mode == MMC_HWPART_CONF_SET)
791 /* The WR_REL_SET is a write-once register but shall be
792 * written before setting PART_SETTING_COMPLETED. As it is
793 * write-once we can only write it when completing the
795 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
796 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
797 EXT_CSD_WR_REL_SET, wr_rel_set);
802 /* Setting PART_SETTING_COMPLETED confirms the partition
803 * configuration but it only becomes effective after power
804 * cycle, so we do not adjust the partition related settings
805 * in the mmc struct. */
807 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
808 EXT_CSD_PARTITION_SETTING,
809 EXT_CSD_PARTITION_SETTING_COMPLETED);
816 #ifndef CONFIG_DM_MMC_OPS
817 int mmc_getcd(struct mmc *mmc)
821 cd = board_mmc_getcd(mmc);
824 if (mmc->cfg->ops->getcd)
825 cd = mmc->cfg->ops->getcd(mmc);
834 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
837 struct mmc_data data;
839 /* Switch the frequency */
840 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
841 cmd.resp_type = MMC_RSP_R1;
842 cmd.cmdarg = (mode << 31) | 0xffffff;
843 cmd.cmdarg &= ~(0xf << (group * 4));
844 cmd.cmdarg |= value << (group * 4);
846 data.dest = (char *)resp;
849 data.flags = MMC_DATA_READ;
851 return mmc_send_cmd(mmc, &cmd, &data);
855 static int sd_change_freq(struct mmc *mmc)
859 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
860 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
861 struct mmc_data data;
866 if (mmc_host_is_spi(mmc))
869 /* Read the SCR to find out if this card supports higher speeds */
870 cmd.cmdidx = MMC_CMD_APP_CMD;
871 cmd.resp_type = MMC_RSP_R1;
872 cmd.cmdarg = mmc->rca << 16;
874 err = mmc_send_cmd(mmc, &cmd, NULL);
879 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
880 cmd.resp_type = MMC_RSP_R1;
886 data.dest = (char *)scr;
889 data.flags = MMC_DATA_READ;
891 err = mmc_send_cmd(mmc, &cmd, &data);
900 mmc->scr[0] = __be32_to_cpu(scr[0]);
901 mmc->scr[1] = __be32_to_cpu(scr[1]);
903 switch ((mmc->scr[0] >> 24) & 0xf) {
905 mmc->version = SD_VERSION_1_0;
908 mmc->version = SD_VERSION_1_10;
911 mmc->version = SD_VERSION_2;
912 if ((mmc->scr[0] >> 15) & 0x1)
913 mmc->version = SD_VERSION_3;
916 mmc->version = SD_VERSION_1_0;
920 if (mmc->scr[0] & SD_DATA_4BIT)
921 mmc->card_caps |= MMC_MODE_4BIT;
923 /* Version 1.0 doesn't support switching */
924 if (mmc->version == SD_VERSION_1_0)
929 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
930 (u8 *)switch_status);
935 /* The high-speed function is busy. Try again */
936 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
940 /* If high-speed isn't supported, we return */
941 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
945 * If the host doesn't support SD_HIGHSPEED, do not switch card to
946 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
947 * This can avoid furthur problem when the card runs in different
948 * mode between the host.
950 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
951 (mmc->cfg->host_caps & MMC_MODE_HS)))
954 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
959 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
960 mmc->card_caps |= MMC_MODE_HS;
965 static int sd_read_ssr(struct mmc *mmc)
969 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
970 struct mmc_data data;
972 unsigned int au, eo, et, es;
974 cmd.cmdidx = MMC_CMD_APP_CMD;
975 cmd.resp_type = MMC_RSP_R1;
976 cmd.cmdarg = mmc->rca << 16;
978 err = mmc_send_cmd(mmc, &cmd, NULL);
982 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
983 cmd.resp_type = MMC_RSP_R1;
987 data.dest = (char *)ssr;
990 data.flags = MMC_DATA_READ;
992 err = mmc_send_cmd(mmc, &cmd, &data);
1000 for (i = 0; i < 16; i++)
1001 ssr[i] = be32_to_cpu(ssr[i]);
1003 au = (ssr[2] >> 12) & 0xF;
1004 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1005 mmc->ssr.au = sd_au_size[au];
1006 es = (ssr[3] >> 24) & 0xFF;
1007 es |= (ssr[2] & 0xFF) << 8;
1008 et = (ssr[3] >> 18) & 0x3F;
1010 eo = (ssr[3] >> 16) & 0x3;
1011 mmc->ssr.erase_timeout = (et * 1000) / es;
1012 mmc->ssr.erase_offset = eo * 1000;
1015 debug("Invalid Allocation Unit Size.\n");
1021 /* frequency bases */
1022 /* divided by 10 to be nice to platforms without floating point */
1023 static const int fbase[] = {
1030 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1031 * to platforms without floating point.
1033 static const u8 multipliers[] = {
1052 #ifndef CONFIG_DM_MMC_OPS
1053 static void mmc_set_ios(struct mmc *mmc)
1055 if (mmc->cfg->ops->set_ios)
1056 mmc->cfg->ops->set_ios(mmc);
1060 void mmc_set_clock(struct mmc *mmc, uint clock)
1062 if (clock > mmc->cfg->f_max)
1063 clock = mmc->cfg->f_max;
1065 if (clock < mmc->cfg->f_min)
1066 clock = mmc->cfg->f_min;
1073 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1075 mmc->bus_width = width;
1080 static int mmc_startup(struct mmc *mmc)
1084 u64 cmult, csize, capacity;
1086 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1087 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1089 bool has_parts = false;
1090 bool part_completed;
1091 struct blk_desc *bdesc;
1093 #ifdef CONFIG_MMC_SPI_CRC_ON
1094 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1095 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1096 cmd.resp_type = MMC_RSP_R1;
1098 err = mmc_send_cmd(mmc, &cmd, NULL);
1105 /* Put the Card in Identify Mode */
1106 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1107 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1108 cmd.resp_type = MMC_RSP_R2;
1111 err = mmc_send_cmd(mmc, &cmd, NULL);
1116 memcpy(mmc->cid, cmd.response, 16);
1119 * For MMC cards, set the Relative Address.
1120 * For SD cards, get the Relatvie Address.
1121 * This also puts the cards into Standby State
1123 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1124 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1125 cmd.cmdarg = mmc->rca << 16;
1126 cmd.resp_type = MMC_RSP_R6;
1128 err = mmc_send_cmd(mmc, &cmd, NULL);
1134 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1137 /* Get the Card-Specific Data */
1138 cmd.cmdidx = MMC_CMD_SEND_CSD;
1139 cmd.resp_type = MMC_RSP_R2;
1140 cmd.cmdarg = mmc->rca << 16;
1142 err = mmc_send_cmd(mmc, &cmd, NULL);
1146 /* Waiting for the ready status */
1147 err = mmc_send_status(mmc, timeout);
1151 mmc->csd[0] = cmd.response[0];
1152 mmc->csd[1] = cmd.response[1];
1153 mmc->csd[2] = cmd.response[2];
1154 mmc->csd[3] = cmd.response[3];
1156 if (mmc->version == MMC_VERSION_UNKNOWN) {
1157 int version = (cmd.response[0] >> 26) & 0xf;
1161 mmc->version = MMC_VERSION_1_2;
1164 mmc->version = MMC_VERSION_1_4;
1167 mmc->version = MMC_VERSION_2_2;
1170 mmc->version = MMC_VERSION_3;
1173 mmc->version = MMC_VERSION_4;
1176 mmc->version = MMC_VERSION_1_2;
1181 /* divide frequency by 10, since the mults are 10x bigger */
1182 freq = fbase[(cmd.response[0] & 0x7)];
1183 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1185 mmc->tran_speed = freq * mult;
1187 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1188 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1191 mmc->write_bl_len = mmc->read_bl_len;
1193 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1195 if (mmc->high_capacity) {
1196 csize = (mmc->csd[1] & 0x3f) << 16
1197 | (mmc->csd[2] & 0xffff0000) >> 16;
1200 csize = (mmc->csd[1] & 0x3ff) << 2
1201 | (mmc->csd[2] & 0xc0000000) >> 30;
1202 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1205 mmc->capacity_user = (csize + 1) << (cmult + 2);
1206 mmc->capacity_user *= mmc->read_bl_len;
1207 mmc->capacity_boot = 0;
1208 mmc->capacity_rpmb = 0;
1209 for (i = 0; i < 4; i++)
1210 mmc->capacity_gp[i] = 0;
1212 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1213 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1215 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1216 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1218 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1219 cmd.cmdidx = MMC_CMD_SET_DSR;
1220 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1221 cmd.resp_type = MMC_RSP_NONE;
1222 if (mmc_send_cmd(mmc, &cmd, NULL))
1223 printf("MMC: SET_DSR failed\n");
1226 /* Select the card, and put it into Transfer Mode */
1227 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1228 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1229 cmd.resp_type = MMC_RSP_R1;
1230 cmd.cmdarg = mmc->rca << 16;
1231 err = mmc_send_cmd(mmc, &cmd, NULL);
1238 * For SD, its erase group is always one sector
1240 mmc->erase_grp_size = 1;
1241 mmc->part_config = MMCPART_NOAVAILABLE;
1242 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1243 /* check ext_csd version and capacity */
1245 err = mmc_send_ext_csd(mmc, ext_csd);
1248 if (ext_csd[EXT_CSD_REV] >= 2) {
1250 * According to the JEDEC Standard, the value of
1251 * ext_csd's capacity is valid if the value is more
1254 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1255 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1256 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1257 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1258 capacity *= MMC_MAX_BLOCK_LEN;
1259 if ((capacity >> 20) > 2 * 1024)
1260 mmc->capacity_user = capacity;
1263 switch (ext_csd[EXT_CSD_REV]) {
1265 mmc->version = MMC_VERSION_4_1;
1268 mmc->version = MMC_VERSION_4_2;
1271 mmc->version = MMC_VERSION_4_3;
1274 mmc->version = MMC_VERSION_4_41;
1277 mmc->version = MMC_VERSION_4_5;
1280 mmc->version = MMC_VERSION_5_0;
1283 mmc->version = MMC_VERSION_5_1;
1287 /* The partition data may be non-zero but it is only
1288 * effective if PARTITION_SETTING_COMPLETED is set in
1289 * EXT_CSD, so ignore any data if this bit is not set,
1290 * except for enabling the high-capacity group size
1291 * definition (see below). */
1292 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1293 EXT_CSD_PARTITION_SETTING_COMPLETED);
1295 /* store the partition info of emmc */
1296 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1297 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1298 ext_csd[EXT_CSD_BOOT_MULT])
1299 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1300 if (part_completed &&
1301 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1302 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1304 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1306 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1308 for (i = 0; i < 4; i++) {
1309 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1310 uint mult = (ext_csd[idx + 2] << 16) +
1311 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1314 if (!part_completed)
1316 mmc->capacity_gp[i] = mult;
1317 mmc->capacity_gp[i] *=
1318 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1319 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1320 mmc->capacity_gp[i] <<= 19;
1323 if (part_completed) {
1324 mmc->enh_user_size =
1325 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1326 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1327 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1328 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1329 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1330 mmc->enh_user_size <<= 19;
1331 mmc->enh_user_start =
1332 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1333 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1334 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1335 ext_csd[EXT_CSD_ENH_START_ADDR];
1336 if (mmc->high_capacity)
1337 mmc->enh_user_start <<= 9;
1341 * Host needs to enable ERASE_GRP_DEF bit if device is
1342 * partitioned. This bit will be lost every time after a reset
1343 * or power off. This will affect erase size.
1347 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1348 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1351 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1352 EXT_CSD_ERASE_GROUP_DEF, 1);
1357 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1360 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1361 /* Read out group size from ext_csd */
1362 mmc->erase_grp_size =
1363 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1365 * if high capacity and partition setting completed
1366 * SEC_COUNT is valid even if it is smaller than 2 GiB
1367 * JEDEC Standard JESD84-B45, 6.2.4
1369 if (mmc->high_capacity && part_completed) {
1370 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1371 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1372 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1373 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1374 capacity *= MMC_MAX_BLOCK_LEN;
1375 mmc->capacity_user = capacity;
1378 /* Calculate the group size from the csd value. */
1379 int erase_gsz, erase_gmul;
1380 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1381 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1382 mmc->erase_grp_size = (erase_gsz + 1)
1386 mmc->hc_wp_grp_size = 1024
1387 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1388 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1390 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1393 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1398 err = sd_change_freq(mmc);
1400 err = mmc_change_freq(mmc);
1405 /* Restrict card's capabilities by what the host can do */
1406 mmc->card_caps &= mmc->cfg->host_caps;
1409 if (mmc->card_caps & MMC_MODE_4BIT) {
1410 cmd.cmdidx = MMC_CMD_APP_CMD;
1411 cmd.resp_type = MMC_RSP_R1;
1412 cmd.cmdarg = mmc->rca << 16;
1414 err = mmc_send_cmd(mmc, &cmd, NULL);
1418 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1419 cmd.resp_type = MMC_RSP_R1;
1421 err = mmc_send_cmd(mmc, &cmd, NULL);
1425 mmc_set_bus_width(mmc, 4);
1428 err = sd_read_ssr(mmc);
1432 if (mmc->card_caps & MMC_MODE_HS)
1433 mmc->tran_speed = 50000000;
1435 mmc->tran_speed = 25000000;
1436 } else if (mmc->version >= MMC_VERSION_4) {
1437 /* Only version 4 of MMC supports wider bus widths */
1440 /* An array of possible bus widths in order of preference */
1441 static unsigned ext_csd_bits[] = {
1442 EXT_CSD_DDR_BUS_WIDTH_8,
1443 EXT_CSD_DDR_BUS_WIDTH_4,
1444 EXT_CSD_BUS_WIDTH_8,
1445 EXT_CSD_BUS_WIDTH_4,
1446 EXT_CSD_BUS_WIDTH_1,
1449 /* An array to map CSD bus widths to host cap bits */
1450 static unsigned ext_to_hostcaps[] = {
1451 [EXT_CSD_DDR_BUS_WIDTH_4] =
1452 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1453 [EXT_CSD_DDR_BUS_WIDTH_8] =
1454 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1455 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1456 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1459 /* An array to map chosen bus width to an integer */
1460 static unsigned widths[] = {
1464 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1465 unsigned int extw = ext_csd_bits[idx];
1466 unsigned int caps = ext_to_hostcaps[extw];
1469 * If the bus width is still not changed,
1470 * don't try to set the default again.
1471 * Otherwise, recover from switch attempts
1472 * by switching to 1-bit bus width.
1474 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1475 mmc->bus_width == 1) {
1481 * Check to make sure the card and controller support
1482 * these capabilities
1484 if ((mmc->card_caps & caps) != caps)
1487 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1488 EXT_CSD_BUS_WIDTH, extw);
1493 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1494 mmc_set_bus_width(mmc, widths[idx]);
1496 err = mmc_send_ext_csd(mmc, test_csd);
1501 /* Only compare read only fields */
1502 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1503 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1504 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1505 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1506 ext_csd[EXT_CSD_REV]
1507 == test_csd[EXT_CSD_REV] &&
1508 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1509 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1510 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1511 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1520 if (mmc->card_caps & MMC_MODE_HS) {
1521 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1522 mmc->tran_speed = 52000000;
1524 mmc->tran_speed = 26000000;
1528 mmc_set_clock(mmc, mmc->tran_speed);
1530 /* Fix the block length for DDR mode */
1531 if (mmc->ddr_mode) {
1532 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1533 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1536 /* fill in device description */
1537 bdesc = mmc_get_blk_desc(mmc);
1541 bdesc->blksz = mmc->read_bl_len;
1542 bdesc->log2blksz = LOG2(bdesc->blksz);
1543 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1544 #if !defined(CONFIG_SPL_BUILD) || \
1545 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1546 !defined(CONFIG_USE_TINY_PRINTF))
1547 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1548 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1549 (mmc->cid[3] >> 16) & 0xffff);
1550 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1551 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1552 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1553 (mmc->cid[2] >> 24) & 0xff);
1554 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1555 (mmc->cid[2] >> 16) & 0xf);
1557 bdesc->vendor[0] = 0;
1558 bdesc->product[0] = 0;
1559 bdesc->revision[0] = 0;
1561 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1568 static int mmc_send_if_cond(struct mmc *mmc)
1573 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1574 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1575 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1576 cmd.resp_type = MMC_RSP_R7;
1578 err = mmc_send_cmd(mmc, &cmd, NULL);
1583 if ((cmd.response[0] & 0xff) != 0xaa)
1586 mmc->version = SD_VERSION_2;
1591 /* board-specific MMC power initializations. */
1592 __weak void board_mmc_power_init(void)
1596 int mmc_start_init(struct mmc *mmc)
1601 /* we pretend there's no card when init is NULL */
1602 no_card = mmc_getcd(mmc) == 0;
1603 #ifndef CONFIG_DM_MMC_OPS
1604 no_card = no_card || (mmc->cfg->ops->init == NULL);
1608 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1609 printf("MMC: no card present\n");
1617 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1618 mmc_adapter_card_type_ident();
1620 board_mmc_power_init();
1622 #ifdef CONFIG_DM_MMC_OPS
1623 /* The device has already been probed ready for use */
1625 /* made sure it's not NULL earlier */
1626 err = mmc->cfg->ops->init(mmc);
1631 mmc_set_bus_width(mmc, 1);
1632 mmc_set_clock(mmc, 1);
1634 /* Reset the Card */
1635 err = mmc_go_idle(mmc);
1640 /* The internal partition reset to user partition(0) at every CMD0*/
1641 mmc_get_blk_desc(mmc)->hwpart = 0;
1643 /* Test for SD version 2 */
1644 err = mmc_send_if_cond(mmc);
1646 /* Now try to get the SD card's operating condition */
1647 err = sd_send_op_cond(mmc);
1649 /* If the command timed out, we check for an MMC card */
1650 if (err == -ETIMEDOUT) {
1651 err = mmc_send_op_cond(mmc);
1654 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1655 printf("Card did not respond to voltage select!\n");
1662 mmc->init_in_progress = 1;
1667 static int mmc_complete_init(struct mmc *mmc)
1671 mmc->init_in_progress = 0;
1672 if (mmc->op_cond_pending)
1673 err = mmc_complete_op_cond(mmc);
1676 err = mmc_startup(mmc);
1684 int mmc_init(struct mmc *mmc)
1687 unsigned long start;
1688 #ifdef CONFIG_DM_MMC
1689 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
1696 start = get_timer(0);
1698 if (!mmc->init_in_progress)
1699 err = mmc_start_init(mmc);
1702 err = mmc_complete_init(mmc);
1703 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1707 int mmc_set_dsr(struct mmc *mmc, u16 val)
1713 /* CPU-specific MMC initializations */
1714 __weak int cpu_mmc_init(bd_t *bis)
1719 /* board-specific MMC initializations. */
1720 __weak int board_mmc_init(bd_t *bis)
1725 void mmc_set_preinit(struct mmc *mmc, int preinit)
1727 mmc->preinit = preinit;
1730 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1731 static int mmc_probe(bd_t *bis)
1735 #elif defined(CONFIG_DM_MMC)
1736 static int mmc_probe(bd_t *bis)
1740 struct udevice *dev;
1742 ret = uclass_get(UCLASS_MMC, &uc);
1747 * Try to add them in sequence order. Really with driver model we
1748 * should allow holes, but the current MMC list does not allow that.
1749 * So if we request 0, 1, 3 we will get 0, 1, 2.
1751 for (i = 0; ; i++) {
1752 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1756 uclass_foreach_dev(dev, uc) {
1757 ret = device_probe(dev);
1759 printf("%s - probe failed: %d\n", dev->name, ret);
1765 static int mmc_probe(bd_t *bis)
1767 if (board_mmc_init(bis) < 0)
1774 int mmc_initialize(bd_t *bis)
1776 static int initialized = 0;
1778 if (initialized) /* Avoid initializing mmc multiple times */
1785 ret = mmc_probe(bis);
1789 #ifndef CONFIG_SPL_BUILD
1790 print_mmc_devices(',');