drivers/mmc/tegra2_mmc.c

   1 /*
   2  * (C) Copyright 2009 SAMSUNG Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Jaehoon Chung <jh80.chung@samsung.com>
   5  * Portions Copyright 2011 NVIDIA Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <common.h>
  23 #include <mmc.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/clk_rst.h>
  26 #include <asm/arch/clock.h>
  27 #include "tegra2_mmc.h"
  28
  29 /* support 4 mmc hosts */
  30 struct mmc mmc_dev[4];
  31 struct mmc_host mmc_host[4];
  32
  33
  34 /**
  35  * Get the host address and peripheral ID for a device. Devices are numbered
  36  * from 0 to 3.
  37  *
  38  * @param host          Structure to fill in (base, reg, mmc_id)
  39  * @param dev_index     Device index (0-3)
  40  */
  41 static void tegra2_get_setup(struct mmc_host *host, int dev_index)
  42 {
  43         debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
  44
  45         switch (dev_index) {
  46         case 1:
  47                 host->base = TEGRA2_SDMMC3_BASE;
  48                 host->mmc_id = PERIPH_ID_SDMMC3;
  49                 break;
  50         case 2:
  51                 host->base = TEGRA2_SDMMC2_BASE;
  52                 host->mmc_id = PERIPH_ID_SDMMC2;
  53                 break;
  54         case 3:
  55                 host->base = TEGRA2_SDMMC1_BASE;
  56                 host->mmc_id = PERIPH_ID_SDMMC1;
  57                 break;
  58         case 0:
  59         default:
  60                 host->base = TEGRA2_SDMMC4_BASE;
  61                 host->mmc_id = PERIPH_ID_SDMMC4;
  62                 break;
  63         }
  64
  65         host->reg = (struct tegra2_mmc *)host->base;
  66 }
  67
  68 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
  69 {
  70         unsigned char ctrl;
  71
  72         debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
  73         (u32)data->dest, data->blocks, data->blocksize);
  74
  75         writel((u32)data->dest, &host->reg->sysad);
  76         /*
  77          * DMASEL[4:3]
  78          * 00 = Selects SDMA
  79          * 01 = Reserved
  80          * 10 = Selects 32-bit Address ADMA2
  81          * 11 = Selects 64-bit Address ADMA2
  82          */
  83         ctrl = readb(&host->reg->hostctl);
  84         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  85         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  86         writeb(ctrl, &host->reg->hostctl);
  87
  88         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  89         writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
  90         writew(data->blocks, &host->reg->blkcnt);
  91 }
  92
  93 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
  94 {
  95         unsigned short mode;
  96         debug(" mmc_set_transfer_mode called\n");
  97         /*
  98          * TRNMOD
  99          * MUL1SIN0[5]  : Multi/Single Block Select
 100          * RD1WT0[4]    : Data Transfer Direction Select
 101          *      1 = read
 102          *      0 = write
 103          * ENACMD12[2]  : Auto CMD12 Enable
 104          * ENBLKCNT[1]  : Block Count Enable
 105          * ENDMA[0]     : DMA Enable
 106          */
 107         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
 108                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
 109
 110         if (data->blocks > 1)
 111                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
 112
 113         if (data->flags & MMC_DATA_READ)
 114                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
 115
 116         writew(mode, &host->reg->trnmod);
 117 }
 118
 119 static int mmc_wait_inhibit(struct mmc_host *host,
 120                             struct mmc_cmd *cmd,
 121                             struct mmc_data *data,
 122                             unsigned int timeout)
 123 {
 124         /*
 125          * PRNSTS
 126          * CMDINHDAT[1] : Command Inhibit (DAT)
 127          * CMDINHCMD[0] : Command Inhibit (CMD)
 128          */
 129         unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
 130
 131         /*
 132          * We shouldn't wait for data inhibit for stop commands, even
 133          * though they might use busy signaling
 134          */
 135         if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
 136                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
 137
 138         while (readl(&host->reg->prnsts) & mask) {
 139                 if (timeout == 0) {
 140                         printf("%s: timeout error\n", __func__);
 141                         return -1;
 142                 }
 143                 timeout--;
 144                 udelay(1000);
 145         }
 146
 147         return 0;
 148 }
 149
 150 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 151                         struct mmc_data *data)
 152 {
 153         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 154         int flags, i;
 155         int result;
 156         unsigned int mask;
 157         unsigned int retry = 0x100000;
 158         debug(" mmc_send_cmd called\n");
 159
 160         result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
 161
 162         if (result < 0)
 163                 return result;
 164
 165         if (data)
 166                 mmc_prepare_data(host, data);
 167
 168         debug("cmd->arg: %08x\n", cmd->cmdarg);
 169         writel(cmd->cmdarg, &host->reg->argument);
 170
 171         if (data)
 172                 mmc_set_transfer_mode(host, data);
 173
 174         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 175                 return -1;
 176
 177         /*
 178          * CMDREG
 179          * CMDIDX[13:8] : Command index
 180          * DATAPRNT[5]  : Data Present Select
 181          * ENCMDIDX[4]  : Command Index Check Enable
 182          * ENCMDCRC[3]  : Command CRC Check Enable
 183          * RSPTYP[1:0]
 184          *      00 = No Response
 185          *      01 = Length 136
 186          *      10 = Length 48
 187          *      11 = Length 48 Check busy after response
 188          */
 189         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 190                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
 191         else if (cmd->resp_type & MMC_RSP_136)
 192                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
 193         else if (cmd->resp_type & MMC_RSP_BUSY)
 194                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
 195         else
 196                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
 197
 198         if (cmd->resp_type & MMC_RSP_CRC)
 199                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
 200         if (cmd->resp_type & MMC_RSP_OPCODE)
 201                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
 202         if (data)
 203                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
 204
 205         debug("cmd: %d\n", cmd->cmdidx);
 206
 207         writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
 208
 209         for (i = 0; i < retry; i++) {
 210                 mask = readl(&host->reg->norintsts);
 211                 /* Command Complete */
 212                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
 213                         if (!data)
 214                                 writel(mask, &host->reg->norintsts);
 215                         break;
 216                 }
 217         }
 218
 219         if (i == retry) {
 220                 printf("%s: waiting for status update\n", __func__);
 221                 return TIMEOUT;
 222         }
 223
 224         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
 225                 /* Timeout Error */
 226                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 227                 return TIMEOUT;
 228         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 229                 /* Error Interrupt */
 230                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 231                 return -1;
 232         }
 233
 234         if (cmd->resp_type & MMC_RSP_PRESENT) {
 235                 if (cmd->resp_type & MMC_RSP_136) {
 236                         /* CRC is stripped so we need to do some shifting. */
 237                         for (i = 0; i < 4; i++) {
 238                                 unsigned int offset =
 239                                         (unsigned int)(&host->reg->rspreg3 - i);
 240                                 cmd->response[i] = readl(offset) << 8;
 241
 242                                 if (i != 3) {
 243                                         cmd->response[i] |=
 244                                                 readb(offset - 1);
 245                                 }
 246                                 debug("cmd->resp[%d]: %08x\n",
 247                                                 i, cmd->response[i]);
 248                         }
 249                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 250                         for (i = 0; i < retry; i++) {
 251                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 252                                 if (readl(&host->reg->prnsts)
 253                                         & (1 << 20))    /* DAT[0] */
 254                                         break;
 255                         }
 256
 257                         if (i == retry) {
 258                                 printf("%s: card is still busy\n", __func__);
 259                                 return TIMEOUT;
 260                         }
 261
 262                         cmd->response[0] = readl(&host->reg->rspreg0);
 263                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 264                 } else {
 265                         cmd->response[0] = readl(&host->reg->rspreg0);
 266                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 267                 }
 268         }
 269
 270         if (data) {
 271                 unsigned long   start = get_timer(0);
 272
 273                 while (1) {
 274                         mask = readl(&host->reg->norintsts);
 275
 276                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 277                                 /* Error Interrupt */
 278                                 writel(mask, &host->reg->norintsts);
 279                                 printf("%s: error during transfer: 0x%08x\n",
 280                                                 __func__, mask);
 281                                 return -1;
 282                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
 283                                 /*
 284                                  * DMA Interrupt, restart the transfer where
 285                                  * it was interrupted.
 286                                  */
 287                                 unsigned int address = readl(&host->reg->sysad);
 288
 289                                 debug("DMA end\n");
 290                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
 291                                        &host->reg->norintsts);
 292                                 writel(address, &host->reg->sysad);
 293                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
 294                                 /* Transfer Complete */
 295                                 debug("r/w is done\n");
 296                                 break;
 297                         } else if (get_timer(start) > 2000UL) {
 298                                 writel(mask, &host->reg->norintsts);
 299                                 printf("%s: MMC Timeout\n"
 300                                        "    Interrupt status        0x%08x\n"
 301                                        "    Interrupt status enable 0x%08x\n"
 302                                        "    Interrupt signal enable 0x%08x\n"
 303                                        "    Present status          0x%08x\n",
 304                                        __func__, mask,
 305                                        readl(&host->reg->norintstsen),
 306                                        readl(&host->reg->norintsigen),
 307                                        readl(&host->reg->prnsts));
 308                                 return -1;
 309                         }
 310                 }
 311                 writel(mask, &host->reg->norintsts);
 312         }
 313
 314         udelay(1000);
 315         return 0;
 316 }
 317
 318 static void mmc_change_clock(struct mmc_host *host, uint clock)
 319 {
 320         int div;
 321         unsigned short clk;
 322         unsigned long timeout;
 323
 324         debug(" mmc_change_clock called\n");
 325
 326         /*
 327          * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
 328          * PLLP_OUT0
 329          */
 330         if (clock == 0)
 331                 goto out;
 332         clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
 333                                     &div);
 334         debug("div = %d\n", div);
 335
 336         writew(0, &host->reg->clkcon);
 337
 338         /*
 339          * CLKCON
 340          * SELFREQ[15:8]        : base clock divided by value
 341          * ENSDCLK[2]           : SD Clock Enable
 342          * STBLINTCLK[1]        : Internal Clock Stable
 343          * ENINTCLK[0]          : Internal Clock Enable
 344          */
 345         div >>= 1;
 346         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
 347                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
 348         writew(clk, &host->reg->clkcon);
 349
 350         /* Wait max 10 ms */
 351         timeout = 10;
 352         while (!(readw(&host->reg->clkcon) &
 353                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
 354                 if (timeout == 0) {
 355                         printf("%s: timeout error\n", __func__);
 356                         return;
 357                 }
 358                 timeout--;
 359                 udelay(1000);
 360         }
 361
 362         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 363         writew(clk, &host->reg->clkcon);
 364
 365         debug("mmc_change_clock: clkcon = %08X\n", clk);
 366
 367 out:
 368         host->clock = clock;
 369 }
 370
 371 static void mmc_set_ios(struct mmc *mmc)
 372 {
 373         struct mmc_host *host = mmc->priv;
 374         unsigned char ctrl;
 375         debug(" mmc_set_ios called\n");
 376
 377         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 378
 379         /* Change clock first */
 380         mmc_change_clock(host, mmc->clock);
 381
 382         ctrl = readb(&host->reg->hostctl);
 383
 384         /*
 385          * WIDE8[5]
 386          * 0 = Depend on WIDE4
 387          * 1 = 8-bit mode
 388          * WIDE4[1]
 389          * 1 = 4-bit mode
 390          * 0 = 1-bit mode
 391          */
 392         if (mmc->bus_width == 8)
 393                 ctrl |= (1 << 5);
 394         else if (mmc->bus_width == 4)
 395                 ctrl |= (1 << 1);
 396         else
 397                 ctrl &= ~(1 << 1);
 398
 399         writeb(ctrl, &host->reg->hostctl);
 400         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 401 }
 402
 403 static void mmc_reset(struct mmc_host *host)
 404 {
 405         unsigned int timeout;
 406         debug(" mmc_reset called\n");
 407
 408         /*
 409          * RSTALL[0] : Software reset for all
 410          * 1 = reset
 411          * 0 = work
 412          */
 413         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
 414
 415         host->clock = 0;
 416
 417         /* Wait max 100 ms */
 418         timeout = 100;
 419
 420         /* hw clears the bit when it's done */
 421         while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
 422                 if (timeout == 0) {
 423                         printf("%s: timeout error\n", __func__);
 424                         return;
 425                 }
 426                 timeout--;
 427                 udelay(1000);
 428         }
 429 }
 430
 431 static int mmc_core_init(struct mmc *mmc)
 432 {
 433         struct mmc_host *host = (struct mmc_host *)mmc->priv;
 434         unsigned int mask;
 435         debug(" mmc_core_init called\n");
 436
 437         mmc_reset(host);
 438
 439         host->version = readw(&host->reg->hcver);
 440         debug("host version = %x\n", host->version);
 441
 442         /* mask all */
 443         writel(0xffffffff, &host->reg->norintstsen);
 444         writel(0xffffffff, &host->reg->norintsigen);
 445
 446         writeb(0xe, &host->reg->timeoutcon);    /* TMCLK * 2^27 */
 447         /*
 448          * NORMAL Interrupt Status Enable Register init
 449          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 450          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 451          * [3] ENSTADMAINT   : DMA boundary interrupt
 452          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 453          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 454         */
 455         mask = readl(&host->reg->norintstsen);
 456         mask &= ~(0xffff);
 457         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
 458                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
 459                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
 460                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
 461                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
 462         writel(mask, &host->reg->norintstsen);
 463
 464         /*
 465          * NORMAL Interrupt Signal Enable Register init
 466          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 467          */
 468         mask = readl(&host->reg->norintsigen);
 469         mask &= ~(0xffff);
 470         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
 471         writel(mask, &host->reg->norintsigen);
 472
 473         return 0;
 474 }
 475
 476 static int tegra2_mmc_initialize(int dev_index, int bus_width)
 477 {
 478         struct mmc_host *host;
 479         struct mmc *mmc;
 480
 481         debug(" mmc_initialize called\n");
 482
 483         host = &mmc_host[dev_index];
 484
 485         host->clock = 0;
 486         tegra2_get_setup(host, dev_index);
 487
 488         clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 489
 490         mmc = &mmc_dev[dev_index];
 491
 492         sprintf(mmc->name, "Tegra2 SD/MMC");
 493         mmc->priv = host;
 494         mmc->send_cmd = mmc_send_cmd;
 495         mmc->set_ios = mmc_set_ios;
 496         mmc->init = mmc_core_init;
 497
 498         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 499         if (bus_width == 8)
 500                 mmc->host_caps = MMC_MODE_8BIT;
 501         else
 502                 mmc->host_caps = MMC_MODE_4BIT;
 503         mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
 504
 505         /*
 506          * min freq is for card identification, and is the highest
 507          *  low-speed SDIO card frequency (actually 400KHz)
 508          * max freq is highest HS eMMC clock as per the SD/MMC spec
 509          *  (actually 52MHz)
 510          * Both of these are the closest equivalents w/216MHz source
 511          *  clock and Tegra2 SDMMC divisors.
 512          */
 513         mmc->f_min = 375000;
 514         mmc->f_max = 48000000;
 515
 516         mmc_register(mmc);
 517
 518         return 0;
 519 }
 520
 521 int tegra2_mmc_init(int dev_index, int bus_width)
 522 {
 523         debug(" tegra2_mmc_init: index %d, bus width %d\n",
 524                 dev_index, bus_width);
 525         return tegra2_mmc_initialize(dev_index, bus_width);
 526 }