Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'
[karo-tx-uboot.git] / drivers / mtd / nand / atmel_nand.c
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
7  *
8  * Add Programmable Multibit ECC support for various AT91 SoC
9  *     (C) Copyright 2012 ATMEL, Hong Xu
10  *
11  * SPDX-License-Identifier:     GPL-2.0+
12  */
13
14 #include <common.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/at91_pio.h>
18
19 #include <malloc.h>
20 #include <nand.h>
21 #include <watchdog.h>
22
23 #ifdef CONFIG_ATMEL_NAND_HWECC
24
25 /* Register access macros */
26 #define ecc_readl(add, reg)                             \
27         readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
28 #define ecc_writel(add, reg, value)                     \
29         writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
30
31 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
32
33 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
34
35 struct atmel_nand_host {
36         struct pmecc_regs __iomem *pmecc;
37         struct pmecc_errloc_regs __iomem *pmerrloc;
38         void __iomem            *pmecc_rom_base;
39
40         u8              pmecc_corr_cap;
41         u16             pmecc_sector_size;
42         u32             pmecc_index_table_offset;
43
44         int             pmecc_bytes_per_sector;
45         int             pmecc_sector_number;
46         int             pmecc_degree;   /* Degree of remainders */
47         int             pmecc_cw_len;   /* Length of codeword */
48
49         /* lookup table for alpha_to and index_of */
50         void __iomem    *pmecc_alpha_to;
51         void __iomem    *pmecc_index_of;
52
53         /* data for pmecc computation */
54         int16_t *pmecc_smu;
55         int16_t *pmecc_partial_syn;
56         int16_t *pmecc_si;
57         int16_t *pmecc_lmu; /* polynomal order */
58         int     *pmecc_mu;
59         int     *pmecc_dmu;
60         int     *pmecc_delta;
61 };
62
63 static struct atmel_nand_host pmecc_host;
64 static struct nand_ecclayout atmel_pmecc_oobinfo;
65
66 /*
67  * Return number of ecc bytes per sector according to sector size and
68  * correction capability
69  *
70  * Following table shows what at91 PMECC supported:
71  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
72  * =====================        ================        =================
73  *                2-bits                 4-bytes                  4-bytes
74  *                4-bits                 7-bytes                  7-bytes
75  *                8-bits                13-bytes                 14-bytes
76  *               12-bits                20-bytes                 21-bytes
77  *               24-bits                39-bytes                 42-bytes
78  */
79 static int pmecc_get_ecc_bytes(int cap, int sector_size)
80 {
81         int m = 12 + sector_size / 512;
82         return (m * cap + 7) / 8;
83 }
84
85 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
86         int oobsize, int ecc_len)
87 {
88         int i;
89
90         layout->eccbytes = ecc_len;
91
92         /* ECC will occupy the last ecc_len bytes continuously */
93         for (i = 0; i < ecc_len; i++)
94                 layout->eccpos[i] = oobsize - ecc_len + i;
95
96         layout->oobfree[0].offset = 2;
97         layout->oobfree[0].length =
98                 oobsize - ecc_len - layout->oobfree[0].offset;
99 }
100
101 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
102 {
103         int table_size;
104
105         table_size = host->pmecc_sector_size == 512 ?
106                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
107
108         /* the ALPHA lookup table is right behind the INDEX lookup table. */
109         return host->pmecc_rom_base + host->pmecc_index_table_offset +
110                         table_size * sizeof(int16_t);
111 }
112
113 static void pmecc_data_free(struct atmel_nand_host *host)
114 {
115         free(host->pmecc_partial_syn);
116         free(host->pmecc_si);
117         free(host->pmecc_lmu);
118         free(host->pmecc_smu);
119         free(host->pmecc_mu);
120         free(host->pmecc_dmu);
121         free(host->pmecc_delta);
122 }
123
124 static int pmecc_data_alloc(struct atmel_nand_host *host)
125 {
126         const int cap = host->pmecc_corr_cap;
127         int size;
128
129         size = (2 * cap + 1) * sizeof(int16_t);
130         host->pmecc_partial_syn = malloc(size);
131         host->pmecc_si = malloc(size);
132         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
133         host->pmecc_smu = malloc((cap + 2) * size);
134
135         size = (cap + 1) * sizeof(int);
136         host->pmecc_mu = malloc(size);
137         host->pmecc_dmu = malloc(size);
138         host->pmecc_delta = malloc(size);
139
140         if (host->pmecc_partial_syn &&
141                         host->pmecc_si &&
142                         host->pmecc_lmu &&
143                         host->pmecc_smu &&
144                         host->pmecc_mu &&
145                         host->pmecc_dmu &&
146                         host->pmecc_delta)
147                 return 0;
148
149         /* error happened */
150         pmecc_data_free(host);
151         return -ENOMEM;
152
153 }
154
155 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
156 {
157         struct nand_chip *nand_chip = mtd->priv;
158         struct atmel_nand_host *host = nand_chip->priv;
159         int i;
160         uint32_t value;
161
162         /* Fill odd syndromes */
163         for (i = 0; i < host->pmecc_corr_cap; i++) {
164                 value = readl(&host->pmecc->rem_port[sector].rem[i / 2]);
165                 if (i & 1)
166                         value >>= 16;
167                 value &= 0xffff;
168                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
169         }
170 }
171
172 static void pmecc_substitute(struct mtd_info *mtd)
173 {
174         struct nand_chip *nand_chip = mtd->priv;
175         struct atmel_nand_host *host = nand_chip->priv;
176         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
177         int16_t __iomem *index_of = host->pmecc_index_of;
178         int16_t *partial_syn = host->pmecc_partial_syn;
179         const int cap = host->pmecc_corr_cap;
180         int16_t *si;
181         int i, j;
182
183         /* si[] is a table that holds the current syndrome value,
184          * an element of that table belongs to the field
185          */
186         si = host->pmecc_si;
187
188         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
189
190         /* Computation 2t syndromes based on S(x) */
191         /* Odd syndromes */
192         for (i = 1; i < 2 * cap; i += 2) {
193                 for (j = 0; j < host->pmecc_degree; j++) {
194                         if (partial_syn[i] & (0x1 << j))
195                                 si[i] = readw(alpha_to + i * j) ^ si[i];
196                 }
197         }
198         /* Even syndrome = (Odd syndrome) ** 2 */
199         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
200                 if (si[j] == 0) {
201                         si[i] = 0;
202                 } else {
203                         int16_t tmp;
204
205                         tmp = readw(index_of + si[j]);
206                         tmp = (tmp * 2) % host->pmecc_cw_len;
207                         si[i] = readw(alpha_to + tmp);
208                 }
209         }
210 }
211
212 /*
213  * This function defines a Berlekamp iterative procedure for
214  * finding the value of the error location polynomial.
215  * The input is si[], initialize by pmecc_substitute().
216  * The output is smu[][].
217  *
218  * This function is written according to chip datasheet Chapter:
219  * Find the Error Location Polynomial Sigma(x) of Section:
220  * Programmable Multibit ECC Control (PMECC).
221  */
222 static void pmecc_get_sigma(struct mtd_info *mtd)
223 {
224         struct nand_chip *nand_chip = mtd->priv;
225         struct atmel_nand_host *host = nand_chip->priv;
226
227         int16_t *lmu = host->pmecc_lmu;
228         int16_t *si = host->pmecc_si;
229         int *mu = host->pmecc_mu;
230         int *dmu = host->pmecc_dmu;     /* Discrepancy */
231         int *delta = host->pmecc_delta; /* Delta order */
232         int cw_len = host->pmecc_cw_len;
233         const int16_t cap = host->pmecc_corr_cap;
234         const int num = 2 * cap + 1;
235         int16_t __iomem *index_of = host->pmecc_index_of;
236         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
237         int i, j, k;
238         uint32_t dmu_0_count, tmp;
239         int16_t *smu = host->pmecc_smu;
240
241         /* index of largest delta */
242         int ro;
243         int largest;
244         int diff;
245
246         /* Init the Sigma(x) */
247         memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
248
249         dmu_0_count = 0;
250
251         /* First Row */
252
253         /* Mu */
254         mu[0] = -1;
255
256         smu[0] = 1;
257
258         /* discrepancy set to 1 */
259         dmu[0] = 1;
260         /* polynom order set to 0 */
261         lmu[0] = 0;
262         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
263         delta[0] = -1;
264
265         /* Second Row */
266
267         /* Mu */
268         mu[1] = 0;
269         /* Sigma(x) set to 1 */
270         smu[num] = 1;
271
272         /* discrepancy set to S1 */
273         dmu[1] = si[1];
274
275         /* polynom order set to 0 */
276         lmu[1] = 0;
277
278         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
279         delta[1] = 0;
280
281         for (i = 1; i <= cap; i++) {
282                 mu[i + 1] = i << 1;
283                 /* Begin Computing Sigma (Mu+1) and L(mu) */
284                 /* check if discrepancy is set to 0 */
285                 if (dmu[i] == 0) {
286                         dmu_0_count++;
287
288                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
289                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
290                                 tmp += 2;
291                         else
292                                 tmp += 1;
293
294                         if (dmu_0_count == tmp) {
295                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
296                                         smu[(cap + 1) * num + j] =
297                                                         smu[i * num + j];
298
299                                 lmu[cap + 1] = lmu[i];
300                                 return;
301                         }
302
303                         /* copy polynom */
304                         for (j = 0; j <= lmu[i] >> 1; j++)
305                                 smu[(i + 1) * num + j] = smu[i * num + j];
306
307                         /* copy previous polynom order to the next */
308                         lmu[i + 1] = lmu[i];
309                 } else {
310                         ro = 0;
311                         largest = -1;
312                         /* find largest delta with dmu != 0 */
313                         for (j = 0; j < i; j++) {
314                                 if ((dmu[j]) && (delta[j] > largest)) {
315                                         largest = delta[j];
316                                         ro = j;
317                                 }
318                         }
319
320                         /* compute difference */
321                         diff = (mu[i] - mu[ro]);
322
323                         /* Compute degree of the new smu polynomial */
324                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
325                                 lmu[i + 1] = lmu[i];
326                         else
327                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
328
329                         /* Init smu[i+1] with 0 */
330                         for (k = 0; k < num; k++)
331                                 smu[(i + 1) * num + k] = 0;
332
333                         /* Compute smu[i+1] */
334                         for (k = 0; k <= lmu[ro] >> 1; k++) {
335                                 int16_t a, b, c;
336
337                                 if (!(smu[ro * num + k] && dmu[i]))
338                                         continue;
339                                 a = readw(index_of + dmu[i]);
340                                 b = readw(index_of + dmu[ro]);
341                                 c = readw(index_of + smu[ro * num + k]);
342                                 tmp = a + (cw_len - b) + c;
343                                 a = readw(alpha_to + tmp % cw_len);
344                                 smu[(i + 1) * num + (k + diff)] = a;
345                         }
346
347                         for (k = 0; k <= lmu[i] >> 1; k++)
348                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
349                 }
350
351                 /* End Computing Sigma (Mu+1) and L(mu) */
352                 /* In either case compute delta */
353                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
354
355                 /* Do not compute discrepancy for the last iteration */
356                 if (i >= cap)
357                         continue;
358
359                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
360                         tmp = 2 * (i - 1);
361                         if (k == 0) {
362                                 dmu[i + 1] = si[tmp + 3];
363                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
364                                 int16_t a, b, c;
365                                 a = readw(index_of +
366                                                 smu[(i + 1) * num + k]);
367                                 b = si[2 * (i - 1) + 3 - k];
368                                 c = readw(index_of + b);
369                                 tmp = a + c;
370                                 tmp %= cw_len;
371                                 dmu[i + 1] = readw(alpha_to + tmp) ^
372                                         dmu[i + 1];
373                         }
374                 }
375         }
376 }
377
378 static int pmecc_err_location(struct mtd_info *mtd)
379 {
380         struct nand_chip *nand_chip = mtd->priv;
381         struct atmel_nand_host *host = nand_chip->priv;
382         const int cap = host->pmecc_corr_cap;
383         const int num = 2 * cap + 1;
384         int sector_size = host->pmecc_sector_size;
385         int err_nbr = 0;        /* number of error */
386         int roots_nbr;          /* number of roots */
387         int i;
388         uint32_t val;
389         int16_t *smu = host->pmecc_smu;
390         int timeout = PMECC_MAX_TIMEOUT_US;
391
392         writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis);
393
394         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
395                 writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]);
396                 err_nbr++;
397         }
398
399         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
400         if (sector_size == 1024)
401                 val |= PMERRLOC_ELCFG_SECTOR_1024;
402
403         writel(val, &host->pmerrloc->elcfg);
404         writel(sector_size * 8 + host->pmecc_degree * cap,
405                         &host->pmerrloc->elen);
406
407         while (--timeout) {
408                 if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE)
409                         break;
410                 WATCHDOG_RESET();
411                 udelay(1);
412         }
413
414         if (!timeout) {
415                 printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n");
416                 return -1;
417         }
418
419         roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK)
420                         >> 8;
421         /* Number of roots == degree of smu hence <= cap */
422         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
423                 return err_nbr - 1;
424
425         /* Number of roots does not match the degree of smu
426          * unable to correct error */
427         return -1;
428 }
429
430 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
431                 int sector_num, int extra_bytes, int err_nbr)
432 {
433         struct nand_chip *nand_chip = mtd->priv;
434         struct atmel_nand_host *host = nand_chip->priv;
435         int i = 0;
436         int byte_pos, bit_pos, sector_size, pos;
437         uint32_t tmp;
438         uint8_t err_byte;
439
440         sector_size = host->pmecc_sector_size;
441
442         while (err_nbr) {
443                 tmp = readl(&host->pmerrloc->el[i]) - 1;
444                 byte_pos = tmp / 8;
445                 bit_pos  = tmp % 8;
446
447                 if (byte_pos >= (sector_size + extra_bytes))
448                         BUG();  /* should never happen */
449
450                 if (byte_pos < sector_size) {
451                         err_byte = *(buf + byte_pos);
452                         *(buf + byte_pos) ^= (1 << bit_pos);
453
454                         pos = sector_num * host->pmecc_sector_size + byte_pos;
455                         printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
456                                 pos, bit_pos, err_byte, *(buf + byte_pos));
457                 } else {
458                         /* Bit flip in OOB area */
459                         tmp = sector_num * host->pmecc_bytes_per_sector
460                                         + (byte_pos - sector_size);
461                         err_byte = ecc[tmp];
462                         ecc[tmp] ^= (1 << bit_pos);
463
464                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
465                         printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
466                                 pos, bit_pos, err_byte, ecc[tmp]);
467                 }
468
469                 i++;
470                 err_nbr--;
471         }
472
473         return;
474 }
475
476 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
477         u8 *ecc)
478 {
479         struct nand_chip *nand_chip = mtd->priv;
480         struct atmel_nand_host *host = nand_chip->priv;
481         int i, err_nbr, eccbytes;
482         uint8_t *buf_pos;
483
484         eccbytes = nand_chip->ecc.bytes;
485         for (i = 0; i < eccbytes; i++)
486                 if (ecc[i] != 0xff)
487                         goto normal_check;
488         /* Erased page, return OK */
489         return 0;
490
491 normal_check:
492         for (i = 0; i < host->pmecc_sector_number; i++) {
493                 err_nbr = 0;
494                 if (pmecc_stat & 0x1) {
495                         buf_pos = buf + i * host->pmecc_sector_size;
496
497                         pmecc_gen_syndrome(mtd, i);
498                         pmecc_substitute(mtd);
499                         pmecc_get_sigma(mtd);
500
501                         err_nbr = pmecc_err_location(mtd);
502                         if (err_nbr == -1) {
503                                 printk(KERN_ERR "PMECC: Too many errors\n");
504                                 mtd->ecc_stats.failed++;
505                                 return -EIO;
506                         } else {
507                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
508                                         host->pmecc_bytes_per_sector, err_nbr);
509                                 mtd->ecc_stats.corrected += err_nbr;
510                         }
511                 }
512                 pmecc_stat >>= 1;
513         }
514
515         return 0;
516 }
517
518 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
519         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
520 {
521         struct atmel_nand_host *host = chip->priv;
522         int eccsize = chip->ecc.size;
523         uint8_t *oob = chip->oob_poi;
524         uint32_t *eccpos = chip->ecc.layout->eccpos;
525         uint32_t stat;
526         int timeout = PMECC_MAX_TIMEOUT_US;
527
528         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
529         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
530         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
531                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
532
533         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
534         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
535
536         chip->read_buf(mtd, buf, eccsize);
537         chip->read_buf(mtd, oob, mtd->oobsize);
538
539         while (--timeout) {
540                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
541                         break;
542                 WATCHDOG_RESET();
543                 udelay(1);
544         }
545
546         if (!timeout) {
547                 printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n");
548                 return -1;
549         }
550
551         stat = pmecc_readl(host->pmecc, isr);
552         if (stat != 0)
553                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
554                         return -EIO;
555
556         return 0;
557 }
558
559 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
560                 struct nand_chip *chip, const uint8_t *buf,
561                 int oob_required)
562 {
563         struct atmel_nand_host *host = chip->priv;
564         uint32_t *eccpos = chip->ecc.layout->eccpos;
565         int i, j;
566         int timeout = PMECC_MAX_TIMEOUT_US;
567
568         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
569         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
570
571         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
572                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
573
574         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
575         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
576
577         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
578
579         while (--timeout) {
580                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
581                         break;
582                 WATCHDOG_RESET();
583                 udelay(1);
584         }
585
586         if (!timeout) {
587                 printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
588                 goto out;
589         }
590
591         for (i = 0; i < host->pmecc_sector_number; i++) {
592                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
593                         int pos;
594
595                         pos = i * host->pmecc_bytes_per_sector + j;
596                         chip->oob_poi[eccpos[pos]] =
597                                 readb(&host->pmecc->ecc_port[i].ecc[j]);
598                 }
599         }
600         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
601 out:
602         return 0;
603 }
604
605 static void atmel_pmecc_core_init(struct mtd_info *mtd)
606 {
607         struct nand_chip *nand_chip = mtd->priv;
608         struct atmel_nand_host *host = nand_chip->priv;
609         uint32_t val = 0;
610         struct nand_ecclayout *ecc_layout;
611
612         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
613         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
614
615         switch (host->pmecc_corr_cap) {
616         case 2:
617                 val = PMECC_CFG_BCH_ERR2;
618                 break;
619         case 4:
620                 val = PMECC_CFG_BCH_ERR4;
621                 break;
622         case 8:
623                 val = PMECC_CFG_BCH_ERR8;
624                 break;
625         case 12:
626                 val = PMECC_CFG_BCH_ERR12;
627                 break;
628         case 24:
629                 val = PMECC_CFG_BCH_ERR24;
630                 break;
631         }
632
633         if (host->pmecc_sector_size == 512)
634                 val |= PMECC_CFG_SECTOR512;
635         else if (host->pmecc_sector_size == 1024)
636                 val |= PMECC_CFG_SECTOR1024;
637
638         switch (host->pmecc_sector_number) {
639         case 1:
640                 val |= PMECC_CFG_PAGE_1SECTOR;
641                 break;
642         case 2:
643                 val |= PMECC_CFG_PAGE_2SECTORS;
644                 break;
645         case 4:
646                 val |= PMECC_CFG_PAGE_4SECTORS;
647                 break;
648         case 8:
649                 val |= PMECC_CFG_PAGE_8SECTORS;
650                 break;
651         }
652
653         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
654                 | PMECC_CFG_AUTO_DISABLE);
655         pmecc_writel(host->pmecc, cfg, val);
656
657         ecc_layout = nand_chip->ecc.layout;
658         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
659         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
660         pmecc_writel(host->pmecc, eaddr,
661                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
662         /* See datasheet about PMECC Clock Control Register */
663         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
664         pmecc_writel(host->pmecc, idr, 0xff);
665         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
666 }
667
668 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
669 /*
670  * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
671  * @ecc_bits: store the ONFI ECC correct bits capbility
672  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
673  *
674  * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
675  * @sector_size are initialize to 0.
676  * Return 0 if success to get the ECC requirement.
677  */
678 static int get_onfi_ecc_param(struct nand_chip *chip,
679                 int *ecc_bits, int *sector_size)
680 {
681         *ecc_bits = *sector_size = 0;
682
683         if (chip->onfi_params.ecc_bits == 0xff)
684                 /* TODO: the sector_size and ecc_bits need to be find in
685                  * extended ecc parameter, currently we don't support it.
686                  */
687                 return -1;
688
689         *ecc_bits = chip->onfi_params.ecc_bits;
690
691         /* The default sector size (ecc codeword size) is 512 */
692         *sector_size = 512;
693
694         return 0;
695 }
696
697 /*
698  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
699  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
700  *                    ONFI ECC parameters.
701  * @host: point to an atmel_nand_host structure.
702  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
703  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
704  * @chip: point to an nand_chip structure.
705  * @cap: store the ONFI ECC correct bits capbility
706  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
707  *
708  * Return 0 if success. otherwise return the error code.
709  */
710 static int pmecc_choose_ecc(struct atmel_nand_host *host,
711                 struct nand_chip *chip,
712                 int *cap, int *sector_size)
713 {
714         /* Get ECC requirement from ONFI parameters */
715         *cap = *sector_size = 0;
716         if (chip->onfi_version) {
717                 if (!get_onfi_ecc_param(chip, cap, sector_size)) {
718                         MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
719                                 *cap, *sector_size);
720                 } else {
721                         dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
722                 }
723         } else {
724                 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
725         }
726         if (*cap == 0 && *sector_size == 0) {
727                 /* Non-ONFI compliant or use extended ONFI parameters */
728                 *cap = 2;
729                 *sector_size = 512;
730         }
731
732         /* If head file doesn't specify then use the one in ONFI parameters */
733         if (host->pmecc_corr_cap == 0) {
734                 /* use the most fitable ecc bits (the near bigger one ) */
735                 if (*cap <= 2)
736                         host->pmecc_corr_cap = 2;
737                 else if (*cap <= 4)
738                         host->pmecc_corr_cap = 4;
739                 else if (*cap <= 8)
740                         host->pmecc_corr_cap = 8;
741                 else if (*cap <= 12)
742                         host->pmecc_corr_cap = 12;
743                 else if (*cap <= 24)
744                         host->pmecc_corr_cap = 24;
745                 else
746                         return -EINVAL;
747         }
748         if (host->pmecc_sector_size == 0) {
749                 /* use the most fitable sector size (the near smaller one ) */
750                 if (*sector_size >= 1024)
751                         host->pmecc_sector_size = 1024;
752                 else if (*sector_size >= 512)
753                         host->pmecc_sector_size = 512;
754                 else
755                         return -EINVAL;
756         }
757         return 0;
758 }
759 #endif
760
761 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
762                 struct mtd_info *mtd)
763 {
764         struct atmel_nand_host *host;
765         int cap, sector_size;
766
767         host = nand->priv = &pmecc_host;
768
769         nand->ecc.mode = NAND_ECC_HW;
770         nand->ecc.calculate = NULL;
771         nand->ecc.correct = NULL;
772         nand->ecc.hwctl = NULL;
773
774 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
775         host->pmecc_corr_cap = host->pmecc_sector_size = 0;
776
777 #ifdef CONFIG_PMECC_CAP
778         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
779 #endif
780 #ifdef CONFIG_PMECC_SECTOR_SIZE
781         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
782 #endif
783         /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
784          * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
785          * from ONFI.
786          */
787         if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
788                 dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
789                                 cap, sector_size);
790                 return -EINVAL;
791         }
792
793         if (cap > host->pmecc_corr_cap)
794                 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
795                                 host->pmecc_corr_cap, cap);
796         if (sector_size < host->pmecc_sector_size)
797                 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
798                                 host->pmecc_sector_size, sector_size);
799 #else   /* CONFIG_SYS_NAND_ONFI_DETECTION */
800         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
801         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
802 #endif
803
804         cap = host->pmecc_corr_cap;
805         sector_size = host->pmecc_sector_size;
806
807         /* TODO: need check whether cap & sector_size is validate */
808
809         if (host->pmecc_sector_size == 512)
810                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
811         else
812                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
813
814         MTDDEBUG(MTD_DEBUG_LEVEL1,
815                 "Initialize PMECC params, cap: %d, sector: %d\n",
816                 cap, sector_size);
817
818         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
819         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
820                         ATMEL_BASE_PMERRLOC;
821         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
822
823         /* ECC is calculated for the whole page (1 step) */
824         nand->ecc.size = mtd->writesize;
825
826         /* set ECC page size and oob layout */
827         switch (mtd->writesize) {
828         case 2048:
829         case 4096:
830                 host->pmecc_degree = PMECC_GF_DIMENSION_13;
831                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
832                 host->pmecc_sector_number = mtd->writesize / sector_size;
833                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
834                         cap, sector_size);
835                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
836                 host->pmecc_index_of = host->pmecc_rom_base +
837                         host->pmecc_index_table_offset;
838
839                 nand->ecc.steps = 1;
840                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
841                                        host->pmecc_sector_number;
842                 if (nand->ecc.bytes > mtd->oobsize - 2) {
843                         printk(KERN_ERR "No room for ECC bytes\n");
844                         return -EINVAL;
845                 }
846                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
847                                         mtd->oobsize,
848                                         nand->ecc.bytes);
849                 nand->ecc.layout = &atmel_pmecc_oobinfo;
850                 break;
851         case 512:
852         case 1024:
853                 /* TODO */
854                 printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n");
855         default:
856                 /* page size not handled by HW ECC */
857                 /* switching back to soft ECC */
858                 nand->ecc.mode = NAND_ECC_SOFT;
859                 nand->ecc.read_page = NULL;
860                 nand->ecc.postpad = 0;
861                 nand->ecc.prepad = 0;
862                 nand->ecc.bytes = 0;
863                 return 0;
864         }
865
866         /* Allocate data for PMECC computation */
867         if (pmecc_data_alloc(host)) {
868                 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
869                 return -ENOMEM;
870         }
871
872         nand->ecc.read_page = atmel_nand_pmecc_read_page;
873         nand->ecc.write_page = atmel_nand_pmecc_write_page;
874         nand->ecc.strength = cap;
875
876         atmel_pmecc_core_init(mtd);
877
878         return 0;
879 }
880
881 #else
882
883 /* oob layout for large page size
884  * bad block info is on bytes 0 and 1
885  * the bytes have to be consecutives to avoid
886  * several NAND_CMD_RNDOUT during read
887  */
888 static struct nand_ecclayout atmel_oobinfo_large = {
889         .eccbytes = 4,
890         .eccpos = {60, 61, 62, 63},
891         .oobfree = {
892                 {2, 58}
893         },
894 };
895
896 /* oob layout for small page size
897  * bad block info is on bytes 4 and 5
898  * the bytes have to be consecutives to avoid
899  * several NAND_CMD_RNDOUT during read
900  */
901 static struct nand_ecclayout atmel_oobinfo_small = {
902         .eccbytes = 4,
903         .eccpos = {0, 1, 2, 3},
904         .oobfree = {
905                 {6, 10}
906         },
907 };
908
909 /*
910  * Calculate HW ECC
911  *
912  * function called after a write
913  *
914  * mtd:        MTD block structure
915  * dat:        raw data (unused)
916  * ecc_code:   buffer for ECC
917  */
918 static int atmel_nand_calculate(struct mtd_info *mtd,
919                 const u_char *dat, unsigned char *ecc_code)
920 {
921         unsigned int ecc_value;
922
923         /* get the first 2 ECC bytes */
924         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
925
926         ecc_code[0] = ecc_value & 0xFF;
927         ecc_code[1] = (ecc_value >> 8) & 0xFF;
928
929         /* get the last 2 ECC bytes */
930         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
931
932         ecc_code[2] = ecc_value & 0xFF;
933         ecc_code[3] = (ecc_value >> 8) & 0xFF;
934
935         return 0;
936 }
937
938 /*
939  * HW ECC read page function
940  *
941  * mtd:        mtd info structure
942  * chip:       nand chip info structure
943  * buf:        buffer to store read data
944  * oob_required:    caller expects OOB data read to chip->oob_poi
945  */
946 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
947                                 uint8_t *buf, int oob_required, int page)
948 {
949         int eccsize = chip->ecc.size;
950         int eccbytes = chip->ecc.bytes;
951         uint32_t *eccpos = chip->ecc.layout->eccpos;
952         uint8_t *p = buf;
953         uint8_t *oob = chip->oob_poi;
954         uint8_t *ecc_pos;
955         int stat;
956
957         /* read the page */
958         chip->read_buf(mtd, p, eccsize);
959
960         /* move to ECC position if needed */
961         if (eccpos[0] != 0) {
962                 /* This only works on large pages
963                  * because the ECC controller waits for
964                  * NAND_CMD_RNDOUTSTART after the
965                  * NAND_CMD_RNDOUT.
966                  * anyway, for small pages, the eccpos[0] == 0
967                  */
968                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
969                                 mtd->writesize + eccpos[0], -1);
970         }
971
972         /* the ECC controller needs to read the ECC just after the data */
973         ecc_pos = oob + eccpos[0];
974         chip->read_buf(mtd, ecc_pos, eccbytes);
975
976         /* check if there's an error */
977         stat = chip->ecc.correct(mtd, p, oob, NULL);
978
979         if (stat < 0)
980                 mtd->ecc_stats.failed++;
981         else
982                 mtd->ecc_stats.corrected += stat;
983
984         /* get back to oob start (end of page) */
985         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
986
987         /* read the oob */
988         chip->read_buf(mtd, oob, mtd->oobsize);
989
990         return 0;
991 }
992
993 /*
994  * HW ECC Correction
995  *
996  * function called after a read
997  *
998  * mtd:        MTD block structure
999  * dat:        raw data read from the chip
1000  * read_ecc:   ECC from the chip (unused)
1001  * isnull:     unused
1002  *
1003  * Detect and correct a 1 bit error for a page
1004  */
1005 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1006                 u_char *read_ecc, u_char *isnull)
1007 {
1008         struct nand_chip *nand_chip = mtd->priv;
1009         unsigned int ecc_status;
1010         unsigned int ecc_word, ecc_bit;
1011
1012         /* get the status from the Status Register */
1013         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1014
1015         /* if there's no error */
1016         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1017                 return 0;
1018
1019         /* get error bit offset (4 bits) */
1020         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1021         /* get word address (12 bits) */
1022         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1023         ecc_word >>= 4;
1024
1025         /* if there are multiple errors */
1026         if (ecc_status & ATMEL_ECC_MULERR) {
1027                 /* check if it is a freshly erased block
1028                  * (filled with 0xff) */
1029                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1030                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1031                         /* the block has just been erased, return OK */
1032                         return 0;
1033                 }
1034                 /* it doesn't seems to be a freshly
1035                  * erased block.
1036                  * We can't correct so many errors */
1037                 printk(KERN_WARNING "atmel_nand : multiple errors detected."
1038                                 " Unable to correct.\n");
1039                 return -EIO;
1040         }
1041
1042         /* if there's a single bit error : we can correct it */
1043         if (ecc_status & ATMEL_ECC_ECCERR) {
1044                 /* there's nothing much to do here.
1045                  * the bit error is on the ECC itself.
1046                  */
1047                 printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
1048                                 " Nothing to correct\n");
1049                 return 0;
1050         }
1051
1052         printk(KERN_WARNING "atmel_nand : one bit error on data."
1053                         " (word offset in the page :"
1054                         " 0x%x bit offset : 0x%x)\n",
1055                         ecc_word, ecc_bit);
1056         /* correct the error */
1057         if (nand_chip->options & NAND_BUSWIDTH_16) {
1058                 /* 16 bits words */
1059                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1060         } else {
1061                 /* 8 bits words */
1062                 dat[ecc_word] ^= (1 << ecc_bit);
1063         }
1064         printk(KERN_WARNING "atmel_nand : error corrected\n");
1065         return 1;
1066 }
1067
1068 /*
1069  * Enable HW ECC : unused on most chips
1070  */
1071 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1072 {
1073 }
1074
1075 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1076 {
1077         nand->ecc.mode = NAND_ECC_HW;
1078         nand->ecc.calculate = atmel_nand_calculate;
1079         nand->ecc.correct = atmel_nand_correct;
1080         nand->ecc.hwctl = atmel_nand_hwctl;
1081         nand->ecc.read_page = atmel_nand_read_page;
1082         nand->ecc.bytes = 4;
1083
1084         if (nand->ecc.mode == NAND_ECC_HW) {
1085                 /* ECC is calculated for the whole page (1 step) */
1086                 nand->ecc.size = mtd->writesize;
1087
1088                 /* set ECC page size and oob layout */
1089                 switch (mtd->writesize) {
1090                 case 512:
1091                         nand->ecc.layout = &atmel_oobinfo_small;
1092                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1093                                         ATMEL_ECC_PAGESIZE_528);
1094                         break;
1095                 case 1024:
1096                         nand->ecc.layout = &atmel_oobinfo_large;
1097                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1098                                         ATMEL_ECC_PAGESIZE_1056);
1099                         break;
1100                 case 2048:
1101                         nand->ecc.layout = &atmel_oobinfo_large;
1102                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1103                                         ATMEL_ECC_PAGESIZE_2112);
1104                         break;
1105                 case 4096:
1106                         nand->ecc.layout = &atmel_oobinfo_large;
1107                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1108                                         ATMEL_ECC_PAGESIZE_4224);
1109                         break;
1110                 default:
1111                         /* page size not handled by HW ECC */
1112                         /* switching back to soft ECC */
1113                         nand->ecc.mode = NAND_ECC_SOFT;
1114                         nand->ecc.calculate = NULL;
1115                         nand->ecc.correct = NULL;
1116                         nand->ecc.hwctl = NULL;
1117                         nand->ecc.read_page = NULL;
1118                         nand->ecc.postpad = 0;
1119                         nand->ecc.prepad = 0;
1120                         nand->ecc.bytes = 0;
1121                         break;
1122                 }
1123         }
1124
1125         return 0;
1126 }
1127
1128 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1129
1130 #endif /* CONFIG_ATMEL_NAND_HWECC */
1131
1132 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1133                                          int cmd, unsigned int ctrl)
1134 {
1135         struct nand_chip *this = mtd->priv;
1136
1137         if (ctrl & NAND_CTRL_CHANGE) {
1138                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1139                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1140                              | CONFIG_SYS_NAND_MASK_CLE);
1141
1142                 if (ctrl & NAND_CLE)
1143                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1144                 if (ctrl & NAND_ALE)
1145                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1146
1147 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1148                 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1149                                     !(ctrl & NAND_NCE));
1150 #endif
1151                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1152         }
1153
1154         if (cmd != NAND_CMD_NONE)
1155                 writeb(cmd, this->IO_ADDR_W);
1156 }
1157
1158 #ifdef CONFIG_SYS_NAND_READY_PIN
1159 static int at91_nand_ready(struct mtd_info *mtd)
1160 {
1161         return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1162 }
1163 #endif
1164
1165 #ifndef CONFIG_SYS_NAND_BASE_LIST
1166 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1167 #endif
1168 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1169 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1170
1171 int atmel_nand_chip_init(int devnum, ulong base_addr)
1172 {
1173         int ret;
1174         struct mtd_info *mtd = &nand_info[devnum];
1175         struct nand_chip *nand = &nand_chip[devnum];
1176
1177         mtd->priv = nand;
1178         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1179
1180         nand->ecc.mode = NAND_ECC_SOFT;
1181 #ifdef CONFIG_SYS_NAND_DBW_16
1182         nand->options = NAND_BUSWIDTH_16;
1183 #endif
1184         nand->cmd_ctrl = at91_nand_hwcontrol;
1185 #ifdef CONFIG_SYS_NAND_READY_PIN
1186         nand->dev_ready = at91_nand_ready;
1187 #endif
1188         nand->chip_delay = 20;
1189
1190         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1191         if (ret)
1192                 return ret;
1193
1194 #ifdef CONFIG_ATMEL_NAND_HWECC
1195 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1196         ret = atmel_pmecc_nand_init_params(nand, mtd);
1197 #else
1198         ret = atmel_hwecc_nand_init_param(nand, mtd);
1199 #endif
1200         if (ret)
1201                 return ret;
1202 #endif
1203
1204         ret = nand_scan_tail(mtd);
1205         if (!ret)
1206                 nand_register(devnum);
1207
1208         return ret;
1209 }
1210
1211 void board_nand_init(void)
1212 {
1213         int i;
1214         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1215                 if (atmel_nand_chip_init(i, base_addr[i]))
1216                         printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip",
1217                                 i);
1218 }