drivers/mtd/nand/atmel_nand.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
   7  *
   8  * Add Programmable Multibit ECC support for various AT91 SoC
   9  *     (C) Copyright 2012 ATMEL, Hong Xu
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/gpio.h>
  17
  18 #include <malloc.h>
  19 #include <nand.h>
  20 #include <watchdog.h>
  21
  22 #ifdef CONFIG_ATMEL_NAND_HWECC
  23
  24 /* Register access macros */
  25 #define ecc_readl(add, reg)                             \
  26         readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
  27 #define ecc_writel(add, reg, value)                     \
  28         writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
  29
  30 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  31
  32 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  33
  34 struct atmel_nand_host {
  35         struct pmecc_regs __iomem *pmecc;
  36         struct pmecc_errloc_regs __iomem *pmerrloc;
  37         void __iomem            *pmecc_rom_base;
  38
  39         u8              pmecc_corr_cap;
  40         u16             pmecc_sector_size;
  41         u32             pmecc_index_table_offset;
  42
  43         int             pmecc_bytes_per_sector;
  44         int             pmecc_sector_number;
  45         int             pmecc_degree;   /* Degree of remainders */
  46         int             pmecc_cw_len;   /* Length of codeword */
  47
  48         /* lookup table for alpha_to and index_of */
  49         void __iomem    *pmecc_alpha_to;
  50         void __iomem    *pmecc_index_of;
  51
  52         /* data for pmecc computation */
  53         int16_t *pmecc_smu;
  54         int16_t *pmecc_partial_syn;
  55         int16_t *pmecc_si;
  56         int16_t *pmecc_lmu; /* polynomal order */
  57         int     *pmecc_mu;
  58         int     *pmecc_dmu;
  59         int     *pmecc_delta;
  60 };
  61
  62 static struct atmel_nand_host pmecc_host;
  63 static struct nand_ecclayout atmel_pmecc_oobinfo;
  64
  65 /*
  66  * Return number of ecc bytes per sector according to sector size and
  67  * correction capability
  68  *
  69  * Following table shows what at91 PMECC supported:
  70  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
  71  * =====================        ================        =================
  72  *                2-bits                 4-bytes                  4-bytes
  73  *                4-bits                 7-bytes                  7-bytes
  74  *                8-bits                13-bytes                 14-bytes
  75  *               12-bits                20-bytes                 21-bytes
  76  *               24-bits                39-bytes                 42-bytes
  77  */
  78 static int pmecc_get_ecc_bytes(int cap, int sector_size)
  79 {
  80         int m = 12 + sector_size / 512;
  81         return (m * cap + 7) / 8;
  82 }
  83
  84 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  85         int oobsize, int ecc_len)
  86 {
  87         int i;
  88
  89         layout->eccbytes = ecc_len;
  90
  91         /* ECC will occupy the last ecc_len bytes continuously */
  92         for (i = 0; i < ecc_len; i++)
  93                 layout->eccpos[i] = oobsize - ecc_len + i;
  94
  95         layout->oobfree[0].offset = 2;
  96         layout->oobfree[0].length =
  97                 oobsize - ecc_len - layout->oobfree[0].offset;
  98 }
  99
 100 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 101 {
 102         int table_size;
 103
 104         table_size = host->pmecc_sector_size == 512 ?
 105                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
 106
 107         /* the ALPHA lookup table is right behind the INDEX lookup table. */
 108         return host->pmecc_rom_base + host->pmecc_index_table_offset +
 109                         table_size * sizeof(int16_t);
 110 }
 111
 112 static void pmecc_data_free(struct atmel_nand_host *host)
 113 {
 114         free(host->pmecc_partial_syn);
 115         free(host->pmecc_si);
 116         free(host->pmecc_lmu);
 117         free(host->pmecc_smu);
 118         free(host->pmecc_mu);
 119         free(host->pmecc_dmu);
 120         free(host->pmecc_delta);
 121 }
 122
 123 static int pmecc_data_alloc(struct atmel_nand_host *host)
 124 {
 125         const int cap = host->pmecc_corr_cap;
 126         int size;
 127
 128         size = (2 * cap + 1) * sizeof(int16_t);
 129         host->pmecc_partial_syn = malloc(size);
 130         host->pmecc_si = malloc(size);
 131         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
 132         host->pmecc_smu = malloc((cap + 2) * size);
 133
 134         size = (cap + 1) * sizeof(int);
 135         host->pmecc_mu = malloc(size);
 136         host->pmecc_dmu = malloc(size);
 137         host->pmecc_delta = malloc(size);
 138
 139         if (host->pmecc_partial_syn &&
 140                         host->pmecc_si &&
 141                         host->pmecc_lmu &&
 142                         host->pmecc_smu &&
 143                         host->pmecc_mu &&
 144                         host->pmecc_dmu &&
 145                         host->pmecc_delta)
 146                 return 0;
 147
 148         /* error happened */
 149         pmecc_data_free(host);
 150         return -ENOMEM;
 151
 152 }
 153
 154 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 155 {
 156         struct nand_chip *nand_chip = mtd->priv;
 157         struct atmel_nand_host *host = nand_chip->priv;
 158         int i;
 159         uint32_t value;
 160
 161         /* Fill odd syndromes */
 162         for (i = 0; i < host->pmecc_corr_cap; i++) {
 163                 value = readl(&host->pmecc->rem_port[sector].rem[i / 2]);
 164                 if (i & 1)
 165                         value >>= 16;
 166                 value &= 0xffff;
 167                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 168         }
 169 }
 170
 171 static void pmecc_substitute(struct mtd_info *mtd)
 172 {
 173         struct nand_chip *nand_chip = mtd->priv;
 174         struct atmel_nand_host *host = nand_chip->priv;
 175         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 176         int16_t __iomem *index_of = host->pmecc_index_of;
 177         int16_t *partial_syn = host->pmecc_partial_syn;
 178         const int cap = host->pmecc_corr_cap;
 179         int16_t *si;
 180         int i, j;
 181
 182         /* si[] is a table that holds the current syndrome value,
 183          * an element of that table belongs to the field
 184          */
 185         si = host->pmecc_si;
 186
 187         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 188
 189         /* Computation 2t syndromes based on S(x) */
 190         /* Odd syndromes */
 191         for (i = 1; i < 2 * cap; i += 2) {
 192                 for (j = 0; j < host->pmecc_degree; j++) {
 193                         if (partial_syn[i] & (0x1 << j))
 194                                 si[i] = readw(alpha_to + i * j) ^ si[i];
 195                 }
 196         }
 197         /* Even syndrome = (Odd syndrome) ** 2 */
 198         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 199                 if (si[j] == 0) {
 200                         si[i] = 0;
 201                 } else {
 202                         int16_t tmp;
 203
 204                         tmp = readw(index_of + si[j]);
 205                         tmp = (tmp * 2) % host->pmecc_cw_len;
 206                         si[i] = readw(alpha_to + tmp);
 207                 }
 208         }
 209 }
 210
 211 /*
 212  * This function defines a Berlekamp iterative procedure for
 213  * finding the value of the error location polynomial.
 214  * The input is si[], initialize by pmecc_substitute().
 215  * The output is smu[][].
 216  *
 217  * This function is written according to chip datasheet Chapter:
 218  * Find the Error Location Polynomial Sigma(x) of Section:
 219  * Programmable Multibit ECC Control (PMECC).
 220  */
 221 static void pmecc_get_sigma(struct mtd_info *mtd)
 222 {
 223         struct nand_chip *nand_chip = mtd->priv;
 224         struct atmel_nand_host *host = nand_chip->priv;
 225
 226         int16_t *lmu = host->pmecc_lmu;
 227         int16_t *si = host->pmecc_si;
 228         int *mu = host->pmecc_mu;
 229         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 230         int *delta = host->pmecc_delta; /* Delta order */
 231         int cw_len = host->pmecc_cw_len;
 232         const int16_t cap = host->pmecc_corr_cap;
 233         const int num = 2 * cap + 1;
 234         int16_t __iomem *index_of = host->pmecc_index_of;
 235         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 236         int i, j, k;
 237         uint32_t dmu_0_count, tmp;
 238         int16_t *smu = host->pmecc_smu;
 239
 240         /* index of largest delta */
 241         int ro;
 242         int largest;
 243         int diff;
 244
 245         /* Init the Sigma(x) */
 246         memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
 247
 248         dmu_0_count = 0;
 249
 250         /* First Row */
 251
 252         /* Mu */
 253         mu[0] = -1;
 254
 255         smu[0] = 1;
 256
 257         /* discrepancy set to 1 */
 258         dmu[0] = 1;
 259         /* polynom order set to 0 */
 260         lmu[0] = 0;
 261         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
 262         delta[0] = -1;
 263
 264         /* Second Row */
 265
 266         /* Mu */
 267         mu[1] = 0;
 268         /* Sigma(x) set to 1 */
 269         smu[num] = 1;
 270
 271         /* discrepancy set to S1 */
 272         dmu[1] = si[1];
 273
 274         /* polynom order set to 0 */
 275         lmu[1] = 0;
 276
 277         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
 278         delta[1] = 0;
 279
 280         for (i = 1; i <= cap; i++) {
 281                 mu[i + 1] = i << 1;
 282                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 283                 /* check if discrepancy is set to 0 */
 284                 if (dmu[i] == 0) {
 285                         dmu_0_count++;
 286
 287                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 288                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 289                                 tmp += 2;
 290                         else
 291                                 tmp += 1;
 292
 293                         if (dmu_0_count == tmp) {
 294                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 295                                         smu[(cap + 1) * num + j] =
 296                                                         smu[i * num + j];
 297
 298                                 lmu[cap + 1] = lmu[i];
 299                                 return;
 300                         }
 301
 302                         /* copy polynom */
 303                         for (j = 0; j <= lmu[i] >> 1; j++)
 304                                 smu[(i + 1) * num + j] = smu[i * num + j];
 305
 306                         /* copy previous polynom order to the next */
 307                         lmu[i + 1] = lmu[i];
 308                 } else {
 309                         ro = 0;
 310                         largest = -1;
 311                         /* find largest delta with dmu != 0 */
 312                         for (j = 0; j < i; j++) {
 313                                 if ((dmu[j]) && (delta[j] > largest)) {
 314                                         largest = delta[j];
 315                                         ro = j;
 316                                 }
 317                         }
 318
 319                         /* compute difference */
 320                         diff = (mu[i] - mu[ro]);
 321
 322                         /* Compute degree of the new smu polynomial */
 323                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 324                                 lmu[i + 1] = lmu[i];
 325                         else
 326                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 327
 328                         /* Init smu[i+1] with 0 */
 329                         for (k = 0; k < num; k++)
 330                                 smu[(i + 1) * num + k] = 0;
 331
 332                         /* Compute smu[i+1] */
 333                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 334                                 int16_t a, b, c;
 335
 336                                 if (!(smu[ro * num + k] && dmu[i]))
 337                                         continue;
 338                                 a = readw(index_of + dmu[i]);
 339                                 b = readw(index_of + dmu[ro]);
 340                                 c = readw(index_of + smu[ro * num + k]);
 341                                 tmp = a + (cw_len - b) + c;
 342                                 a = readw(alpha_to + tmp % cw_len);
 343                                 smu[(i + 1) * num + (k + diff)] = a;
 344                         }
 345
 346                         for (k = 0; k <= lmu[i] >> 1; k++)
 347                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 348                 }
 349
 350                 /* End Computing Sigma (Mu+1) and L(mu) */
 351                 /* In either case compute delta */
 352                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 353
 354                 /* Do not compute discrepancy for the last iteration */
 355                 if (i >= cap)
 356                         continue;
 357
 358                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 359                         tmp = 2 * (i - 1);
 360                         if (k == 0) {
 361                                 dmu[i + 1] = si[tmp + 3];
 362                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 363                                 int16_t a, b, c;
 364                                 a = readw(index_of +
 365                                                 smu[(i + 1) * num + k]);
 366                                 b = si[2 * (i - 1) + 3 - k];
 367                                 c = readw(index_of + b);
 368                                 tmp = a + c;
 369                                 tmp %= cw_len;
 370                                 dmu[i + 1] = readw(alpha_to + tmp) ^
 371                                         dmu[i + 1];
 372                         }
 373                 }
 374         }
 375 }
 376
 377 static int pmecc_err_location(struct mtd_info *mtd)
 378 {
 379         struct nand_chip *nand_chip = mtd->priv;
 380         struct atmel_nand_host *host = nand_chip->priv;
 381         const int cap = host->pmecc_corr_cap;
 382         const int num = 2 * cap + 1;
 383         int sector_size = host->pmecc_sector_size;
 384         int err_nbr = 0;        /* number of error */
 385         int roots_nbr;          /* number of roots */
 386         int i;
 387         uint32_t val;
 388         int16_t *smu = host->pmecc_smu;
 389         int timeout = PMECC_MAX_TIMEOUT_US;
 390
 391         writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis);
 392
 393         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 394                 writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]);
 395                 err_nbr++;
 396         }
 397
 398         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
 399         if (sector_size == 1024)
 400                 val |= PMERRLOC_ELCFG_SECTOR_1024;
 401
 402         writel(val, &host->pmerrloc->elcfg);
 403         writel(sector_size * 8 + host->pmecc_degree * cap,
 404                         &host->pmerrloc->elen);
 405
 406         while (--timeout) {
 407                 if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE)
 408                         break;
 409                 WATCHDOG_RESET();
 410                 udelay(1);
 411         }
 412
 413         if (!timeout) {
 414                 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
 415                 return -1;
 416         }
 417
 418         roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK)
 419                         >> 8;
 420         /* Number of roots == degree of smu hence <= cap */
 421         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 422                 return err_nbr - 1;
 423
 424         /* Number of roots does not match the degree of smu
 425          * unable to correct error */
 426         return -1;
 427 }
 428
 429 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 430                 int sector_num, int extra_bytes, int err_nbr)
 431 {
 432         struct nand_chip *nand_chip = mtd->priv;
 433         struct atmel_nand_host *host = nand_chip->priv;
 434         int i = 0;
 435         int byte_pos, bit_pos, sector_size, pos;
 436         uint32_t tmp;
 437         uint8_t err_byte;
 438
 439         sector_size = host->pmecc_sector_size;
 440
 441         while (err_nbr) {
 442                 tmp = readl(&host->pmerrloc->el[i]) - 1;
 443                 byte_pos = tmp / 8;
 444                 bit_pos  = tmp % 8;
 445
 446                 if (byte_pos >= (sector_size + extra_bytes))
 447                         BUG();  /* should never happen */
 448
 449                 if (byte_pos < sector_size) {
 450                         err_byte = *(buf + byte_pos);
 451                         *(buf + byte_pos) ^= (1 << bit_pos);
 452
 453                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 454                         dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 455                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 456                 } else {
 457                         /* Bit flip in OOB area */
 458                         tmp = sector_num * host->pmecc_bytes_per_sector
 459                                         + (byte_pos - sector_size);
 460                         err_byte = ecc[tmp];
 461                         ecc[tmp] ^= (1 << bit_pos);
 462
 463                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
 464                         dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 465                                 pos, bit_pos, err_byte, ecc[tmp]);
 466                 }
 467
 468                 i++;
 469                 err_nbr--;
 470         }
 471
 472         return;
 473 }
 474
 475 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 476         u8 *ecc)
 477 {
 478         struct nand_chip *nand_chip = mtd->priv;
 479         struct atmel_nand_host *host = nand_chip->priv;
 480         int i, err_nbr, eccbytes;
 481         uint8_t *buf_pos;
 482
 483         eccbytes = nand_chip->ecc.bytes;
 484         for (i = 0; i < eccbytes; i++)
 485                 if (ecc[i] != 0xff)
 486                         goto normal_check;
 487         /* Erased page, return OK */
 488         return 0;
 489
 490 normal_check:
 491         for (i = 0; i < host->pmecc_sector_number; i++) {
 492                 err_nbr = 0;
 493                 if (pmecc_stat & 0x1) {
 494                         buf_pos = buf + i * host->pmecc_sector_size;
 495
 496                         pmecc_gen_syndrome(mtd, i);
 497                         pmecc_substitute(mtd);
 498                         pmecc_get_sigma(mtd);
 499
 500                         err_nbr = pmecc_err_location(mtd);
 501                         if (err_nbr == -1) {
 502                                 dev_err(host->dev, "PMECC: Too many errors\n");
 503                                 mtd->ecc_stats.failed++;
 504                                 return -EIO;
 505                         } else {
 506                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 507                                         host->pmecc_bytes_per_sector, err_nbr);
 508                                 mtd->ecc_stats.corrected += err_nbr;
 509                         }
 510                 }
 511                 pmecc_stat >>= 1;
 512         }
 513
 514         return 0;
 515 }
 516
 517 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 518         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 519 {
 520         struct atmel_nand_host *host = chip->priv;
 521         int eccsize = chip->ecc.size;
 522         uint8_t *oob = chip->oob_poi;
 523         uint32_t *eccpos = chip->ecc.layout->eccpos;
 524         uint32_t stat;
 525         int timeout = PMECC_MAX_TIMEOUT_US;
 526
 527         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 528         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 529         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
 530                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
 531
 532         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 533         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 534
 535         chip->read_buf(mtd, buf, eccsize);
 536         chip->read_buf(mtd, oob, mtd->oobsize);
 537
 538         while (--timeout) {
 539                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 540                         break;
 541                 WATCHDOG_RESET();
 542                 udelay(1);
 543         }
 544
 545         if (!timeout) {
 546                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
 547                 return -1;
 548         }
 549
 550         stat = pmecc_readl(host->pmecc, isr);
 551         if (stat != 0)
 552                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
 553                         return -EIO;
 554
 555         return 0;
 556 }
 557
 558 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 559                 struct nand_chip *chip, const uint8_t *buf,
 560                 int oob_required)
 561 {
 562         struct atmel_nand_host *host = chip->priv;
 563         uint32_t *eccpos = chip->ecc.layout->eccpos;
 564         int i, j;
 565         int timeout = PMECC_MAX_TIMEOUT_US;
 566
 567         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 568         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 569
 570         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
 571                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
 572
 573         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 574         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 575
 576         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 577
 578         while (--timeout) {
 579                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 580                         break;
 581                 WATCHDOG_RESET();
 582                 udelay(1);
 583         }
 584
 585         if (!timeout) {
 586                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
 587                 goto out;
 588         }
 589
 590         for (i = 0; i < host->pmecc_sector_number; i++) {
 591                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
 592                         int pos;
 593
 594                         pos = i * host->pmecc_bytes_per_sector + j;
 595                         chip->oob_poi[eccpos[pos]] =
 596                                 readb(&host->pmecc->ecc_port[i].ecc[j]);
 597                 }
 598         }
 599         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 600 out:
 601         return 0;
 602 }
 603
 604 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 605 {
 606         struct nand_chip *nand_chip = mtd->priv;
 607         struct atmel_nand_host *host = nand_chip->priv;
 608         uint32_t val = 0;
 609         struct nand_ecclayout *ecc_layout;
 610
 611         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 612         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 613
 614         switch (host->pmecc_corr_cap) {
 615         case 2:
 616                 val = PMECC_CFG_BCH_ERR2;
 617                 break;
 618         case 4:
 619                 val = PMECC_CFG_BCH_ERR4;
 620                 break;
 621         case 8:
 622                 val = PMECC_CFG_BCH_ERR8;
 623                 break;
 624         case 12:
 625                 val = PMECC_CFG_BCH_ERR12;
 626                 break;
 627         case 24:
 628                 val = PMECC_CFG_BCH_ERR24;
 629                 break;
 630         }
 631
 632         if (host->pmecc_sector_size == 512)
 633                 val |= PMECC_CFG_SECTOR512;
 634         else if (host->pmecc_sector_size == 1024)
 635                 val |= PMECC_CFG_SECTOR1024;
 636
 637         switch (host->pmecc_sector_number) {
 638         case 1:
 639                 val |= PMECC_CFG_PAGE_1SECTOR;
 640                 break;
 641         case 2:
 642                 val |= PMECC_CFG_PAGE_2SECTORS;
 643                 break;
 644         case 4:
 645                 val |= PMECC_CFG_PAGE_4SECTORS;
 646                 break;
 647         case 8:
 648                 val |= PMECC_CFG_PAGE_8SECTORS;
 649                 break;
 650         }
 651
 652         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
 653                 | PMECC_CFG_AUTO_DISABLE);
 654         pmecc_writel(host->pmecc, cfg, val);
 655
 656         ecc_layout = nand_chip->ecc.layout;
 657         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
 658         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
 659         pmecc_writel(host->pmecc, eaddr,
 660                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
 661         /* See datasheet about PMECC Clock Control Register */
 662         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
 663         pmecc_writel(host->pmecc, idr, 0xff);
 664         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 665 }
 666
 667 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 668 /*
 669  * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
 670  * @ecc_bits: store the ONFI ECC correct bits capbility
 671  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
 672  *
 673  * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
 674  * @sector_size are initialize to 0.
 675  * Return 0 if success to get the ECC requirement.
 676  */
 677 static int get_onfi_ecc_param(struct nand_chip *chip,
 678                 int *ecc_bits, int *sector_size)
 679 {
 680         *ecc_bits = *sector_size = 0;
 681
 682         if (chip->onfi_params.ecc_bits == 0xff)
 683                 /* TODO: the sector_size and ecc_bits need to be find in
 684                  * extended ecc parameter, currently we don't support it.
 685                  */
 686                 return -1;
 687
 688         *ecc_bits = chip->onfi_params.ecc_bits;
 689
 690         /* The default sector size (ecc codeword size) is 512 */
 691         *sector_size = 512;
 692
 693         return 0;
 694 }
 695
 696 /*
 697  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
 698  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
 699  *                    ONFI ECC parameters.
 700  * @host: point to an atmel_nand_host structure.
 701  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
 702  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
 703  * @chip: point to an nand_chip structure.
 704  * @cap: store the ONFI ECC correct bits capbility
 705  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
 706  *
 707  * Return 0 if success. otherwise return the error code.
 708  */
 709 static int pmecc_choose_ecc(struct atmel_nand_host *host,
 710                 struct nand_chip *chip,
 711                 int *cap, int *sector_size)
 712 {
 713         /* Get ECC requirement from ONFI parameters */
 714         *cap = *sector_size = 0;
 715         if (chip->onfi_version) {
 716                 if (!get_onfi_ecc_param(chip, cap, sector_size)) {
 717                         MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
 718                                 *cap, *sector_size);
 719                 } else {
 720                         dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
 721                 }
 722         } else {
 723                 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
 724         }
 725         if (*cap == 0 && *sector_size == 0) {
 726                 /* Non-ONFI compliant or use extended ONFI parameters */
 727                 *cap = 2;
 728                 *sector_size = 512;
 729         }
 730
 731         /* If head file doesn't specify then use the one in ONFI parameters */
 732         if (host->pmecc_corr_cap == 0) {
 733                 /* use the most fitable ecc bits (the near bigger one ) */
 734                 if (*cap <= 2)
 735                         host->pmecc_corr_cap = 2;
 736                 else if (*cap <= 4)
 737                         host->pmecc_corr_cap = 4;
 738                 else if (*cap <= 8)
 739                         host->pmecc_corr_cap = 8;
 740                 else if (*cap <= 12)
 741                         host->pmecc_corr_cap = 12;
 742                 else if (*cap <= 24)
 743                         host->pmecc_corr_cap = 24;
 744                 else
 745                         return -EINVAL;
 746         }
 747         if (host->pmecc_sector_size == 0) {
 748                 /* use the most fitable sector size (the near smaller one ) */
 749                 if (*sector_size >= 1024)
 750                         host->pmecc_sector_size = 1024;
 751                 else if (*sector_size >= 512)
 752                         host->pmecc_sector_size = 512;
 753                 else
 754                         return -EINVAL;
 755         }
 756         return 0;
 757 }
 758 #endif
 759
 760 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 761                 struct mtd_info *mtd)
 762 {
 763         struct atmel_nand_host *host;
 764         int cap, sector_size;
 765
 766         host = nand->priv = &pmecc_host;
 767
 768         nand->ecc.mode = NAND_ECC_HW;
 769         nand->ecc.calculate = NULL;
 770         nand->ecc.correct = NULL;
 771         nand->ecc.hwctl = NULL;
 772
 773 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 774         host->pmecc_corr_cap = host->pmecc_sector_size = 0;
 775
 776 #ifdef CONFIG_PMECC_CAP
 777         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 778 #endif
 779 #ifdef CONFIG_PMECC_SECTOR_SIZE
 780         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 781 #endif
 782         /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
 783          * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
 784          * from ONFI.
 785          */
 786         if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
 787                 dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
 788                                 cap, sector_size);
 789                 return -EINVAL;
 790         }
 791
 792         if (cap > host->pmecc_corr_cap)
 793                 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
 794                                 host->pmecc_corr_cap, cap);
 795         if (sector_size < host->pmecc_sector_size)
 796                 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
 797                                 host->pmecc_sector_size, sector_size);
 798 #else   /* CONFIG_SYS_NAND_ONFI_DETECTION */
 799         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 800         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 801 #endif
 802
 803         cap = host->pmecc_corr_cap;
 804         sector_size = host->pmecc_sector_size;
 805
 806         /* TODO: need check whether cap & sector_size is validate */
 807
 808         if (host->pmecc_sector_size == 512)
 809                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
 810         else
 811                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
 812
 813         MTDDEBUG(MTD_DEBUG_LEVEL1,
 814                 "Initialize PMECC params, cap: %d, sector: %d\n",
 815                 cap, sector_size);
 816
 817         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
 818         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
 819                         ATMEL_BASE_PMERRLOC;
 820         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
 821
 822         /* ECC is calculated for the whole page (1 step) */
 823         nand->ecc.size = mtd->writesize;
 824
 825         /* set ECC page size and oob layout */
 826         switch (mtd->writesize) {
 827         case 2048:
 828         case 4096:
 829         case 8192:
 830                 host->pmecc_degree = (sector_size == 512) ?
 831                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
 832                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
 833                 host->pmecc_sector_number = mtd->writesize / sector_size;
 834                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
 835                         cap, sector_size);
 836                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
 837                 host->pmecc_index_of = host->pmecc_rom_base +
 838                         host->pmecc_index_table_offset;
 839
 840                 nand->ecc.steps = 1;
 841                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
 842                                        host->pmecc_sector_number;
 843
 844                 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
 845                         dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
 846                                         MTD_MAX_ECCPOS_ENTRIES_LARGE);
 847                         return -EINVAL;
 848                 }
 849
 850                 if (nand->ecc.bytes > mtd->oobsize - 2) {
 851                         dev_err(host->dev, "No room for ECC bytes\n");
 852                         return -EINVAL;
 853                 }
 854                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
 855                                         mtd->oobsize,
 856                                         nand->ecc.bytes);
 857                 nand->ecc.layout = &atmel_pmecc_oobinfo;
 858                 break;
 859         case 512:
 860         case 1024:
 861                 /* TODO */
 862                 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
 863         default:
 864                 /* page size not handled by HW ECC */
 865                 /* switching back to soft ECC */
 866                 nand->ecc.mode = NAND_ECC_SOFT;
 867                 nand->ecc.read_page = NULL;
 868                 nand->ecc.postpad = 0;
 869                 nand->ecc.prepad = 0;
 870                 nand->ecc.bytes = 0;
 871                 return 0;
 872         }
 873
 874         /* Allocate data for PMECC computation */
 875         if (pmecc_data_alloc(host)) {
 876                 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
 877                 return -ENOMEM;
 878         }
 879
 880         nand->ecc.read_page = atmel_nand_pmecc_read_page;
 881         nand->ecc.write_page = atmel_nand_pmecc_write_page;
 882         nand->ecc.strength = cap;
 883
 884         atmel_pmecc_core_init(mtd);
 885
 886         return 0;
 887 }
 888
 889 #else
 890
 891 /* oob layout for large page size
 892  * bad block info is on bytes 0 and 1
 893  * the bytes have to be consecutives to avoid
 894  * several NAND_CMD_RNDOUT during read
 895  */
 896 static struct nand_ecclayout atmel_oobinfo_large = {
 897         .eccbytes = 4,
 898         .eccpos = {60, 61, 62, 63},
 899         .oobfree = {
 900                 {2, 58}
 901         },
 902 };
 903
 904 /* oob layout for small page size
 905  * bad block info is on bytes 4 and 5
 906  * the bytes have to be consecutives to avoid
 907  * several NAND_CMD_RNDOUT during read
 908  */
 909 static struct nand_ecclayout atmel_oobinfo_small = {
 910         .eccbytes = 4,
 911         .eccpos = {0, 1, 2, 3},
 912         .oobfree = {
 913                 {6, 10}
 914         },
 915 };
 916
 917 /*
 918  * Calculate HW ECC
 919  *
 920  * function called after a write
 921  *
 922  * mtd:        MTD block structure
 923  * dat:        raw data (unused)
 924  * ecc_code:   buffer for ECC
 925  */
 926 static int atmel_nand_calculate(struct mtd_info *mtd,
 927                 const u_char *dat, unsigned char *ecc_code)
 928 {
 929         unsigned int ecc_value;
 930
 931         /* get the first 2 ECC bytes */
 932         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
 933
 934         ecc_code[0] = ecc_value & 0xFF;
 935         ecc_code[1] = (ecc_value >> 8) & 0xFF;
 936
 937         /* get the last 2 ECC bytes */
 938         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
 939
 940         ecc_code[2] = ecc_value & 0xFF;
 941         ecc_code[3] = (ecc_value >> 8) & 0xFF;
 942
 943         return 0;
 944 }
 945
 946 /*
 947  * HW ECC read page function
 948  *
 949  * mtd:        mtd info structure
 950  * chip:       nand chip info structure
 951  * buf:        buffer to store read data
 952  * oob_required:    caller expects OOB data read to chip->oob_poi
 953  */
 954 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 955                                 uint8_t *buf, int oob_required, int page)
 956 {
 957         int eccsize = chip->ecc.size;
 958         int eccbytes = chip->ecc.bytes;
 959         uint32_t *eccpos = chip->ecc.layout->eccpos;
 960         uint8_t *p = buf;
 961         uint8_t *oob = chip->oob_poi;
 962         uint8_t *ecc_pos;
 963         int stat;
 964
 965         /* read the page */
 966         chip->read_buf(mtd, p, eccsize);
 967
 968         /* move to ECC position if needed */
 969         if (eccpos[0] != 0) {
 970                 /* This only works on large pages
 971                  * because the ECC controller waits for
 972                  * NAND_CMD_RNDOUTSTART after the
 973                  * NAND_CMD_RNDOUT.
 974                  * anyway, for small pages, the eccpos[0] == 0
 975                  */
 976                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
 977                                 mtd->writesize + eccpos[0], -1);
 978         }
 979
 980         /* the ECC controller needs to read the ECC just after the data */
 981         ecc_pos = oob + eccpos[0];
 982         chip->read_buf(mtd, ecc_pos, eccbytes);
 983
 984         /* check if there's an error */
 985         stat = chip->ecc.correct(mtd, p, oob, NULL);
 986
 987         if (stat < 0)
 988                 mtd->ecc_stats.failed++;
 989         else
 990                 mtd->ecc_stats.corrected += stat;
 991
 992         /* get back to oob start (end of page) */
 993         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 994
 995         /* read the oob */
 996         chip->read_buf(mtd, oob, mtd->oobsize);
 997
 998         return 0;
 999 }
1000
1001 /*
1002  * HW ECC Correction
1003  *
1004  * function called after a read
1005  *
1006  * mtd:        MTD block structure
1007  * dat:        raw data read from the chip
1008  * read_ecc:   ECC from the chip (unused)
1009  * isnull:     unused
1010  *
1011  * Detect and correct a 1 bit error for a page
1012  */
1013 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1014                 u_char *read_ecc, u_char *isnull)
1015 {
1016         struct nand_chip *nand_chip = mtd->priv;
1017         unsigned int ecc_status;
1018         unsigned int ecc_word, ecc_bit;
1019
1020         /* get the status from the Status Register */
1021         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1022
1023         /* if there's no error */
1024         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1025                 return 0;
1026
1027         /* get error bit offset (4 bits) */
1028         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1029         /* get word address (12 bits) */
1030         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1031         ecc_word >>= 4;
1032
1033         /* if there are multiple errors */
1034         if (ecc_status & ATMEL_ECC_MULERR) {
1035                 /* check if it is a freshly erased block
1036                  * (filled with 0xff) */
1037                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1038                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1039                         /* the block has just been erased, return OK */
1040                         return 0;
1041                 }
1042                 /* it doesn't seems to be a freshly
1043                  * erased block.
1044                  * We can't correct so many errors */
1045                 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1046                                 " Unable to correct.\n");
1047                 return -EIO;
1048         }
1049
1050         /* if there's a single bit error : we can correct it */
1051         if (ecc_status & ATMEL_ECC_ECCERR) {
1052                 /* there's nothing much to do here.
1053                  * the bit error is on the ECC itself.
1054                  */
1055                 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1056                                 " Nothing to correct\n");
1057                 return 0;
1058         }
1059
1060         dev_warn(host->dev, "atmel_nand : one bit error on data."
1061                         " (word offset in the page :"
1062                         " 0x%x bit offset : 0x%x)\n",
1063                         ecc_word, ecc_bit);
1064         /* correct the error */
1065         if (nand_chip->options & NAND_BUSWIDTH_16) {
1066                 /* 16 bits words */
1067                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1068         } else {
1069                 /* 8 bits words */
1070                 dat[ecc_word] ^= (1 << ecc_bit);
1071         }
1072         dev_warn(host->dev, "atmel_nand : error corrected\n");
1073         return 1;
1074 }
1075
1076 /*
1077  * Enable HW ECC : unused on most chips
1078  */
1079 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1080 {
1081 }
1082
1083 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1084 {
1085         nand->ecc.mode = NAND_ECC_HW;
1086         nand->ecc.calculate = atmel_nand_calculate;
1087         nand->ecc.correct = atmel_nand_correct;
1088         nand->ecc.hwctl = atmel_nand_hwctl;
1089         nand->ecc.read_page = atmel_nand_read_page;
1090         nand->ecc.bytes = 4;
1091
1092         if (nand->ecc.mode == NAND_ECC_HW) {
1093                 /* ECC is calculated for the whole page (1 step) */
1094                 nand->ecc.size = mtd->writesize;
1095
1096                 /* set ECC page size and oob layout */
1097                 switch (mtd->writesize) {
1098                 case 512:
1099                         nand->ecc.layout = &atmel_oobinfo_small;
1100                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1101                                         ATMEL_ECC_PAGESIZE_528);
1102                         break;
1103                 case 1024:
1104                         nand->ecc.layout = &atmel_oobinfo_large;
1105                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1106                                         ATMEL_ECC_PAGESIZE_1056);
1107                         break;
1108                 case 2048:
1109                         nand->ecc.layout = &atmel_oobinfo_large;
1110                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1111                                         ATMEL_ECC_PAGESIZE_2112);
1112                         break;
1113                 case 4096:
1114                         nand->ecc.layout = &atmel_oobinfo_large;
1115                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1116                                         ATMEL_ECC_PAGESIZE_4224);
1117                         break;
1118                 default:
1119                         /* page size not handled by HW ECC */
1120                         /* switching back to soft ECC */
1121                         nand->ecc.mode = NAND_ECC_SOFT;
1122                         nand->ecc.calculate = NULL;
1123                         nand->ecc.correct = NULL;
1124                         nand->ecc.hwctl = NULL;
1125                         nand->ecc.read_page = NULL;
1126                         nand->ecc.postpad = 0;
1127                         nand->ecc.prepad = 0;
1128                         nand->ecc.bytes = 0;
1129                         break;
1130                 }
1131         }
1132
1133         return 0;
1134 }
1135
1136 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1137
1138 #endif /* CONFIG_ATMEL_NAND_HWECC */
1139
1140 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1141                                          int cmd, unsigned int ctrl)
1142 {
1143         struct nand_chip *this = mtd->priv;
1144
1145         if (ctrl & NAND_CTRL_CHANGE) {
1146                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1147                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1148                              | CONFIG_SYS_NAND_MASK_CLE);
1149
1150                 if (ctrl & NAND_CLE)
1151                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1152                 if (ctrl & NAND_ALE)
1153                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1154
1155 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1156                 gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
1157 #endif
1158                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1159         }
1160
1161         if (cmd != NAND_CMD_NONE)
1162                 writeb(cmd, this->IO_ADDR_W);
1163 }
1164
1165 #ifdef CONFIG_SYS_NAND_READY_PIN
1166 static int at91_nand_ready(struct mtd_info *mtd)
1167 {
1168         return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
1169 }
1170 #endif
1171
1172 #ifndef CONFIG_SYS_NAND_BASE_LIST
1173 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1174 #endif
1175 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1176 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1177
1178 int atmel_nand_chip_init(int devnum, ulong base_addr)
1179 {
1180         int ret;
1181         struct mtd_info *mtd = &nand_info[devnum];
1182         struct nand_chip *nand = &nand_chip[devnum];
1183
1184         mtd->priv = nand;
1185         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1186
1187 #ifdef CONFIG_NAND_ECC_BCH
1188         nand->ecc.mode = NAND_ECC_SOFT_BCH;
1189 #else
1190         nand->ecc.mode = NAND_ECC_SOFT;
1191 #endif
1192 #ifdef CONFIG_SYS_NAND_DBW_16
1193         nand->options = NAND_BUSWIDTH_16;
1194 #endif
1195         nand->cmd_ctrl = at91_nand_hwcontrol;
1196 #ifdef CONFIG_SYS_NAND_READY_PIN
1197         nand->dev_ready = at91_nand_ready;
1198 #endif
1199         nand->chip_delay = 75;
1200
1201         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1202         if (ret)
1203                 return ret;
1204
1205 #ifdef CONFIG_ATMEL_NAND_HWECC
1206 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1207         ret = atmel_pmecc_nand_init_params(nand, mtd);
1208 #else
1209         ret = atmel_hwecc_nand_init_param(nand, mtd);
1210 #endif
1211         if (ret)
1212                 return ret;
1213 #endif
1214
1215         ret = nand_scan_tail(mtd);
1216         if (!ret)
1217                 nand_register(devnum);
1218
1219         return ret;
1220 }
1221
1222 void board_nand_init(void)
1223 {
1224         int i;
1225         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1226                 if (atmel_nand_chip_init(i, base_addr[i]))
1227                         dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1228                                 i);
1229 }