drivers/mtd/nand/omap_gpmc.c

   1 /*
   2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
   3  * Rohit Choraria <rohitkc@ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/mem.h>
  12 #include <linux/mtd/omap_gpmc.h>
  13 #include <linux/mtd/nand_ecc.h>
  14 #include <linux/bch.h>
  15 #include <linux/compiler.h>
  16 #include <nand.h>
  17 #include <linux/mtd/omap_elm.h>
  18
  19 #define BADBLOCK_MARKER_LENGTH  2
  20 #define SECTOR_BYTES            512
  21 #define ECCCLEAR                (0x1 << 8)
  22 #define ECCRESULTREG1           (0x1 << 0)
  23 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
  24 #define BCH4_BIT_PAD            4
  25
  26 #ifdef CONFIG_BCH
  27 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
  28                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
  29 #endif
  30 static uint8_t cs;
  31 static __maybe_unused struct nand_ecclayout omap_ecclayout;
  32
  33 /*
  34  * omap_nand_hwcontrol - Set the address pointers corretly for the
  35  *                      following address/data/command operation
  36  */
  37 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
  38                                 uint32_t ctrl)
  39 {
  40         register struct nand_chip *this = mtd->priv;
  41
  42         /*
  43          * Point the IO_ADDR to DATA and ADDRESS registers instead
  44          * of chip address
  45          */
  46         switch (ctrl) {
  47         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
  48                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
  49                 break;
  50         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
  51                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
  52                 break;
  53         case NAND_CTRL_CHANGE | NAND_NCE:
  54                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
  55                 break;
  56         }
  57
  58         if (cmd != NAND_CMD_NONE)
  59                 writeb(cmd, this->IO_ADDR_W);
  60 }
  61
  62 #ifdef CONFIG_SPL_BUILD
  63 /* Check wait pin as dev ready indicator */
  64 int omap_spl_dev_ready(struct mtd_info *mtd)
  65 {
  66         return gpmc_cfg->status & (1 << 8);
  67 }
  68 #endif
  69
  70
  71 /*
  72  * gen_true_ecc - This function will generate true ECC value, which
  73  * can be used when correcting data read from NAND flash memory core
  74  *
  75  * @ecc_buf:    buffer to store ecc code
  76  *
  77  * @return:     re-formatted ECC value
  78  */
  79 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
  80 {
  81         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
  82                 ((ecc_buf[2] & 0x0F) << 8);
  83 }
  84
  85 /*
  86  * omap_correct_data - Compares the ecc read from nand spare area with ECC
  87  * registers values and corrects one bit error if it has occured
  88  * Further details can be had from OMAP TRM and the following selected links:
  89  * http://en.wikipedia.org/wiki/Hamming_code
  90  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
  91  *
  92  * @mtd:                 MTD device structure
  93  * @dat:                 page data
  94  * @read_ecc:            ecc read from nand flash
  95  * @calc_ecc:            ecc read from ECC registers
  96  *
  97  * @return 0 if data is OK or corrected, else returns -1
  98  */
  99 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 100                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 101 {
 102         uint32_t orig_ecc, new_ecc, res, hm;
 103         uint16_t parity_bits, byte;
 104         uint8_t bit;
 105
 106         /* Regenerate the orginal ECC */
 107         orig_ecc = gen_true_ecc(read_ecc);
 108         new_ecc = gen_true_ecc(calc_ecc);
 109         /* Get the XOR of real ecc */
 110         res = orig_ecc ^ new_ecc;
 111         if (res) {
 112                 /* Get the hamming width */
 113                 hm = hweight32(res);
 114                 /* Single bit errors can be corrected! */
 115                 if (hm == 12) {
 116                         /* Correctable data! */
 117                         parity_bits = res >> 16;
 118                         bit = (parity_bits & 0x7);
 119                         byte = (parity_bits >> 3) & 0x1FF;
 120                         /* Flip the bit to correct */
 121                         dat[byte] ^= (0x1 << bit);
 122                 } else if (hm == 1) {
 123                         printf("Error: Ecc is wrong\n");
 124                         /* ECC itself is corrupted */
 125                         return 2;
 126                 } else {
 127                         /*
 128                          * hm distance != parity pairs OR one, could mean 2 bit
 129                          * error OR potentially be on a blank page..
 130                          * orig_ecc: contains spare area data from nand flash.
 131                          * new_ecc: generated ecc while reading data area.
 132                          * Note: if the ecc = 0, all data bits from which it was
 133                          * generated are 0xFF.
 134                          * The 3 byte(24 bits) ecc is generated per 512byte
 135                          * chunk of a page. If orig_ecc(from spare area)
 136                          * is 0xFF && new_ecc(computed now from data area)=0x0,
 137                          * this means that data area is 0xFF and spare area is
 138                          * 0xFF. A sure sign of a erased page!
 139                          */
 140                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
 141                                 return 0;
 142                         printf("Error: Bad compare! failed\n");
 143                         /* detected 2 bit error */
 144                         return -1;
 145                 }
 146         }
 147         return 0;
 148 }
 149
 150 /*
 151  * Generic BCH interface
 152  */
 153 struct nand_bch_priv {
 154         struct bch_control *control;
 155         enum omap_ecc ecc_scheme;
 156 };
 157
 158 /*
 159  * This can be a single instance cause all current users have only one NAND
 160  * with nearly the same setup (BCH8, some with ELM and others with sw BCH
 161  * library).
 162  * When some users with other BCH strength will exists this have to change!
 163  */
 164 static __maybe_unused struct nand_bch_priv bch_priv = {
 165         .control = NULL
 166 };
 167
 168 /*
 169  * omap_reverse_list - re-orders list elements in reverse order [internal]
 170  * @list:       pointer to start of list
 171  * @length:     length of list
 172 */
 173 void omap_reverse_list(u8 *list, unsigned int length)
 174 {
 175         unsigned int i, j;
 176         unsigned int half_length = length / 2;
 177         u8 tmp;
 178         for (i = 0, j = length - 1; i < half_length; i++, j--) {
 179                 tmp = list[i];
 180                 list[i] = list[j];
 181                 list[j] = tmp;
 182         }
 183 }
 184
 185 /*
 186  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
 187  * @mtd:        MTD device structure
 188  * @mode:       Read/Write mode
 189  */
 190 __maybe_unused
 191 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 192 {
 193         struct nand_chip        *nand   = mtd->priv;
 194         struct nand_bch_priv    *bch    = nand->priv;
 195         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 196         unsigned int ecc_algo = 0;
 197         unsigned int bch_type = 0;
 198         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
 199         u32 ecc_size_config_val = 0;
 200         u32 ecc_config_val = 0;
 201
 202         /* configure GPMC for specific ecc-scheme */
 203         switch (bch->ecc_scheme) {
 204         case OMAP_ECC_HAM1_CODE_SW:
 205                 return;
 206         case OMAP_ECC_HAM1_CODE_HW:
 207                 ecc_algo = 0x0;
 208                 bch_type = 0x0;
 209                 bch_wrapmode = 0x00;
 210                 eccsize0 = 0xFF;
 211                 eccsize1 = 0xFF;
 212                 break;
 213         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 214         case OMAP_ECC_BCH8_CODE_HW:
 215                 ecc_algo = 0x1;
 216                 bch_type = 0x1;
 217                 if (mode == NAND_ECC_WRITE) {
 218                         bch_wrapmode = 0x01;
 219                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 220                         eccsize1 = 28; /* OOB bits in nibbles per sector */
 221                 } else {
 222                         bch_wrapmode = 0x01;
 223                         eccsize0 = 26; /* ECC bits in nibbles per sector */
 224                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
 225                 }
 226                 break;
 227         default:
 228                 return;
 229         }
 230         /* Clear ecc and enable bits */
 231         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 232         /* Configure ecc size for BCH */
 233         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
 234         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
 235
 236         /* Configure device details for BCH engine */
 237         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
 238                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
 239                         (bch_wrapmode << 8)     | /* wrap mode */
 240                         (dev_width << 7)        | /* bus width */
 241                         (0x0 << 4)              | /* number of sectors */
 242                         (cs <<  1)              | /* ECC CS */
 243                         (0x1));                   /* enable ECC */
 244         writel(ecc_config_val, &gpmc_cfg->ecc_config);
 245 }
 246
 247 /*
 248  *  omap_calculate_ecc - Read ECC result
 249  *  @mtd:       MTD structure
 250  *  @dat:       unused
 251  *  @ecc_code:  ecc_code buffer
 252  *  Using noninverted ECC can be considered ugly since writing a blank
 253  *  page ie. padding will clear the ECC bytes. This is no problem as
 254  *  long nobody is trying to write data on the seemingly unused page.
 255  *  Reading an erased page will produce an ECC mismatch between
 256  *  generated and read ECC bytes that has to be dealt with separately.
 257  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
 258  *  is used, the result of read will be 0x0 while the ECC offsets of the
 259  *  spare area will be 0xFF which will result in an ECC mismatch.
 260  */
 261 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 262                                 uint8_t *ecc_code)
 263 {
 264         struct nand_chip *chip = mtd->priv;
 265         struct nand_bch_priv *bch = chip->priv;
 266         uint32_t *ptr, val = 0;
 267         int8_t i = 0, j;
 268
 269         switch (bch->ecc_scheme) {
 270         case OMAP_ECC_HAM1_CODE_HW:
 271                 val = readl(&gpmc_cfg->ecc1_result);
 272                 ecc_code[0] = val & 0xFF;
 273                 ecc_code[1] = (val >> 16) & 0xFF;
 274                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 275                 break;
 276 #ifdef CONFIG_BCH
 277         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 278 #endif
 279         case OMAP_ECC_BCH8_CODE_HW:
 280                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
 281                 val = readl(ptr);
 282                 ecc_code[i++] = (val >>  0) & 0xFF;
 283                 ptr--;
 284                 for (j = 0; j < 3; j++) {
 285                         val = readl(ptr);
 286                         ecc_code[i++] = (val >> 24) & 0xFF;
 287                         ecc_code[i++] = (val >> 16) & 0xFF;
 288                         ecc_code[i++] = (val >>  8) & 0xFF;
 289                         ecc_code[i++] = (val >>  0) & 0xFF;
 290                         ptr--;
 291                 }
 292                 break;
 293         default:
 294                 return -EINVAL;
 295         }
 296         /* ECC scheme specific syndrome customizations */
 297         switch (bch->ecc_scheme) {
 298         case OMAP_ECC_HAM1_CODE_HW:
 299                 break;
 300 #ifdef CONFIG_BCH
 301         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 302
 303                 for (i = 0; i < chip->ecc.bytes; i++)
 304                         *(ecc_code + i) = *(ecc_code + i) ^
 305                                                 bch8_polynomial[i];
 306                 break;
 307 #endif
 308         case OMAP_ECC_BCH8_CODE_HW:
 309                 ecc_code[chip->ecc.bytes - 1] = 0x00;
 310                 break;
 311         default:
 312                 return -EINVAL;
 313         }
 314         return 0;
 315 }
 316
 317 #ifdef CONFIG_NAND_OMAP_ELM
 318 /*
 319  * omap_correct_data_bch - Compares the ecc read from nand spare area
 320  * with ECC registers values and corrects one bit error if it has occured
 321  *
 322  * @mtd:        MTD device structure
 323  * @dat:        page data
 324  * @read_ecc:   ecc read from nand flash (ignored)
 325  * @calc_ecc:   ecc read from ECC registers
 326  *
 327  * @return 0 if data is OK or corrected, else returns -1
 328  */
 329 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 330                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 331 {
 332         struct nand_chip *chip = mtd->priv;
 333         struct nand_bch_priv *bch = chip->priv;
 334         uint32_t eccbytes = chip->ecc.bytes;
 335         uint32_t error_count = 0, error_max;
 336         uint32_t error_loc[8];
 337         enum bch_level bch_type;
 338         uint32_t i, ecc_flag = 0;
 339         uint8_t count, err = 0;
 340         uint32_t byte_pos, bit_pos;
 341
 342         /* check calculated ecc */
 343         for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
 344                 if (calc_ecc[i] != 0x00)
 345                         ecc_flag = 1;
 346         }
 347         if (!ecc_flag)
 348                 return 0;
 349
 350         /* check for whether its a erased-page */
 351         ecc_flag = 0;
 352         for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
 353                 if (read_ecc[i] != 0xff)
 354                         ecc_flag = 1;
 355         }
 356         if (!ecc_flag)
 357                 return 0;
 358
 359         /*
 360          * while reading ECC result we read it in big endian.
 361          * Hence while loading to ELM we have rotate to get the right endian.
 362          */
 363         switch (bch->ecc_scheme) {
 364         case OMAP_ECC_BCH8_CODE_HW:
 365                 bch_type = BCH_8_BIT;
 366                 omap_reverse_list(calc_ecc, eccbytes - 1);
 367                 break;
 368         default:
 369                 return -EINVAL;
 370         }
 371         /* use elm module to check for errors */
 372         elm_config(bch_type);
 373         if (elm_check_error(calc_ecc, bch_type, &error_count, error_loc)) {
 374                 printf("nand: error: uncorrectable ECC errors\n");
 375                 return -EINVAL;
 376         }
 377         /* correct bch error */
 378         for (count = 0; count < error_count; count++) {
 379                 switch (bch->ecc_scheme) {
 380                 case OMAP_ECC_BCH8_CODE_HW:
 381                         /* 14th byte in ECC is reserved to match ROM layout */
 382                         error_max = SECTOR_BYTES + (eccbytes - 1);
 383                         break;
 384                 default:
 385                         return -EINVAL;
 386                 }
 387                 byte_pos = error_max - (error_loc[count] / 8) - 1;
 388                 bit_pos  = error_loc[count] % 8;
 389                 if (byte_pos < SECTOR_BYTES) {
 390                         dat[byte_pos] ^= 1 << bit_pos;
 391                         printf("nand: bit-flip corrected @data=%d\n", byte_pos);
 392                 } else if (byte_pos < error_max) {
 393                         read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
 394                         printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
 395                                                                 SECTOR_BYTES);
 396                 } else {
 397                         err = -EBADMSG;
 398                         printf("nand: error: invalid bit-flip location\n");
 399                 }
 400         }
 401         return (err) ? err : error_count;
 402 }
 403
 404 /**
 405  * omap_read_page_bch - hardware ecc based page read function
 406  * @mtd:        mtd info structure
 407  * @chip:       nand chip info structure
 408  * @buf:        buffer to store read data
 409  * @oob_required: caller expects OOB data read to chip->oob_poi
 410  * @page:       page number to read
 411  *
 412  */
 413 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 414                                 uint8_t *buf, int oob_required, int page)
 415 {
 416         int i, eccsize = chip->ecc.size;
 417         int eccbytes = chip->ecc.bytes;
 418         int eccsteps = chip->ecc.steps;
 419         uint8_t *p = buf;
 420         uint8_t *ecc_calc = chip->buffers->ecccalc;
 421         uint8_t *ecc_code = chip->buffers->ecccode;
 422         uint32_t *eccpos = chip->ecc.layout->eccpos;
 423         uint8_t *oob = chip->oob_poi;
 424         uint32_t data_pos;
 425         uint32_t oob_pos;
 426
 427         data_pos = 0;
 428         /* oob area start */
 429         oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
 430         oob += chip->ecc.layout->eccpos[0];
 431
 432         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
 433                                 oob += eccbytes) {
 434                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 435                 /* read data */
 436                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
 437                 chip->read_buf(mtd, p, eccsize);
 438
 439                 /* read respective ecc from oob area */
 440                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
 441                 chip->read_buf(mtd, oob, eccbytes);
 442                 /* read syndrome */
 443                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 444
 445                 data_pos += eccsize;
 446                 oob_pos += eccbytes;
 447         }
 448
 449         for (i = 0; i < chip->ecc.total; i++)
 450                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 451
 452         eccsteps = chip->ecc.steps;
 453         p = buf;
 454
 455         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 456                 int stat;
 457
 458                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 459                 if (stat < 0)
 460                         mtd->ecc_stats.failed++;
 461                 else
 462                         mtd->ecc_stats.corrected += stat;
 463         }
 464         return 0;
 465 }
 466 #endif /* CONFIG_NAND_OMAP_ELM */
 467
 468 /*
 469  * OMAP3 BCH8 support (with BCH library)
 470  */
 471 #ifdef CONFIG_BCH
 472 /**
 473  * omap_correct_data_bch_sw - Decode received data and correct errors
 474  * @mtd: MTD device structure
 475  * @data: page data
 476  * @read_ecc: ecc read from nand flash
 477  * @calc_ecc: ecc read from HW ECC registers
 478  */
 479 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 480                                  u_char *read_ecc, u_char *calc_ecc)
 481 {
 482         int i, count;
 483         /* cannot correct more than 8 errors */
 484         unsigned int errloc[8];
 485         struct nand_chip *chip = mtd->priv;
 486         struct nand_bch_priv *chip_priv = chip->priv;
 487         struct bch_control *bch = chip_priv->control;
 488
 489         count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
 490         if (count > 0) {
 491                 /* correct errors */
 492                 for (i = 0; i < count; i++) {
 493                         /* correct data only, not ecc bytes */
 494                         if (errloc[i] < 8*512)
 495                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
 496                         printf("corrected bitflip %u\n", errloc[i]);
 497 #ifdef DEBUG
 498                         puts("read_ecc: ");
 499                         /*
 500                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
 501                          * here!
 502                          */
 503                         for (i = 0; i < 13; i++)
 504                                 printf("%02x ", read_ecc[i]);
 505                         puts("\n");
 506                         puts("calc_ecc: ");
 507                         for (i = 0; i < 13; i++)
 508                                 printf("%02x ", calc_ecc[i]);
 509                         puts("\n");
 510 #endif
 511                 }
 512         } else if (count < 0) {
 513                 puts("ecc unrecoverable error\n");
 514         }
 515         return count;
 516 }
 517
 518 /**
 519  * omap_free_bch - Release BCH ecc resources
 520  * @mtd: MTD device structure
 521  */
 522 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 523 {
 524         struct nand_chip *chip = mtd->priv;
 525         struct nand_bch_priv *chip_priv = chip->priv;
 526         struct bch_control *bch = NULL;
 527
 528         if (chip_priv)
 529                 bch = chip_priv->control;
 530
 531         if (bch) {
 532                 free_bch(bch);
 533                 chip_priv->control = NULL;
 534         }
 535 }
 536 #endif /* CONFIG_BCH */
 537
 538 /**
 539  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
 540  * @nand: NAND chip device structure
 541  * @ecc_scheme: ecc scheme to configure
 542  * @pagesize: number of main-area bytes per page of NAND device
 543  * @oobsize: number of OOB/spare bytes per page of NAND device
 544  */
 545 static int omap_select_ecc_scheme(struct nand_chip *nand,
 546         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
 547         struct nand_bch_priv    *bch            = nand->priv;
 548         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
 549         int eccsteps = pagesize / SECTOR_BYTES;
 550         int i;
 551
 552         switch (ecc_scheme) {
 553         case OMAP_ECC_HAM1_CODE_SW:
 554                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
 555                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
 556                  * initialized in nand_scan_tail(), so just set ecc.mode */
 557                 bch_priv.control        = NULL;
 558                 nand->ecc.mode          = NAND_ECC_SOFT;
 559                 nand->ecc.layout        = NULL;
 560                 nand->ecc.size          = 0;
 561                 bch->ecc_scheme         = OMAP_ECC_HAM1_CODE_SW;
 562                 break;
 563
 564         case OMAP_ECC_HAM1_CODE_HW:
 565                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
 566                 /* check ecc-scheme requirements before updating ecc info */
 567                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 568                         printf("nand: error: insufficient OOB: require=%d\n", (
 569                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 570                         return -EINVAL;
 571                 }
 572                 bch_priv.control        = NULL;
 573                 /* populate ecc specific fields */
 574                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 575                 nand->ecc.mode          = NAND_ECC_HW;
 576                 nand->ecc.strength      = 1;
 577                 nand->ecc.size          = SECTOR_BYTES;
 578                 nand->ecc.bytes         = 3;
 579                 nand->ecc.hwctl         = omap_enable_hwecc;
 580                 nand->ecc.correct       = omap_correct_data;
 581                 nand->ecc.calculate     = omap_calculate_ecc;
 582                 /* define ecc-layout */
 583                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 584                 for (i = 0; i < ecclayout->eccbytes; i++) {
 585                         if (nand->options & NAND_BUSWIDTH_16)
 586                                 ecclayout->eccpos[i] = i + 2;
 587                         else
 588                                 ecclayout->eccpos[i] = i + 1;
 589                 }
 590                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 591                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 592                                                 BADBLOCK_MARKER_LENGTH;
 593                 bch->ecc_scheme         = OMAP_ECC_HAM1_CODE_HW;
 594                 break;
 595
 596         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 597 #ifdef CONFIG_BCH
 598                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
 599                 /* check ecc-scheme requirements before updating ecc info */
 600                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 601                         printf("nand: error: insufficient OOB: require=%d\n", (
 602                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 603                         return -EINVAL;
 604                 }
 605                 /* check if BCH S/W library can be used for error detection */
 606                 bch_priv.control = init_bch(13, 8, 0x201b);
 607                 if (!bch_priv.control) {
 608                         printf("nand: error: could not init_bch()\n");
 609                         return -ENODEV;
 610                 }
 611                 /* populate ecc specific fields */
 612                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 613                 nand->ecc.mode          = NAND_ECC_HW;
 614                 nand->ecc.strength      = 8;
 615                 nand->ecc.size          = SECTOR_BYTES;
 616                 nand->ecc.bytes         = 13;
 617                 nand->ecc.hwctl         = omap_enable_hwecc;
 618                 nand->ecc.correct       = omap_correct_data_bch_sw;
 619                 nand->ecc.calculate     = omap_calculate_ecc;
 620                 /* define ecc-layout */
 621                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 622                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
 623                 for (i = 1; i < ecclayout->eccbytes; i++) {
 624                         if (i % nand->ecc.bytes)
 625                                 ecclayout->eccpos[i] =
 626                                                 ecclayout->eccpos[i - 1] + 1;
 627                         else
 628                                 ecclayout->eccpos[i] =
 629                                                 ecclayout->eccpos[i - 1] + 2;
 630                 }
 631                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 632                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 633                                                 BADBLOCK_MARKER_LENGTH;
 634                 bch->ecc_scheme         = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
 635                 break;
 636 #else
 637                 printf("nand: error: CONFIG_BCH required for ECC\n");
 638                 return -EINVAL;
 639 #endif
 640
 641         case OMAP_ECC_BCH8_CODE_HW:
 642 #ifdef CONFIG_NAND_OMAP_ELM
 643                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
 644                 /* check ecc-scheme requirements before updating ecc info */
 645                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 646                         printf("nand: error: insufficient OOB: require=%d\n", (
 647                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 648                         return -EINVAL;
 649                 }
 650                 /* intialize ELM for ECC error detection */
 651                 elm_init();
 652                 /* populate ecc specific fields */
 653                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 654                 nand->ecc.mode          = NAND_ECC_HW;
 655                 nand->ecc.strength      = 8;
 656                 nand->ecc.size          = SECTOR_BYTES;
 657                 nand->ecc.bytes         = 14;
 658                 nand->ecc.hwctl         = omap_enable_hwecc;
 659                 nand->ecc.correct       = omap_correct_data_bch;
 660                 nand->ecc.calculate     = omap_calculate_ecc;
 661                 nand->ecc.read_page     = omap_read_page_bch;
 662                 /* define ecc-layout */
 663                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 664                 for (i = 0; i < ecclayout->eccbytes; i++)
 665                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 666                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 667                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 668                                                 BADBLOCK_MARKER_LENGTH;
 669                 bch->ecc_scheme         = OMAP_ECC_BCH8_CODE_HW;
 670                 break;
 671 #else
 672                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 673                 return -EINVAL;
 674 #endif
 675
 676         default:
 677                 debug("nand: error: ecc scheme not enabled or supported\n");
 678                 return -EINVAL;
 679         }
 680
 681         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
 682         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
 683                 nand->ecc.layout = ecclayout;
 684
 685         return 0;
 686 }
 687
 688 #ifndef CONFIG_SPL_BUILD
 689 /*
 690  * omap_nand_switch_ecc - switch the ECC operation between different engines
 691  * (h/w and s/w) and different algorithms (hamming and BCHx)
 692  *
 693  * @hardware            - true if one of the HW engines should be used
 694  * @eccstrength         - the number of bits that could be corrected
 695  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
 696  */
 697 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 698 {
 699         struct nand_chip *nand;
 700         struct mtd_info *mtd;
 701         int err = 0;
 702
 703         if (nand_curr_device < 0 ||
 704             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 705             !nand_info[nand_curr_device].name) {
 706                 printf("nand: error: no NAND devices found\n");
 707                 return -ENODEV;
 708         }
 709
 710         mtd = &nand_info[nand_curr_device];
 711         nand = mtd->priv;
 712         nand->options |= NAND_OWN_BUFFERS;
 713         nand->options &= ~NAND_SUBPAGE_READ;
 714         /* Setup the ecc configurations again */
 715         if (hardware) {
 716                 if (eccstrength == 1) {
 717                         err = omap_select_ecc_scheme(nand,
 718                                         OMAP_ECC_HAM1_CODE_HW,
 719                                         mtd->writesize, mtd->oobsize);
 720                 } else if (eccstrength == 8) {
 721                         err = omap_select_ecc_scheme(nand,
 722                                         OMAP_ECC_BCH8_CODE_HW,
 723                                         mtd->writesize, mtd->oobsize);
 724                 } else {
 725                         printf("nand: error: unsupported ECC scheme\n");
 726                         return -EINVAL;
 727                 }
 728         } else {
 729                 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 730                                         mtd->writesize, mtd->oobsize);
 731         }
 732
 733         /* Update NAND handling after ECC mode switch */
 734         if (!err)
 735                 err = nand_scan_tail(mtd);
 736         return err;
 737 }
 738 #endif /* CONFIG_SPL_BUILD */
 739
 740 /*
 741  * Board-specific NAND initialization. The following members of the
 742  * argument are board-specific:
 743  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
 744  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
 745  * - cmd_ctrl: hardwarespecific function for accesing control-lines
 746  * - waitfunc: hardwarespecific function for accesing device ready/busy line
 747  * - ecc.hwctl: function to enable (reset) hardware ecc generator
 748  * - ecc.mode: mode of ecc, see defines
 749  * - chip_delay: chip dependent delay for transfering data from array to
 750  *   read regs (tR)
 751  * - options: various chip options. They can partly be set to inform
 752  *   nand_scan about special functionality. See the defines for further
 753  *   explanation
 754  */
 755 int board_nand_init(struct nand_chip *nand)
 756 {
 757         int32_t gpmc_config = 0;
 758         cs = 0;
 759         int err = 0;
 760         /*
 761          * xloader/Uboot's gpmc configuration would have configured GPMC for
 762          * nand type of memory. The following logic scans and latches on to the
 763          * first CS with NAND type memory.
 764          * TBD: need to make this logic generic to handle multiple CS NAND
 765          * devices.
 766          */
 767         while (cs < GPMC_MAX_CS) {
 768                 /* Check if NAND type is set */
 769                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
 770                         /* Found it!! */
 771                         break;
 772                 }
 773                 cs++;
 774         }
 775         if (cs >= GPMC_MAX_CS) {
 776                 printf("nand: error: Unable to find NAND settings in "
 777                         "GPMC Configuration - quitting\n");
 778                 return -ENODEV;
 779         }
 780
 781         gpmc_config = readl(&gpmc_cfg->config);
 782         /* Disable Write protect */
 783         gpmc_config |= 0x10;
 784         writel(gpmc_config, &gpmc_cfg->config);
 785
 786         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 787         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 788         nand->priv      = &bch_priv;
 789         nand->cmd_ctrl  = omap_nand_hwcontrol;
 790         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
 791         /* If we are 16 bit dev, our gpmc config tells us that */
 792         if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
 793                 nand->options |= NAND_BUSWIDTH_16;
 794
 795         nand->chip_delay = 100;
 796         nand->ecc.layout = &omap_ecclayout;
 797
 798         /* select ECC scheme */
 799 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
 800         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
 801                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
 802 #else
 803         /* pagesize and oobsize are not required to configure sw ecc-scheme */
 804         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 805                         0, 0);
 806 #endif
 807         if (err)
 808                 return err;
 809
 810 #ifdef CONFIG_SPL_BUILD
 811         if (nand->options & NAND_BUSWIDTH_16)
 812                 nand->read_buf = nand_read_buf16;
 813         else
 814                 nand->read_buf = nand_read_buf;
 815         nand->dev_ready = omap_spl_dev_ready;
 816 #endif
 817
 818         return 0;
 819 }