mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemes
[karo-tx-uboot.git] / drivers / mtd / nand / omap_gpmc.c
1 /*
2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3  * Rohit Choraria <rohitkc@ti.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/errno.h>
11 #include <asm/arch/mem.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/omap_gpmc.h>
14 #include <linux/mtd/nand_ecc.h>
15 #include <linux/bch.h>
16 #include <linux/compiler.h>
17 #include <nand.h>
18 #include <asm/omap_elm.h>
19
20 #define BADBLOCK_MARKER_LENGTH  2
21 #define SECTOR_BYTES            512
22 #define ECCCLEAR                (0x1 << 8)
23 #define ECCRESULTREG1           (0x1 << 0)
24 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
25 #define BCH4_BIT_PAD            4
26
27 #ifdef CONFIG_BCH
28 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
29                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
30 #endif
31 static uint8_t cs;
32 static __maybe_unused struct nand_ecclayout omap_ecclayout;
33
34 /*
35  * omap_nand_hwcontrol - Set the address pointers corretly for the
36  *                      following address/data/command operation
37  */
38 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
39                                 uint32_t ctrl)
40 {
41         register struct nand_chip *this = mtd->priv;
42
43         /*
44          * Point the IO_ADDR to DATA and ADDRESS registers instead
45          * of chip address
46          */
47         switch (ctrl) {
48         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
49                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
50                 break;
51         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
52                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
53                 break;
54         case NAND_CTRL_CHANGE | NAND_NCE:
55                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
56                 break;
57         }
58
59         if (cmd != NAND_CMD_NONE)
60                 writeb(cmd, this->IO_ADDR_W);
61 }
62
63 #ifdef CONFIG_SPL_BUILD
64 /* Check wait pin as dev ready indicator */
65 int omap_spl_dev_ready(struct mtd_info *mtd)
66 {
67         return gpmc_cfg->status & (1 << 8);
68 }
69 #endif
70
71
72 /*
73  * gen_true_ecc - This function will generate true ECC value, which
74  * can be used when correcting data read from NAND flash memory core
75  *
76  * @ecc_buf:    buffer to store ecc code
77  *
78  * @return:     re-formatted ECC value
79  */
80 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
81 {
82         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
83                 ((ecc_buf[2] & 0x0F) << 8);
84 }
85
86 /*
87  * omap_correct_data - Compares the ecc read from nand spare area with ECC
88  * registers values and corrects one bit error if it has occured
89  * Further details can be had from OMAP TRM and the following selected links:
90  * http://en.wikipedia.org/wiki/Hamming_code
91  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
92  *
93  * @mtd:                 MTD device structure
94  * @dat:                 page data
95  * @read_ecc:            ecc read from nand flash
96  * @calc_ecc:            ecc read from ECC registers
97  *
98  * @return 0 if data is OK or corrected, else returns -1
99  */
100 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
101                                 uint8_t *read_ecc, uint8_t *calc_ecc)
102 {
103         uint32_t orig_ecc, new_ecc, res, hm;
104         uint16_t parity_bits, byte;
105         uint8_t bit;
106
107         /* Regenerate the orginal ECC */
108         orig_ecc = gen_true_ecc(read_ecc);
109         new_ecc = gen_true_ecc(calc_ecc);
110         /* Get the XOR of real ecc */
111         res = orig_ecc ^ new_ecc;
112         if (res) {
113                 /* Get the hamming width */
114                 hm = hweight32(res);
115                 /* Single bit errors can be corrected! */
116                 if (hm == 12) {
117                         /* Correctable data! */
118                         parity_bits = res >> 16;
119                         bit = (parity_bits & 0x7);
120                         byte = (parity_bits >> 3) & 0x1FF;
121                         /* Flip the bit to correct */
122                         dat[byte] ^= (0x1 << bit);
123                 } else if (hm == 1) {
124                         printf("Error: Ecc is wrong\n");
125                         /* ECC itself is corrupted */
126                         return 2;
127                 } else {
128                         /*
129                          * hm distance != parity pairs OR one, could mean 2 bit
130                          * error OR potentially be on a blank page..
131                          * orig_ecc: contains spare area data from nand flash.
132                          * new_ecc: generated ecc while reading data area.
133                          * Note: if the ecc = 0, all data bits from which it was
134                          * generated are 0xFF.
135                          * The 3 byte(24 bits) ecc is generated per 512byte
136                          * chunk of a page. If orig_ecc(from spare area)
137                          * is 0xFF && new_ecc(computed now from data area)=0x0,
138                          * this means that data area is 0xFF and spare area is
139                          * 0xFF. A sure sign of a erased page!
140                          */
141                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
142                                 return 0;
143                         printf("Error: Bad compare! failed\n");
144                         /* detected 2 bit error */
145                         return -1;
146                 }
147         }
148         return 0;
149 }
150
151 /*
152  * Generic BCH interface
153  */
154 struct nand_bch_priv {
155         uint8_t mode;
156         uint8_t type;
157         uint8_t nibbles;
158         struct bch_control *control;
159         enum omap_ecc ecc_scheme;
160 };
161
162 /* bch types */
163 #define ECC_BCH4        0
164 #define ECC_BCH8        1
165 #define ECC_BCH16       2
166
167 /* BCH nibbles for diff bch levels */
168 #define ECC_BCH4_NIBBLES        13
169 #define ECC_BCH8_NIBBLES        26
170 #define ECC_BCH16_NIBBLES       52
171
172 /*
173  * This can be a single instance cause all current users have only one NAND
174  * with nearly the same setup (BCH8, some with ELM and others with sw BCH
175  * library).
176  * When some users with other BCH strength will exists this have to change!
177  */
178 static __maybe_unused struct nand_bch_priv bch_priv = {
179         .type = ECC_BCH8,
180         .nibbles = ECC_BCH8_NIBBLES,
181         .control = NULL
182 };
183
184 /*
185  * omap_reverse_list - re-orders list elements in reverse order [internal]
186  * @list:       pointer to start of list
187  * @length:     length of list
188 */
189 void omap_reverse_list(u8 *list, unsigned int length)
190 {
191         unsigned int i, j;
192         unsigned int half_length = length / 2;
193         u8 tmp;
194         for (i = 0, j = length - 1; i < half_length; i++, j--) {
195                 tmp = list[i];
196                 list[i] = list[j];
197                 list[j] = tmp;
198         }
199 }
200
201 /*
202  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
203  * @mtd:        MTD device structure
204  * @mode:       Read/Write mode
205  */
206 __maybe_unused
207 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
208 {
209         struct nand_chip        *nand   = mtd->priv;
210         struct nand_bch_priv    *bch    = nand->priv;
211         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
212         unsigned int ecc_algo = 0;
213         unsigned int bch_type = 0;
214         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
215         u32 ecc_size_config_val = 0;
216         u32 ecc_config_val = 0;
217
218         /* configure GPMC for specific ecc-scheme */
219         switch (bch->ecc_scheme) {
220         case OMAP_ECC_HAM1_CODE_SW:
221                 return;
222         case OMAP_ECC_HAM1_CODE_HW:
223                 ecc_algo = 0x0;
224                 bch_type = 0x0;
225                 bch_wrapmode = 0x00;
226                 eccsize0 = 0xFF;
227                 eccsize1 = 0xFF;
228                 break;
229         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
230         case OMAP_ECC_BCH8_CODE_HW:
231                 ecc_algo = 0x1;
232                 bch_type = 0x1;
233                 if (mode == NAND_ECC_WRITE) {
234                         bch_wrapmode = 0x01;
235                         eccsize0 = 0;  /* extra bits in nibbles per sector */
236                         eccsize1 = 28; /* OOB bits in nibbles per sector */
237                 } else {
238                         bch_wrapmode = 0x01;
239                         eccsize0 = 26; /* ECC bits in nibbles per sector */
240                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
241                 }
242                 break;
243         default:
244                 return;
245         }
246         /* Clear ecc and enable bits */
247         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
248         /* Configure ecc size for BCH */
249         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
250         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
251
252         /* Configure device details for BCH engine */
253         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
254                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
255                         (bch_wrapmode << 8)     | /* wrap mode */
256                         (dev_width << 7)        | /* bus width */
257                         (0x0 << 4)              | /* number of sectors */
258                         (cs <<  1)              | /* ECC CS */
259                         (0x1));                   /* enable ECC */
260         writel(ecc_config_val, &gpmc_cfg->ecc_config);
261 }
262
263 /*
264  *  omap_calculate_ecc - Read ECC result
265  *  @mtd:       MTD structure
266  *  @dat:       unused
267  *  @ecc_code:  ecc_code buffer
268  *  Using noninverted ECC can be considered ugly since writing a blank
269  *  page ie. padding will clear the ECC bytes. This is no problem as
270  *  long nobody is trying to write data on the seemingly unused page.
271  *  Reading an erased page will produce an ECC mismatch between
272  *  generated and read ECC bytes that has to be dealt with separately.
273  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
274  *  is used, the result of read will be 0x0 while the ECC offsets of the
275  *  spare area will be 0xFF which will result in an ECC mismatch.
276  */
277 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
278                                 uint8_t *ecc_code)
279 {
280         struct nand_chip *chip = mtd->priv;
281         struct nand_bch_priv *bch = chip->priv;
282         uint32_t *ptr, val = 0;
283         int8_t i = 0, j;
284
285         switch (bch->ecc_scheme) {
286         case OMAP_ECC_HAM1_CODE_HW:
287                 val = readl(&gpmc_cfg->ecc1_result);
288                 ecc_code[0] = val & 0xFF;
289                 ecc_code[1] = (val >> 16) & 0xFF;
290                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
291                 break;
292 #ifdef CONFIG_BCH
293         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
294 #endif
295         case OMAP_ECC_BCH8_CODE_HW:
296                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
297                 val = readl(ptr);
298                 ecc_code[i++] = (val >>  0) & 0xFF;
299                 ptr--;
300                 for (j = 0; j < 3; j++) {
301                         val = readl(ptr);
302                         ecc_code[i++] = (val >> 24) & 0xFF;
303                         ecc_code[i++] = (val >> 16) & 0xFF;
304                         ecc_code[i++] = (val >>  8) & 0xFF;
305                         ecc_code[i++] = (val >>  0) & 0xFF;
306                         ptr--;
307                 }
308                 break;
309         default:
310                 return -EINVAL;
311         }
312         /* ECC scheme specific syndrome customizations */
313         switch (bch->ecc_scheme) {
314         case OMAP_ECC_HAM1_CODE_HW:
315                 break;
316 #ifdef CONFIG_BCH
317         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
318
319                 for (i = 0; i < chip->ecc.bytes; i++)
320                         *(ecc_code + i) = *(ecc_code + i) ^
321                                                 bch8_polynomial[i];
322                 break;
323 #endif
324         case OMAP_ECC_BCH8_CODE_HW:
325                 ecc_code[chip->ecc.bytes - 1] = 0x00;
326                 break;
327         default:
328                 return -EINVAL;
329         }
330         return 0;
331 }
332
333 #ifdef CONFIG_NAND_OMAP_ELM
334 /*
335  * omap_correct_data_bch - Compares the ecc read from nand spare area
336  * with ECC registers values and corrects one bit error if it has occured
337  *
338  * @mtd:        MTD device structure
339  * @dat:        page data
340  * @read_ecc:   ecc read from nand flash (ignored)
341  * @calc_ecc:   ecc read from ECC registers
342  *
343  * @return 0 if data is OK or corrected, else returns -1
344  */
345 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
346                                 uint8_t *read_ecc, uint8_t *calc_ecc)
347 {
348         struct nand_chip *chip = mtd->priv;
349         struct nand_bch_priv *bch = chip->priv;
350         uint32_t eccbytes = chip->ecc.bytes;
351         uint32_t error_count = 0, error_max;
352         uint32_t error_loc[8];
353         uint32_t i, ecc_flag = 0;
354         uint8_t count, err = 0;
355         uint32_t byte_pos, bit_pos;
356
357         /* check calculated ecc */
358         for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
359                 if (calc_ecc[i] != 0x00)
360                         ecc_flag = 1;
361         }
362         if (!ecc_flag)
363                 return 0;
364
365         /* check for whether its a erased-page */
366         ecc_flag = 0;
367         for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
368                 if (read_ecc[i] != 0xff)
369                         ecc_flag = 1;
370         }
371         if (!ecc_flag)
372                 return 0;
373
374         /*
375          * while reading ECC result we read it in big endian.
376          * Hence while loading to ELM we have rotate to get the right endian.
377          */
378         switch (bch->ecc_scheme) {
379         case OMAP_ECC_BCH8_CODE_HW:
380                 omap_reverse_list(calc_ecc, eccbytes - 1);
381                 break;
382         default:
383                 return -EINVAL;
384         }
385         /* use elm module to check for errors */
386         elm_config((enum bch_level)(bch->type));
387         if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) {
388                 printf("nand: error: uncorrectable ECC errors\n");
389                 return -EINVAL;
390         }
391         /* correct bch error */
392         for (count = 0; count < error_count; count++) {
393                 switch (bch->type) {
394                 case ECC_BCH8:
395                         /* 14th byte in ECC is reserved to match ROM layout */
396                         error_max = SECTOR_BYTES + (eccbytes - 1);
397                         break;
398                 default:
399                         return -EINVAL;
400                 }
401                 byte_pos = error_max - (error_loc[count] / 8) - 1;
402                 bit_pos  = error_loc[count] % 8;
403                 if (byte_pos < SECTOR_BYTES) {
404                         dat[byte_pos] ^= 1 << bit_pos;
405                         printf("nand: bit-flip corrected @data=%d\n", byte_pos);
406                 } else if (byte_pos < error_max) {
407                         read_ecc[byte_pos - SECTOR_BYTES] = 1 << bit_pos;
408                         printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
409                                                                 SECTOR_BYTES);
410                 } else {
411                         err = -EBADMSG;
412                         printf("nand: error: invalid bit-flip location\n");
413                 }
414         }
415         return (err) ? err : error_count;
416 }
417
418 /**
419  * omap_read_page_bch - hardware ecc based page read function
420  * @mtd:        mtd info structure
421  * @chip:       nand chip info structure
422  * @buf:        buffer to store read data
423  * @oob_required: caller expects OOB data read to chip->oob_poi
424  * @page:       page number to read
425  *
426  */
427 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
428                                 uint8_t *buf, int oob_required, int page)
429 {
430         int i, eccsize = chip->ecc.size;
431         int eccbytes = chip->ecc.bytes;
432         int eccsteps = chip->ecc.steps;
433         uint8_t *p = buf;
434         uint8_t *ecc_calc = chip->buffers->ecccalc;
435         uint8_t *ecc_code = chip->buffers->ecccode;
436         uint32_t *eccpos = chip->ecc.layout->eccpos;
437         uint8_t *oob = chip->oob_poi;
438         uint32_t data_pos;
439         uint32_t oob_pos;
440
441         data_pos = 0;
442         /* oob area start */
443         oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
444         oob += chip->ecc.layout->eccpos[0];
445
446         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
447                                 oob += eccbytes) {
448                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
449                 /* read data */
450                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
451                 chip->read_buf(mtd, p, eccsize);
452
453                 /* read respective ecc from oob area */
454                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
455                 chip->read_buf(mtd, oob, eccbytes);
456                 /* read syndrome */
457                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
458
459                 data_pos += eccsize;
460                 oob_pos += eccbytes;
461         }
462
463         for (i = 0; i < chip->ecc.total; i++)
464                 ecc_code[i] = chip->oob_poi[eccpos[i]];
465
466         eccsteps = chip->ecc.steps;
467         p = buf;
468
469         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
470                 int stat;
471
472                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
473                 if (stat < 0)
474                         mtd->ecc_stats.failed++;
475                 else
476                         mtd->ecc_stats.corrected += stat;
477         }
478         return 0;
479 }
480 #endif /* CONFIG_NAND_OMAP_ELM */
481
482 /*
483  * OMAP3 BCH8 support (with BCH library)
484  */
485 #ifdef CONFIG_BCH
486 /**
487  * omap_correct_data_bch_sw - Decode received data and correct errors
488  * @mtd: MTD device structure
489  * @data: page data
490  * @read_ecc: ecc read from nand flash
491  * @calc_ecc: ecc read from HW ECC registers
492  */
493 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
494                                  u_char *read_ecc, u_char *calc_ecc)
495 {
496         int i, count;
497         /* cannot correct more than 8 errors */
498         unsigned int errloc[8];
499         struct nand_chip *chip = mtd->priv;
500         struct nand_bch_priv *chip_priv = chip->priv;
501         struct bch_control *bch = chip_priv->control;
502
503         count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
504         if (count > 0) {
505                 /* correct errors */
506                 for (i = 0; i < count; i++) {
507                         /* correct data only, not ecc bytes */
508                         if (errloc[i] < 8*512)
509                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
510                         printf("corrected bitflip %u\n", errloc[i]);
511 #ifdef DEBUG
512                         puts("read_ecc: ");
513                         /*
514                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
515                          * here!
516                          */
517                         for (i = 0; i < 13; i++)
518                                 printf("%02x ", read_ecc[i]);
519                         puts("\n");
520                         puts("calc_ecc: ");
521                         for (i = 0; i < 13; i++)
522                                 printf("%02x ", calc_ecc[i]);
523                         puts("\n");
524 #endif
525                 }
526         } else if (count < 0) {
527                 puts("ecc unrecoverable error\n");
528         }
529         return count;
530 }
531
532 /**
533  * omap_free_bch - Release BCH ecc resources
534  * @mtd: MTD device structure
535  */
536 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
537 {
538         struct nand_chip *chip = mtd->priv;
539         struct nand_bch_priv *chip_priv = chip->priv;
540         struct bch_control *bch = NULL;
541
542         if (chip_priv)
543                 bch = chip_priv->control;
544
545         if (bch) {
546                 free_bch(bch);
547                 chip_priv->control = NULL;
548         }
549 }
550 #endif /* CONFIG_BCH */
551
552 /**
553  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
554  * @nand: NAND chip device structure
555  * @ecc_scheme: ecc scheme to configure
556  * @pagesize: number of main-area bytes per page of NAND device
557  * @oobsize: number of OOB/spare bytes per page of NAND device
558  */
559 static int omap_select_ecc_scheme(struct nand_chip *nand,
560         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
561         struct nand_bch_priv    *bch            = nand->priv;
562         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
563         int eccsteps = pagesize / SECTOR_BYTES;
564         int i;
565
566         switch (ecc_scheme) {
567         case OMAP_ECC_HAM1_CODE_SW:
568                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
569                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
570                  * initialized in nand_scan_tail(), so just set ecc.mode */
571                 bch_priv.control        = NULL;
572                 bch_priv.type           = 0;
573                 nand->ecc.mode          = NAND_ECC_SOFT;
574                 nand->ecc.layout        = NULL;
575                 nand->ecc.size          = 0;
576                 bch->ecc_scheme         = OMAP_ECC_HAM1_CODE_SW;
577                 break;
578
579         case OMAP_ECC_HAM1_CODE_HW:
580                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
581                 /* check ecc-scheme requirements before updating ecc info */
582                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
583                         printf("nand: error: insufficient OOB: require=%d\n", (
584                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
585                         return -EINVAL;
586                 }
587                 bch_priv.control        = NULL;
588                 bch_priv.type           = 0;
589                 /* populate ecc specific fields */
590                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
591                 nand->ecc.mode          = NAND_ECC_HW;
592                 nand->ecc.strength      = 1;
593                 nand->ecc.size          = SECTOR_BYTES;
594                 nand->ecc.bytes         = 3;
595                 nand->ecc.hwctl         = omap_enable_hwecc;
596                 nand->ecc.correct       = omap_correct_data;
597                 nand->ecc.calculate     = omap_calculate_ecc;
598                 /* define ecc-layout */
599                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
600                 for (i = 0; i < ecclayout->eccbytes; i++) {
601                         if (nand->options & NAND_BUSWIDTH_16)
602                                 ecclayout->eccpos[i] = i + 2;
603                         else
604                                 ecclayout->eccpos[i] = i + 1;
605                 }
606                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
607                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
608                                                 BADBLOCK_MARKER_LENGTH;
609                 bch->ecc_scheme         = OMAP_ECC_HAM1_CODE_HW;
610                 break;
611
612         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
613 #ifdef CONFIG_BCH
614                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
615                 /* check ecc-scheme requirements before updating ecc info */
616                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
617                         printf("nand: error: insufficient OOB: require=%d\n", (
618                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
619                         return -EINVAL;
620                 }
621                 /* check if BCH S/W library can be used for error detection */
622                 bch_priv.control = init_bch(13, 8, 0x201b);
623                 if (!bch_priv.control) {
624                         printf("nand: error: could not init_bch()\n");
625                         return -ENODEV;
626                 }
627                 bch_priv.type = ECC_BCH8;
628                 /* populate ecc specific fields */
629                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
630                 nand->ecc.mode          = NAND_ECC_HW;
631                 nand->ecc.strength      = 8;
632                 nand->ecc.size          = SECTOR_BYTES;
633                 nand->ecc.bytes         = 13;
634                 nand->ecc.hwctl         = omap_enable_hwecc;
635                 nand->ecc.correct       = omap_correct_data_bch_sw;
636                 nand->ecc.calculate     = omap_calculate_ecc;
637                 /* define ecc-layout */
638                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
639                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
640                 for (i = 1; i < ecclayout->eccbytes; i++) {
641                         if (i % nand->ecc.bytes)
642                                 ecclayout->eccpos[i] =
643                                                 ecclayout->eccpos[i - 1] + 1;
644                         else
645                                 ecclayout->eccpos[i] =
646                                                 ecclayout->eccpos[i - 1] + 2;
647                 }
648                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
649                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
650                                                 BADBLOCK_MARKER_LENGTH;
651                 bch->ecc_scheme         = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
652                 break;
653 #else
654                 printf("nand: error: CONFIG_BCH required for ECC\n");
655                 return -EINVAL;
656 #endif
657
658         case OMAP_ECC_BCH8_CODE_HW:
659 #ifdef CONFIG_NAND_OMAP_ELM
660                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
661                 /* check ecc-scheme requirements before updating ecc info */
662                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
663                         printf("nand: error: insufficient OOB: require=%d\n", (
664                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
665                         return -EINVAL;
666                 }
667                 /* intialize ELM for ECC error detection */
668                 elm_init();
669                 bch_priv.type           = ECC_BCH8;
670                 /* populate ecc specific fields */
671                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
672                 nand->ecc.mode          = NAND_ECC_HW;
673                 nand->ecc.strength      = 8;
674                 nand->ecc.size          = SECTOR_BYTES;
675                 nand->ecc.bytes         = 14;
676                 nand->ecc.hwctl         = omap_enable_hwecc;
677                 nand->ecc.correct       = omap_correct_data_bch;
678                 nand->ecc.calculate     = omap_calculate_ecc;
679                 nand->ecc.read_page     = omap_read_page_bch;
680                 /* define ecc-layout */
681                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
682                 for (i = 0; i < ecclayout->eccbytes; i++)
683                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
684                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
685                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
686                                                 BADBLOCK_MARKER_LENGTH;
687                 bch->ecc_scheme         = OMAP_ECC_BCH8_CODE_HW;
688                 break;
689 #else
690                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
691                 return -EINVAL;
692 #endif
693
694         default:
695                 debug("nand: error: ecc scheme not enabled or supported\n");
696                 return -EINVAL;
697         }
698
699         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
700         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
701                 nand->ecc.layout = ecclayout;
702
703         return 0;
704 }
705
706 #ifndef CONFIG_SPL_BUILD
707 /*
708  * omap_nand_switch_ecc - switch the ECC operation between different engines
709  * (h/w and s/w) and different algorithms (hamming and BCHx)
710  *
711  * @hardware            - true if one of the HW engines should be used
712  * @eccstrength         - the number of bits that could be corrected
713  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
714  */
715 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
716 {
717         struct nand_chip *nand;
718         struct mtd_info *mtd;
719         int err = 0;
720
721         if (nand_curr_device < 0 ||
722             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
723             !nand_info[nand_curr_device].name) {
724                 printf("nand: error: no NAND devices found\n");
725                 return -ENODEV;
726         }
727
728         mtd = &nand_info[nand_curr_device];
729         nand = mtd->priv;
730         nand->options |= NAND_OWN_BUFFERS;
731         nand->options &= ~NAND_SUBPAGE_READ;
732         /* Setup the ecc configurations again */
733         if (hardware) {
734                 if (eccstrength == 1) {
735                         err = omap_select_ecc_scheme(nand,
736                                         OMAP_ECC_HAM1_CODE_HW,
737                                         mtd->writesize, mtd->oobsize);
738                 } else if (eccstrength == 8) {
739                         err = omap_select_ecc_scheme(nand,
740                                         OMAP_ECC_BCH8_CODE_HW,
741                                         mtd->writesize, mtd->oobsize);
742                 } else {
743                         printf("nand: error: unsupported ECC scheme\n");
744                         return -EINVAL;
745                 }
746         } else {
747                 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
748                                         mtd->writesize, mtd->oobsize);
749         }
750
751         /* Update NAND handling after ECC mode switch */
752         if (!err)
753                 err = nand_scan_tail(mtd);
754         return err;
755 }
756 #endif /* CONFIG_SPL_BUILD */
757
758 /*
759  * Board-specific NAND initialization. The following members of the
760  * argument are board-specific:
761  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
762  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
763  * - cmd_ctrl: hardwarespecific function for accesing control-lines
764  * - waitfunc: hardwarespecific function for accesing device ready/busy line
765  * - ecc.hwctl: function to enable (reset) hardware ecc generator
766  * - ecc.mode: mode of ecc, see defines
767  * - chip_delay: chip dependent delay for transfering data from array to
768  *   read regs (tR)
769  * - options: various chip options. They can partly be set to inform
770  *   nand_scan about special functionality. See the defines for further
771  *   explanation
772  */
773 int board_nand_init(struct nand_chip *nand)
774 {
775         int32_t gpmc_config = 0;
776         cs = 0;
777         int err = 0;
778         /*
779          * xloader/Uboot's gpmc configuration would have configured GPMC for
780          * nand type of memory. The following logic scans and latches on to the
781          * first CS with NAND type memory.
782          * TBD: need to make this logic generic to handle multiple CS NAND
783          * devices.
784          */
785         while (cs < GPMC_MAX_CS) {
786                 /* Check if NAND type is set */
787                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
788                         /* Found it!! */
789                         break;
790                 }
791                 cs++;
792         }
793         if (cs >= GPMC_MAX_CS) {
794                 printf("nand: error: Unable to find NAND settings in "
795                         "GPMC Configuration - quitting\n");
796                 return -ENODEV;
797         }
798
799         gpmc_config = readl(&gpmc_cfg->config);
800         /* Disable Write protect */
801         gpmc_config |= 0x10;
802         writel(gpmc_config, &gpmc_cfg->config);
803
804         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
805         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
806         nand->priv      = &bch_priv;
807         nand->cmd_ctrl  = omap_nand_hwcontrol;
808         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
809         /* If we are 16 bit dev, our gpmc config tells us that */
810         if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
811                 nand->options |= NAND_BUSWIDTH_16;
812
813         nand->chip_delay = 100;
814         nand->ecc.layout = &omap_ecclayout;
815
816         /* select ECC scheme */
817 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
818         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
819                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
820 #else
821         /* pagesize and oobsize are not required to configure sw ecc-scheme */
822         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
823                         0, 0);
824 #endif
825         if (err)
826                 return err;
827
828 #ifdef CONFIG_SPL_BUILD
829         if (nand->options & NAND_BUSWIDTH_16)
830                 nand->read_buf = nand_read_buf16;
831         else
832                 nand->read_buf = nand_read_buf;
833         nand->dev_ready = omap_spl_dev_ready;
834 #endif
835
836         return 0;
837 }