ad5b0f17ccfa1d601d1c68e5065fdc52a4fbc1a7
[karo-tx-uboot.git] / drivers / mtd / nand / omap_gpmc.c
1 /*
2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3  * Rohit Choraria <rohitkc@ti.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/errno.h>
11 #include <asm/arch/mem.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/omap_gpmc.h>
14 #include <linux/mtd/nand_ecc.h>
15 #include <linux/bch.h>
16 #include <linux/compiler.h>
17 #include <nand.h>
18 #include <asm/omap_elm.h>
19
20 #define BADBLOCK_MARKER_LENGTH  2
21 #define SECTOR_BYTES            512
22 #define ECCCLEAR                (0x1 << 8)
23 #define ECCRESULTREG1           (0x1 << 0)
24 #ifdef CONFIG_BCH
25 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
26                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
27 #endif
28 static uint8_t cs;
29 static __maybe_unused struct nand_ecclayout omap_ecclayout;
30
31 /*
32  * omap_nand_hwcontrol - Set the address pointers corretly for the
33  *                      following address/data/command operation
34  */
35 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
36                                 uint32_t ctrl)
37 {
38         register struct nand_chip *this = mtd->priv;
39
40         /*
41          * Point the IO_ADDR to DATA and ADDRESS registers instead
42          * of chip address
43          */
44         switch (ctrl) {
45         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
46                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
47                 break;
48         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
49                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
50                 break;
51         case NAND_CTRL_CHANGE | NAND_NCE:
52                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
53                 break;
54         }
55
56         if (cmd != NAND_CMD_NONE)
57                 writeb(cmd, this->IO_ADDR_W);
58 }
59
60 #ifdef CONFIG_SPL_BUILD
61 /* Check wait pin as dev ready indicator */
62 int omap_spl_dev_ready(struct mtd_info *mtd)
63 {
64         return gpmc_cfg->status & (1 << 8);
65 }
66 #endif
67
68
69 /*
70  * gen_true_ecc - This function will generate true ECC value, which
71  * can be used when correcting data read from NAND flash memory core
72  *
73  * @ecc_buf:    buffer to store ecc code
74  *
75  * @return:     re-formatted ECC value
76  */
77 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
78 {
79         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
80                 ((ecc_buf[2] & 0x0F) << 8);
81 }
82
83 /*
84  * omap_correct_data - Compares the ecc read from nand spare area with ECC
85  * registers values and corrects one bit error if it has occured
86  * Further details can be had from OMAP TRM and the following selected links:
87  * http://en.wikipedia.org/wiki/Hamming_code
88  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
89  *
90  * @mtd:                 MTD device structure
91  * @dat:                 page data
92  * @read_ecc:            ecc read from nand flash
93  * @calc_ecc:            ecc read from ECC registers
94  *
95  * @return 0 if data is OK or corrected, else returns -1
96  */
97 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
98                                 uint8_t *read_ecc, uint8_t *calc_ecc)
99 {
100         uint32_t orig_ecc, new_ecc, res, hm;
101         uint16_t parity_bits, byte;
102         uint8_t bit;
103
104         /* Regenerate the orginal ECC */
105         orig_ecc = gen_true_ecc(read_ecc);
106         new_ecc = gen_true_ecc(calc_ecc);
107         /* Get the XOR of real ecc */
108         res = orig_ecc ^ new_ecc;
109         if (res) {
110                 /* Get the hamming width */
111                 hm = hweight32(res);
112                 /* Single bit errors can be corrected! */
113                 if (hm == 12) {
114                         /* Correctable data! */
115                         parity_bits = res >> 16;
116                         bit = (parity_bits & 0x7);
117                         byte = (parity_bits >> 3) & 0x1FF;
118                         /* Flip the bit to correct */
119                         dat[byte] ^= (0x1 << bit);
120                 } else if (hm == 1) {
121                         printf("Error: Ecc is wrong\n");
122                         /* ECC itself is corrupted */
123                         return 2;
124                 } else {
125                         /*
126                          * hm distance != parity pairs OR one, could mean 2 bit
127                          * error OR potentially be on a blank page..
128                          * orig_ecc: contains spare area data from nand flash.
129                          * new_ecc: generated ecc while reading data area.
130                          * Note: if the ecc = 0, all data bits from which it was
131                          * generated are 0xFF.
132                          * The 3 byte(24 bits) ecc is generated per 512byte
133                          * chunk of a page. If orig_ecc(from spare area)
134                          * is 0xFF && new_ecc(computed now from data area)=0x0,
135                          * this means that data area is 0xFF and spare area is
136                          * 0xFF. A sure sign of a erased page!
137                          */
138                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
139                                 return 0;
140                         printf("Error: Bad compare! failed\n");
141                         /* detected 2 bit error */
142                         return -1;
143                 }
144         }
145         return 0;
146 }
147
148 /*
149  * Generic BCH interface
150  */
151 struct nand_bch_priv {
152         uint8_t mode;
153         uint8_t type;
154         uint8_t nibbles;
155         struct bch_control *control;
156         enum omap_ecc ecc_scheme;
157 };
158
159 /* bch types */
160 #define ECC_BCH4        0
161 #define ECC_BCH8        1
162 #define ECC_BCH16       2
163
164 /* BCH nibbles for diff bch levels */
165 #define ECC_BCH4_NIBBLES        13
166 #define ECC_BCH8_NIBBLES        26
167 #define ECC_BCH16_NIBBLES       52
168
169 /*
170  * This can be a single instance cause all current users have only one NAND
171  * with nearly the same setup (BCH8, some with ELM and others with sw BCH
172  * library).
173  * When some users with other BCH strength will exists this have to change!
174  */
175 static __maybe_unused struct nand_bch_priv bch_priv = {
176         .type = ECC_BCH8,
177         .nibbles = ECC_BCH8_NIBBLES,
178         .control = NULL
179 };
180
181 /*
182  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
183  * @mtd:        MTD device structure
184  * @mode:       Read/Write mode
185  */
186 __maybe_unused
187 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
188 {
189         struct nand_chip        *nand   = mtd->priv;
190         struct nand_bch_priv    *bch    = nand->priv;
191         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
192         unsigned int ecc_algo = 0;
193         unsigned int bch_type = 0;
194         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
195         u32 ecc_size_config_val = 0;
196         u32 ecc_config_val = 0;
197
198         /* configure GPMC for specific ecc-scheme */
199         switch (bch->ecc_scheme) {
200         case OMAP_ECC_HAM1_CODE_SW:
201                 return;
202         case OMAP_ECC_HAM1_CODE_HW:
203                 ecc_algo = 0x0;
204                 bch_type = 0x0;
205                 bch_wrapmode = 0x00;
206                 eccsize0 = 0xFF;
207                 eccsize1 = 0xFF;
208                 break;
209         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
210         case OMAP_ECC_BCH8_CODE_HW:
211                 ecc_algo = 0x1;
212                 bch_type = 0x1;
213                 if (mode == NAND_ECC_WRITE) {
214                         bch_wrapmode = 0x01;
215                         eccsize0 = 0;  /* extra bits in nibbles per sector */
216                         eccsize1 = 28; /* OOB bits in nibbles per sector */
217                 } else {
218                         bch_wrapmode = 0x01;
219                         eccsize0 = 26; /* ECC bits in nibbles per sector */
220                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
221                 }
222                 break;
223         default:
224                 return;
225         }
226         /* Clear ecc and enable bits */
227         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
228         /* Configure ecc size for BCH */
229         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
230         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
231
232         /* Configure device details for BCH engine */
233         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
234                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
235                         (bch_wrapmode << 8)     | /* wrap mode */
236                         (dev_width << 7)        | /* bus width */
237                         (0x0 << 4)              | /* number of sectors */
238                         (cs <<  1)              | /* ECC CS */
239                         (0x1));                   /* enable ECC */
240         writel(ecc_config_val, &gpmc_cfg->ecc_config);
241 }
242
243 /*
244  *  omap_calculate_ecc - Read ECC result
245  *  @mtd:       MTD structure
246  *  @dat:       unused
247  *  @ecc_code:  ecc_code buffer
248  *  Using noninverted ECC can be considered ugly since writing a blank
249  *  page ie. padding will clear the ECC bytes. This is no problem as
250  *  long nobody is trying to write data on the seemingly unused page.
251  *  Reading an erased page will produce an ECC mismatch between
252  *  generated and read ECC bytes that has to be dealt with separately.
253  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
254  *  is used, the result of read will be 0x0 while the ECC offsets of the
255  *  spare area will be 0xFF which will result in an ECC mismatch.
256  */
257 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
258                                 uint8_t *ecc_code)
259 {
260         struct nand_chip *chip = mtd->priv;
261         struct nand_bch_priv *bch = chip->priv;
262         uint32_t *ptr, val = 0;
263         int8_t i = 0, j;
264
265         switch (bch->ecc_scheme) {
266         case OMAP_ECC_HAM1_CODE_HW:
267                 val = readl(&gpmc_cfg->ecc1_result);
268                 ecc_code[0] = val & 0xFF;
269                 ecc_code[1] = (val >> 16) & 0xFF;
270                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
271                 break;
272 #ifdef CONFIG_BCH
273         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
274 #endif
275         case OMAP_ECC_BCH8_CODE_HW:
276                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
277                 val = readl(ptr);
278                 ecc_code[i++] = (val >>  0) & 0xFF;
279                 ptr--;
280                 for (j = 0; j < 3; j++) {
281                         val = readl(ptr);
282                         ecc_code[i++] = (val >> 24) & 0xFF;
283                         ecc_code[i++] = (val >> 16) & 0xFF;
284                         ecc_code[i++] = (val >>  8) & 0xFF;
285                         ecc_code[i++] = (val >>  0) & 0xFF;
286                         ptr--;
287                 }
288                 break;
289         default:
290                 return -EINVAL;
291         }
292         /* ECC scheme specific syndrome customizations */
293         switch (bch->ecc_scheme) {
294         case OMAP_ECC_HAM1_CODE_HW:
295                 break;
296 #ifdef CONFIG_BCH
297         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
298
299                 for (i = 0; i < chip->ecc.bytes; i++)
300                         *(ecc_code + i) = *(ecc_code + i) ^
301                                                 bch8_polynomial[i];
302                 break;
303 #endif
304         case OMAP_ECC_BCH8_CODE_HW:
305                 ecc_code[chip->ecc.bytes - 1] = 0x00;
306                 break;
307         default:
308                 return -EINVAL;
309         }
310         return 0;
311 }
312
313 #ifdef CONFIG_NAND_OMAP_ELM
314 /*
315  * omap_rotate_ecc_bch - Rotate the syndrome bytes
316  *
317  * @mtd:        MTD device structure
318  * @calc_ecc:   ECC read from ECC registers
319  * @syndrome:   Rotated syndrome will be retuned in this array
320  *
321  */
322 static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
323                 uint8_t *syndrome)
324 {
325         struct nand_chip *chip = mtd->priv;
326         struct nand_bch_priv *bch = chip->priv;
327         uint8_t n_bytes = 0;
328         int8_t i, j;
329
330         switch (bch->type) {
331         case ECC_BCH4:
332                 n_bytes = 8;
333                 break;
334
335         case ECC_BCH16:
336                 n_bytes = 28;
337                 break;
338
339         case ECC_BCH8:
340         default:
341                 n_bytes = 13;
342                 break;
343         }
344
345         for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--)
346                 syndrome[i] =  calc_ecc[j];
347 }
348
349 /*
350  * omap_fix_errors_bch - Correct bch error in the data
351  *
352  * @mtd:        MTD device structure
353  * @data:       Data read from flash
354  * @error_count:Number of errors in data
355  * @error_loc:  Locations of errors in the data
356  *
357  */
358 static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
359                 uint32_t error_count, uint32_t *error_loc)
360 {
361         struct nand_chip *chip = mtd->priv;
362         struct nand_bch_priv *bch = chip->priv;
363         uint8_t count = 0;
364         uint32_t error_byte_pos;
365         uint32_t error_bit_mask;
366         uint32_t last_bit = (bch->nibbles * 4) - 1;
367
368         /* Flip all bits as specified by the error location array. */
369         /* FOR( each found error location flip the bit ) */
370         for (count = 0; count < error_count; count++) {
371                 if (error_loc[count] > last_bit) {
372                         /* Remove the ECC spare bits from correction. */
373                         error_loc[count] -= (last_bit + 1);
374                         /* Offset bit in data region */
375                         error_byte_pos = ((512 * 8) -
376                                         (error_loc[count]) - 1) / 8;
377                         /* Error Bit mask */
378                         error_bit_mask = 0x1 << (error_loc[count] % 8);
379                         /* Toggle the error bit to make the correction. */
380                         data[error_byte_pos] ^= error_bit_mask;
381                 }
382         }
383 }
384
385 /*
386  * omap_correct_data_bch - Compares the ecc read from nand spare area
387  * with ECC registers values and corrects one bit error if it has occured
388  *
389  * @mtd:        MTD device structure
390  * @dat:        page data
391  * @read_ecc:   ecc read from nand flash (ignored)
392  * @calc_ecc:   ecc read from ECC registers
393  *
394  * @return 0 if data is OK or corrected, else returns -1
395  */
396 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
397                                 uint8_t *read_ecc, uint8_t *calc_ecc)
398 {
399         struct nand_chip *chip = mtd->priv;
400         struct nand_bch_priv *bch = chip->priv;
401         uint8_t syndrome[28];
402         uint32_t error_count = 0;
403         uint32_t error_loc[8];
404         uint32_t i, ecc_flag;
405
406         ecc_flag = 0;
407         for (i = 0; i < chip->ecc.bytes; i++)
408                 if (read_ecc[i] != 0xff)
409                         ecc_flag = 1;
410
411         if (!ecc_flag)
412                 return 0;
413
414         elm_reset();
415         elm_config((enum bch_level)(bch->type));
416
417         /*
418          * while reading ECC result we read it in big endian.
419          * Hence while loading to ELM we have rotate to get the right endian.
420          */
421         omap_rotate_ecc_bch(mtd, calc_ecc, syndrome);
422
423         /* use elm module to check for errors */
424         if (elm_check_error(syndrome, bch->nibbles, &error_count,
425                                 error_loc) != 0) {
426                 printf("ECC: uncorrectable.\n");
427                 return -1;
428         }
429
430         /* correct bch error */
431         if (error_count > 0)
432                 omap_fix_errors_bch(mtd, dat, error_count, error_loc);
433
434         return 0;
435 }
436
437 /**
438  * omap_read_page_bch - hardware ecc based page read function
439  * @mtd:        mtd info structure
440  * @chip:       nand chip info structure
441  * @buf:        buffer to store read data
442  * @oob_required: caller expects OOB data read to chip->oob_poi
443  * @page:       page number to read
444  *
445  */
446 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
447                                 uint8_t *buf, int oob_required, int page)
448 {
449         int i, eccsize = chip->ecc.size;
450         int eccbytes = chip->ecc.bytes;
451         int eccsteps = chip->ecc.steps;
452         uint8_t *p = buf;
453         uint8_t *ecc_calc = chip->buffers->ecccalc;
454         uint8_t *ecc_code = chip->buffers->ecccode;
455         uint32_t *eccpos = chip->ecc.layout->eccpos;
456         uint8_t *oob = chip->oob_poi;
457         uint32_t data_pos;
458         uint32_t oob_pos;
459
460         data_pos = 0;
461         /* oob area start */
462         oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
463         oob += chip->ecc.layout->eccpos[0];
464
465         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
466                                 oob += eccbytes) {
467                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
468                 /* read data */
469                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
470                 chip->read_buf(mtd, p, eccsize);
471
472                 /* read respective ecc from oob area */
473                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
474                 chip->read_buf(mtd, oob, eccbytes);
475                 /* read syndrome */
476                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
477
478                 data_pos += eccsize;
479                 oob_pos += eccbytes;
480         }
481
482         for (i = 0; i < chip->ecc.total; i++)
483                 ecc_code[i] = chip->oob_poi[eccpos[i]];
484
485         eccsteps = chip->ecc.steps;
486         p = buf;
487
488         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
489                 int stat;
490
491                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
492                 if (stat < 0)
493                         mtd->ecc_stats.failed++;
494                 else
495                         mtd->ecc_stats.corrected += stat;
496         }
497         return 0;
498 }
499 #endif /* CONFIG_NAND_OMAP_ELM */
500
501 /*
502  * OMAP3 BCH8 support (with BCH library)
503  */
504 #ifdef CONFIG_BCH
505 /**
506  * omap_correct_data_bch_sw - Decode received data and correct errors
507  * @mtd: MTD device structure
508  * @data: page data
509  * @read_ecc: ecc read from nand flash
510  * @calc_ecc: ecc read from HW ECC registers
511  */
512 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
513                                  u_char *read_ecc, u_char *calc_ecc)
514 {
515         int i, count;
516         /* cannot correct more than 8 errors */
517         unsigned int errloc[8];
518         struct nand_chip *chip = mtd->priv;
519         struct nand_bch_priv *chip_priv = chip->priv;
520         struct bch_control *bch = chip_priv->control;
521
522         count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
523         if (count > 0) {
524                 /* correct errors */
525                 for (i = 0; i < count; i++) {
526                         /* correct data only, not ecc bytes */
527                         if (errloc[i] < 8*512)
528                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
529                         printf("corrected bitflip %u\n", errloc[i]);
530 #ifdef DEBUG
531                         puts("read_ecc: ");
532                         /*
533                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
534                          * here!
535                          */
536                         for (i = 0; i < 13; i++)
537                                 printf("%02x ", read_ecc[i]);
538                         puts("\n");
539                         puts("calc_ecc: ");
540                         for (i = 0; i < 13; i++)
541                                 printf("%02x ", calc_ecc[i]);
542                         puts("\n");
543 #endif
544                 }
545         } else if (count < 0) {
546                 puts("ecc unrecoverable error\n");
547         }
548         return count;
549 }
550
551 /**
552  * omap_free_bch - Release BCH ecc resources
553  * @mtd: MTD device structure
554  */
555 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
556 {
557         struct nand_chip *chip = mtd->priv;
558         struct nand_bch_priv *chip_priv = chip->priv;
559         struct bch_control *bch = NULL;
560
561         if (chip_priv)
562                 bch = chip_priv->control;
563
564         if (bch) {
565                 free_bch(bch);
566                 chip_priv->control = NULL;
567         }
568 }
569 #endif /* CONFIG_BCH */
570
571 /**
572  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
573  * @nand: NAND chip device structure
574  * @ecc_scheme: ecc scheme to configure
575  * @pagesize: number of main-area bytes per page of NAND device
576  * @oobsize: number of OOB/spare bytes per page of NAND device
577  */
578 static int omap_select_ecc_scheme(struct nand_chip *nand,
579         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
580         struct nand_bch_priv    *bch            = nand->priv;
581         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
582         int eccsteps = pagesize / SECTOR_BYTES;
583         int i;
584
585         switch (ecc_scheme) {
586         case OMAP_ECC_HAM1_CODE_SW:
587                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
588                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
589                  * initialized in nand_scan_tail(), so just set ecc.mode */
590                 bch_priv.control        = NULL;
591                 bch_priv.type           = 0;
592                 nand->ecc.mode          = NAND_ECC_SOFT;
593                 nand->ecc.layout        = NULL;
594                 nand->ecc.size          = 0;
595                 bch->ecc_scheme         = OMAP_ECC_HAM1_CODE_SW;
596                 break;
597
598         case OMAP_ECC_HAM1_CODE_HW:
599                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
600                 /* check ecc-scheme requirements before updating ecc info */
601                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
602                         printf("nand: error: insufficient OOB: require=%d\n", (
603                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
604                         return -EINVAL;
605                 }
606                 bch_priv.control        = NULL;
607                 bch_priv.type           = 0;
608                 /* populate ecc specific fields */
609                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
610                 nand->ecc.mode          = NAND_ECC_HW;
611                 nand->ecc.strength      = 1;
612                 nand->ecc.size          = SECTOR_BYTES;
613                 nand->ecc.bytes         = 3;
614                 nand->ecc.hwctl         = omap_enable_hwecc;
615                 nand->ecc.correct       = omap_correct_data;
616                 nand->ecc.calculate     = omap_calculate_ecc;
617                 /* define ecc-layout */
618                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
619                 for (i = 0; i < ecclayout->eccbytes; i++) {
620                         if (nand->options & NAND_BUSWIDTH_16)
621                                 ecclayout->eccpos[i] = i + 2;
622                         else
623                                 ecclayout->eccpos[i] = i + 1;
624                 }
625                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
626                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
627                                                 BADBLOCK_MARKER_LENGTH;
628                 bch->ecc_scheme         = OMAP_ECC_HAM1_CODE_HW;
629                 break;
630
631         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
632 #ifdef CONFIG_BCH
633                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
634                 /* check ecc-scheme requirements before updating ecc info */
635                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
636                         printf("nand: error: insufficient OOB: require=%d\n", (
637                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
638                         return -EINVAL;
639                 }
640                 /* check if BCH S/W library can be used for error detection */
641                 bch_priv.control = init_bch(13, 8, 0x201b);
642                 if (!bch_priv.control) {
643                         printf("nand: error: could not init_bch()\n");
644                         return -ENODEV;
645                 }
646                 bch_priv.type = ECC_BCH8;
647                 /* populate ecc specific fields */
648                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
649                 nand->ecc.mode          = NAND_ECC_HW;
650                 nand->ecc.strength      = 8;
651                 nand->ecc.size          = SECTOR_BYTES;
652                 nand->ecc.bytes         = 13;
653                 nand->ecc.hwctl         = omap_enable_hwecc;
654                 nand->ecc.correct       = omap_correct_data_bch_sw;
655                 nand->ecc.calculate     = omap_calculate_ecc;
656                 /* define ecc-layout */
657                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
658                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
659                 for (i = 1; i < ecclayout->eccbytes; i++) {
660                         if (i % nand->ecc.bytes)
661                                 ecclayout->eccpos[i] =
662                                                 ecclayout->eccpos[i - 1] + 1;
663                         else
664                                 ecclayout->eccpos[i] =
665                                                 ecclayout->eccpos[i - 1] + 2;
666                 }
667                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
668                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
669                                                 BADBLOCK_MARKER_LENGTH;
670                 bch->ecc_scheme         = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
671                 break;
672 #else
673                 printf("nand: error: CONFIG_BCH required for ECC\n");
674                 return -EINVAL;
675 #endif
676
677         case OMAP_ECC_BCH8_CODE_HW:
678 #ifdef CONFIG_NAND_OMAP_ELM
679                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
680                 /* check ecc-scheme requirements before updating ecc info */
681                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
682                         printf("nand: error: insufficient OOB: require=%d\n", (
683                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
684                         return -EINVAL;
685                 }
686                 /* intialize ELM for ECC error detection */
687                 elm_init();
688                 bch_priv.type           = ECC_BCH8;
689                 /* populate ecc specific fields */
690                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
691                 nand->ecc.mode          = NAND_ECC_HW;
692                 nand->ecc.strength      = 8;
693                 nand->ecc.size          = SECTOR_BYTES;
694                 nand->ecc.bytes         = 14;
695                 nand->ecc.hwctl         = omap_enable_hwecc;
696                 nand->ecc.correct       = omap_correct_data_bch;
697                 nand->ecc.calculate     = omap_calculate_ecc;
698                 nand->ecc.read_page     = omap_read_page_bch;
699                 /* define ecc-layout */
700                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
701                 for (i = 0; i < ecclayout->eccbytes; i++)
702                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
703                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
704                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
705                                                 BADBLOCK_MARKER_LENGTH;
706                 bch->ecc_scheme         = OMAP_ECC_BCH8_CODE_HW;
707                 break;
708 #else
709                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
710                 return -EINVAL;
711 #endif
712
713         default:
714                 debug("nand: error: ecc scheme not enabled or supported\n");
715                 return -EINVAL;
716         }
717
718         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
719         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
720                 nand->ecc.layout = ecclayout;
721
722         return 0;
723 }
724
725 #ifndef CONFIG_SPL_BUILD
726 /*
727  * omap_nand_switch_ecc - switch the ECC operation between different engines
728  * (h/w and s/w) and different algorithms (hamming and BCHx)
729  *
730  * @hardware            - true if one of the HW engines should be used
731  * @eccstrength         - the number of bits that could be corrected
732  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
733  */
734 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
735 {
736         struct nand_chip *nand;
737         struct mtd_info *mtd;
738         int err = 0;
739
740         if (nand_curr_device < 0 ||
741             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
742             !nand_info[nand_curr_device].name) {
743                 printf("nand: error: no NAND devices found\n");
744                 return -ENODEV;
745         }
746
747         mtd = &nand_info[nand_curr_device];
748         nand = mtd->priv;
749         nand->options |= NAND_OWN_BUFFERS;
750         nand->options &= ~NAND_SUBPAGE_READ;
751         /* Setup the ecc configurations again */
752         if (hardware) {
753                 if (eccstrength == 1) {
754                         err = omap_select_ecc_scheme(nand,
755                                         OMAP_ECC_HAM1_CODE_HW,
756                                         mtd->writesize, mtd->oobsize);
757                 } else if (eccstrength == 8) {
758                         err = omap_select_ecc_scheme(nand,
759                                         OMAP_ECC_BCH8_CODE_HW,
760                                         mtd->writesize, mtd->oobsize);
761                 } else {
762                         printf("nand: error: unsupported ECC scheme\n");
763                         return -EINVAL;
764                 }
765         } else {
766                 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
767                                         mtd->writesize, mtd->oobsize);
768         }
769
770         /* Update NAND handling after ECC mode switch */
771         if (!err)
772                 err = nand_scan_tail(mtd);
773         return err;
774 }
775 #endif /* CONFIG_SPL_BUILD */
776
777 /*
778  * Board-specific NAND initialization. The following members of the
779  * argument are board-specific:
780  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
781  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
782  * - cmd_ctrl: hardwarespecific function for accesing control-lines
783  * - waitfunc: hardwarespecific function for accesing device ready/busy line
784  * - ecc.hwctl: function to enable (reset) hardware ecc generator
785  * - ecc.mode: mode of ecc, see defines
786  * - chip_delay: chip dependent delay for transfering data from array to
787  *   read regs (tR)
788  * - options: various chip options. They can partly be set to inform
789  *   nand_scan about special functionality. See the defines for further
790  *   explanation
791  */
792 int board_nand_init(struct nand_chip *nand)
793 {
794         int32_t gpmc_config = 0;
795         cs = 0;
796         int err = 0;
797         /*
798          * xloader/Uboot's gpmc configuration would have configured GPMC for
799          * nand type of memory. The following logic scans and latches on to the
800          * first CS with NAND type memory.
801          * TBD: need to make this logic generic to handle multiple CS NAND
802          * devices.
803          */
804         while (cs < GPMC_MAX_CS) {
805                 /* Check if NAND type is set */
806                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
807                         /* Found it!! */
808                         break;
809                 }
810                 cs++;
811         }
812         if (cs >= GPMC_MAX_CS) {
813                 printf("nand: error: Unable to find NAND settings in "
814                         "GPMC Configuration - quitting\n");
815                 return -ENODEV;
816         }
817
818         gpmc_config = readl(&gpmc_cfg->config);
819         /* Disable Write protect */
820         gpmc_config |= 0x10;
821         writel(gpmc_config, &gpmc_cfg->config);
822
823         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
824         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
825         nand->priv      = &bch_priv;
826         nand->cmd_ctrl  = omap_nand_hwcontrol;
827         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
828         /* If we are 16 bit dev, our gpmc config tells us that */
829         if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
830                 nand->options |= NAND_BUSWIDTH_16;
831
832         nand->chip_delay = 100;
833         nand->ecc.layout = &omap_ecclayout;
834
835         /* select ECC scheme */
836 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
837         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
838                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
839 #else
840         /* pagesize and oobsize are not required to configure sw ecc-scheme */
841         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
842                         0, 0);
843 #endif
844         if (err)
845                 return err;
846
847 #ifdef CONFIG_SPL_BUILD
848         if (nand->options & NAND_BUSWIDTH_16)
849                 nand->read_buf = nand_read_buf16;
850         else
851                 nand->read_buf = nand_read_buf;
852         nand->dev_ready = omap_spl_dev_ready;
853 #endif
854
855         return 0;
856 }