drivers/net/cpsw.c

   1 /*
   2  * CPSW Ethernet Switch Driver
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <common.h>
  23 #include <command.h>
  24 #include <net.h>
  25 #include <miiphy.h>
  26 #include <malloc.h>
  27 #include <net.h>
  28 #include <netdev.h>
  29 #include <asm/errno.h>
  30 #include <asm/io.h>
  31 #include <asm/arch/cpu.h>
  32
  33 #define BITMASK(bits)           ((1 << (bits)) - 1)
  34 #define PHY_REG_MASK            0x1f
  35 #define PHY_ID_MASK             0x1f
  36 #define NUM_DESCS               (PKTBUFSRX * 2)
  37 #define PKT_MIN                 60
  38 #define PKT_MAX                 (1500 + 14 + 4 + 4)
  39
  40 /* DMA Registers */
  41 #define CPDMA_TXCONTROL         0x004
  42 #define CPDMA_RXCONTROL         0x014
  43 #define CPDMA_SOFTRESET         0x01c
  44 #define CPDMA_RXFREE            0x0e0
  45 #define CPDMA_TXHDP_VER1        0x100
  46 #define CPDMA_TXHDP_VER2        0x200
  47 #define CPDMA_RXHDP_VER1        0x120
  48 #define CPDMA_RXHDP_VER2        0x220
  49 #define CPDMA_TXCP_VER1         0x140
  50 #define CPDMA_TXCP_VER2         0x240
  51 #define CPDMA_RXCP_VER1         0x160
  52 #define CPDMA_RXCP_VER2         0x260
  53
  54 /* Descriptor mode bits */
  55 #define CPDMA_DESC_SOP          BIT(31)
  56 #define CPDMA_DESC_EOP          BIT(30)
  57 #define CPDMA_DESC_OWNER        BIT(29)
  58 #define CPDMA_DESC_EOQ          BIT(28)
  59
  60 #ifndef CONFIG_SYS_CACHELINE_SIZE
  61 #define CONFIG_SYS_CACHELINE_SIZE       64
  62 #endif
  63
  64 struct cpsw_mdio_regs {
  65         u32     version;
  66         u32     control;
  67 #define CONTROL_IDLE            (1 << 31)
  68 #define CONTROL_ENABLE          (1 << 30)
  69
  70         u32     alive;
  71         u32     link;
  72         u32     linkintraw;
  73         u32     linkintmasked;
  74         u32     __reserved_0[2];
  75         u32     userintraw;
  76         u32     userintmasked;
  77         u32     userintmaskset;
  78         u32     userintmaskclr;
  79         u32     __reserved_1[20];
  80
  81         struct {
  82                 u32 access;
  83                 u32 physel;
  84 #define USERACCESS_GO           (1 << 31)
  85 #define USERACCESS_WRITE        (1 << 30)
  86 #define USERACCESS_ACK          (1 << 29)
  87 #define USERACCESS_READ         0
  88 #define USERACCESS_DATA         0xffff
  89         } user[0];
  90 };
  91
  92 struct cpsw_regs {
  93         u32     id_ver;
  94         u32     control;
  95         u32     soft_reset;
  96         u32     stat_port_en;
  97         u32     ptype;
  98 };
  99
 100 struct cpsw_slave_regs {
 101         u32     max_blks;
 102         u32     blk_cnt;
 103         u32     flow_thresh;
 104         u32     port_vlan;
 105         u32     tx_pri_map;
 106         u32     ts_seq_mtype;
 107 #ifdef CONFIG_TI814X
 108         u32     ts_ctl;
 109         u32     ts_seq_ltype;
 110         u32     ts_vlan;
 111 #endif
 112         u32     sa_lo;
 113         u32     sa_hi;
 114 };
 115
 116 struct cpsw_host_regs {
 117         u32     max_blks;
 118         u32     blk_cnt;
 119         u32     flow_thresh;
 120         u32     port_vlan;
 121         u32     tx_pri_map;
 122         u32     cpdma_tx_pri_map;
 123         u32     cpdma_rx_chan_map;
 124 };
 125
 126 struct cpsw_sliver_regs {
 127         u32     id_ver;
 128         u32     mac_control;
 129         u32     mac_status;
 130         u32     soft_reset;
 131         u32     rx_maxlen;
 132         u32     __reserved_0;
 133         u32     rx_pause;
 134         u32     tx_pause;
 135         u32     __reserved_1;
 136         u32     rx_pri_map;
 137 };
 138
 139 #define ALE_ENTRY_BITS          68
 140 #define ALE_ENTRY_WORDS         DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
 141
 142 /* ALE Registers */
 143 #define ALE_CONTROL             0x08
 144 #define ALE_UNKNOWNVLAN         0x18
 145 #define ALE_TABLE_CONTROL       0x20
 146 #define ALE_TABLE               0x34
 147 #define ALE_PORTCTL             0x40
 148
 149 #define ALE_TABLE_WRITE         BIT(31)
 150
 151 #define ALE_TYPE_FREE                   0
 152 #define ALE_TYPE_ADDR                   1
 153 #define ALE_TYPE_VLAN                   2
 154 #define ALE_TYPE_VLAN_ADDR              3
 155
 156 #define ALE_UCAST_PERSISTANT            0
 157 #define ALE_UCAST_UNTOUCHED             1
 158 #define ALE_UCAST_OUI                   2
 159 #define ALE_UCAST_TOUCHED               3
 160
 161 #define ALE_MCAST_FWD                   0
 162 #define ALE_MCAST_BLOCK_LEARN_FWD       1
 163 #define ALE_MCAST_FWD_LEARN             2
 164 #define ALE_MCAST_FWD_2                 3
 165
 166 enum cpsw_ale_port_state {
 167         ALE_PORT_STATE_DISABLE  = 0x00,
 168         ALE_PORT_STATE_BLOCK    = 0x01,
 169         ALE_PORT_STATE_LEARN    = 0x02,
 170         ALE_PORT_STATE_FORWARD  = 0x03,
 171 };
 172
 173 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
 174 #define ALE_SECURE      1
 175 #define ALE_BLOCKED     2
 176
 177 struct cpsw_slave {
 178         struct cpsw_slave_regs          *regs;
 179         struct cpsw_sliver_regs         *sliver;
 180         int                             slave_num;
 181         u32                             mac_control;
 182         struct cpsw_slave_data          *data;
 183 };
 184
 185 struct cpdma_desc {
 186         /* hardware fields */
 187         u32                     hw_next;
 188         u32                     hw_buffer;
 189         u32                     hw_len;
 190         u32                     hw_mode;
 191 } __attribute__((aligned(CONFIG_SYS_CACHELINE_SIZE)));
 192
 193 struct cpsw_desc {
 194         volatile void *sw_buffer;
 195         struct cpsw_desc *next;
 196         struct cpdma_desc *dma_desc;
 197 };
 198
 199 struct cpdma_chan {
 200         struct cpsw_desc        *head, *tail;
 201         void                    *hdp, *cp, *rxfree;
 202 };
 203
 204 #define desc_write(desc, fld, val)      __raw_writel((u32)(val), &(desc)->dma_desc->fld)
 205 #define desc_read(desc, fld)            __raw_readl(&(desc)->dma_desc->fld)
 206 #define desc_read_ptr(desc, fld)        ((void *)__raw_readl(&(desc)->dma_desc->fld))
 207
 208 #define chan_write(chan, fld, val)      __raw_writel((u32)(val), (chan)->fld)
 209 #define chan_read(chan, fld)            __raw_readl((chan)->fld)
 210 #define chan_read_ptr(chan, fld)        ((void *)__raw_readl((chan)->fld))
 211
 212 struct cpsw_priv {
 213         struct eth_device               *dev;
 214         struct cpsw_platform_data       *data;
 215         int                             host_port;
 216
 217         struct cpsw_regs                *regs;
 218         void                            *dma_regs;
 219         struct cpsw_host_regs           *host_port_regs;
 220         void                            *ale_regs;
 221
 222         struct cpsw_desc                descs[NUM_DESCS];
 223         struct cpsw_desc                *desc_free;
 224         struct cpdma_chan               rx_chan, tx_chan;
 225
 226         struct cpsw_slave               *slaves;
 227 };
 228
 229 #define for_each_slave(priv, func, arg...)      \
 230         do {                                                            \
 231                 int idx;                                                \
 232                 for (idx = 0; idx < (priv)->data->slaves; idx++)        \
 233                         (func)((priv)->slaves + idx, ##arg);            \
 234         } while (0)
 235
 236 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
 237 {
 238         int idx;
 239
 240         idx    = start / 32;
 241         start -= idx * 32;
 242         idx    = 2 - idx; /* flip */
 243         return (ale_entry[idx] >> start) & BITMASK(bits);
 244 }
 245
 246 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
 247                                       u32 value)
 248 {
 249         int idx;
 250
 251         value &= BITMASK(bits);
 252         idx    = start / 32;
 253         start -= idx * 32;
 254         idx    = 2 - idx; /* flip */
 255         ale_entry[idx] &= ~(BITMASK(bits) << start);
 256         ale_entry[idx] |=  (value << start);
 257 }
 258
 259 #define DEFINE_ALE_FIELD(name, start, bits)                             \
 260 static inline int cpsw_ale_get_##name(u32 *ale_entry)                   \
 261 {                                                                       \
 262         return cpsw_ale_get_field(ale_entry, start, bits);              \
 263 }                                                                       \
 264 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)       \
 265 {                                                                       \
 266         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 267 }
 268
 269 DEFINE_ALE_FIELD(entry_type,            60,     2)
 270 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 271 DEFINE_ALE_FIELD(port_mask,             66,     3)
 272 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 273 DEFINE_ALE_FIELD(port_num,              66,     2)
 274 DEFINE_ALE_FIELD(blocked,               65,     1)
 275 DEFINE_ALE_FIELD(secure,                64,     1)
 276 DEFINE_ALE_FIELD(mcast,                 40,     1)
 277
 278 /* The MAC address field in the ALE entry cannot be macroized as above */
 279 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 280 {
 281         int i;
 282
 283         for (i = 0; i < 6; i++)
 284                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 285 }
 286
 287 static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
 288 {
 289         int i;
 290
 291         for (i = 0; i < 6; i++)
 292                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 293 }
 294
 295 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 296 {
 297         int i;
 298
 299         __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
 300
 301         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 302                 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
 303
 304         return idx;
 305 }
 306
 307 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 308 {
 309         int i;
 310
 311         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 312                 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
 313
 314         __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
 315
 316         return idx;
 317 }
 318
 319 static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr)
 320 {
 321         u32 ale_entry[ALE_ENTRY_WORDS];
 322         int type, idx;
 323
 324         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 325                 u8 entry_addr[6];
 326
 327                 cpsw_ale_read(priv, idx, ale_entry);
 328                 type = cpsw_ale_get_entry_type(ale_entry);
 329                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 330                         continue;
 331                 cpsw_ale_get_addr(ale_entry, entry_addr);
 332                 if (memcmp(entry_addr, addr, 6) == 0)
 333                         return idx;
 334         }
 335         return -ENOENT;
 336 }
 337
 338 static int cpsw_ale_match_free(struct cpsw_priv *priv)
 339 {
 340         u32 ale_entry[ALE_ENTRY_WORDS];
 341         int type, idx;
 342
 343         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 344                 cpsw_ale_read(priv, idx, ale_entry);
 345                 type = cpsw_ale_get_entry_type(ale_entry);
 346                 if (type == ALE_TYPE_FREE)
 347                         return idx;
 348         }
 349         return -ENOENT;
 350 }
 351
 352 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
 353 {
 354         u32 ale_entry[ALE_ENTRY_WORDS];
 355         int type, idx;
 356
 357         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 358                 cpsw_ale_read(priv, idx, ale_entry);
 359                 type = cpsw_ale_get_entry_type(ale_entry);
 360                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 361                         continue;
 362                 if (cpsw_ale_get_mcast(ale_entry))
 363                         continue;
 364                 type = cpsw_ale_get_ucast_type(ale_entry);
 365                 if (type != ALE_UCAST_PERSISTANT &&
 366                     type != ALE_UCAST_OUI)
 367                         return idx;
 368         }
 369         return -ENOENT;
 370 }
 371
 372 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr,
 373                               int port, int flags)
 374 {
 375         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 376         int idx;
 377
 378         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 379         cpsw_ale_set_addr(ale_entry, addr);
 380         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 381         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 382         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 383         cpsw_ale_set_port_num(ale_entry, port);
 384
 385         idx = cpsw_ale_match_addr(priv, addr);
 386         if (idx < 0)
 387                 idx = cpsw_ale_match_free(priv);
 388         if (idx < 0)
 389                 idx = cpsw_ale_find_ageable(priv);
 390         if (idx < 0)
 391                 return -ENOMEM;
 392
 393         cpsw_ale_write(priv, idx, ale_entry);
 394         return 0;
 395 }
 396
 397 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask)
 398 {
 399         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 400         int idx, mask;
 401
 402         idx = cpsw_ale_match_addr(priv, addr);
 403         if (idx >= 0)
 404                 cpsw_ale_read(priv, idx, ale_entry);
 405
 406         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 407         cpsw_ale_set_addr(ale_entry, addr);
 408         cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
 409
 410         mask = cpsw_ale_get_port_mask(ale_entry);
 411         port_mask |= mask;
 412         cpsw_ale_set_port_mask(ale_entry, port_mask);
 413
 414         if (idx < 0)
 415                 idx = cpsw_ale_match_free(priv);
 416         if (idx < 0)
 417                 idx = cpsw_ale_find_ageable(priv);
 418         if (idx < 0)
 419                 return -ENOMEM;
 420
 421         cpsw_ale_write(priv, idx, ale_entry);
 422         return 0;
 423 }
 424
 425 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
 426 {
 427         u32 tmp, mask = BIT(bit);
 428
 429         tmp  = __raw_readl(priv->ale_regs + ALE_CONTROL);
 430         tmp &= ~mask;
 431         tmp |= val ? mask : 0;
 432         __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
 433 }
 434
 435 #define cpsw_ale_enable(priv, val)      cpsw_ale_control(priv, 31, val)
 436 #define cpsw_ale_clear(priv, val)       cpsw_ale_control(priv, 30, val)
 437 #define cpsw_ale_vlan_aware(priv, val)  cpsw_ale_control(priv,  2, val)
 438
 439 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
 440                                        int val)
 441 {
 442         int offset = ALE_PORTCTL + 4 * port;
 443         u32 tmp, mask = 0x3;
 444
 445         tmp  = __raw_readl(priv->ale_regs + offset);
 446         tmp &= ~mask;
 447         tmp |= val & 0x3;
 448         __raw_writel(tmp, priv->ale_regs + offset);
 449 }
 450
 451 static struct cpsw_mdio_regs *mdio_regs;
 452
 453 /* wait until hardware is ready for another user access */
 454 static inline u32 wait_for_user_access(void)
 455 {
 456         int timeout = 1000;
 457         u32 reg;
 458
 459         while ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO) {
 460                 udelay(1);
 461                 if (--timeout <= 0) {
 462                         printf("TIMEOUT waiting for USERACCESS_GO\n");
 463                         return -1;
 464                 }
 465         }
 466
 467         return reg;
 468 }
 469
 470 /* wait until hardware state machine is idle */
 471 static inline void wait_for_idle(void)
 472 {
 473         int timeout = 1000;
 474
 475         while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0) {
 476                 if (--timeout <= 0) {
 477                         printf("TIMEOUT waiting for state machine idle\n");
 478                         break;
 479                 }
 480                 udelay(1);
 481         }
 482 }
 483
 484 static int cpsw_mdio_read(const char *devname, unsigned char phy_id,
 485                           unsigned char phy_reg, unsigned short *data)
 486 {
 487         u32 reg;
 488
 489         if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
 490                 return -EINVAL;
 491
 492         wait_for_user_access();
 493         reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
 494                (phy_id << 16));
 495         __raw_writel(reg, &mdio_regs->user[0].access);
 496         reg = wait_for_user_access();
 497
 498         *data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
 499         return (reg & USERACCESS_ACK) ? 0 : -EIO;
 500 }
 501
 502 static int cpsw_mdio_write(const char *devname, unsigned char phy_id,
 503                            unsigned char phy_reg, unsigned short data)
 504 {
 505         u32 reg;
 506
 507         if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
 508                 return -EINVAL;
 509
 510         wait_for_user_access();
 511         reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
 512                    (phy_id << 16) | (data & USERACCESS_DATA));
 513         __raw_writel(reg, &mdio_regs->user[0].access);
 514         wait_for_user_access();
 515
 516         return 0;
 517 }
 518
 519 static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
 520 {
 521         mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
 522
 523         /* set enable and clock divider */
 524         __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
 525
 526         /*
 527          * wait for scan logic to settle:
 528          * the scan time consists of (a) a large fixed component, and (b) a
 529          * small component that varies with the mii bus frequency.  These
 530          * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
 531          * silicon.  Since the effect of (b) was found to be largely
 532          * negligible, we keep things simple here.
 533          */
 534         udelay(1000);
 535
 536         miiphy_register(name, cpsw_mdio_read, cpsw_mdio_write);
 537 }
 538
 539 static inline void soft_reset(void *reg)
 540 {
 541         int loops = 0;
 542
 543         debug("%s %p\n", __func__, reg);
 544         __raw_writel(1, reg);
 545         while (__raw_readl(reg) & 1) {
 546                 loops++;
 547         }
 548         debug("%s: reset finished after %u loops\n", __func__, loops);
 549 }
 550
 551 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 552                          ((mac)[2] << 16) | ((mac)[3] << 24))
 553 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 554
 555 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 556                                struct cpsw_priv *priv)
 557 {
 558         __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
 559         __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
 560 }
 561
 562 #define NUM_TRIES 50
 563 static void cpsw_slave_update_link(struct cpsw_slave *slave,
 564                                    struct cpsw_priv *priv, int *link)
 565 {
 566         char *name = priv->dev->name;
 567         int phy_id = slave->data->phy_id;
 568         int speed, duplex;
 569         unsigned short reg;
 570         u32 mac_control = 0;
 571         int retries = NUM_TRIES;
 572
 573         while (retries-- > 0) {
 574                 if (miiphy_read(name, phy_id, MII_BMSR, &reg)) {
 575                         printf("Failed to read PHY reg\n");
 576                         return; /* could not read, assume no link */
 577                 }
 578
 579                 if (reg & BMSR_LSTATUS) { /* link up */
 580                         speed = miiphy_speed(name, phy_id);
 581                         duplex = miiphy_duplex(name, phy_id);
 582
 583                         *link = 1;
 584                         mac_control = priv->data->mac_control;
 585                         if (speed == 10)
 586                                 mac_control |= BIT(18); /* In Band mode */
 587                         else if (speed == 100)
 588                                 mac_control |= BIT(15);
 589                         else if (speed == 1000) {
 590                                 if (priv->data->gigabit_en)
 591                                         mac_control |= BIT(7);
 592                                 else {
 593                                         /* Disable gigabit as it's non-functional */
 594                                         mac_control &= ~BIT(7);
 595                                         speed = 100;
 596                                 }
 597                         }
 598
 599                         if (duplex == FULL)
 600                                 mac_control |= BIT(0);  /* FULLDUPLEXEN */
 601                         break;
 602                 }
 603                 udelay(100000);
 604         }
 605         debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
 606                 slave->mac_control, mac_control, NUM_TRIES - retries);
 607
 608         if (mac_control == slave->mac_control)
 609                 return;
 610
 611         if (mac_control) {
 612                 printf("link up on port %d, speed %d, %s duplex\n",
 613                                 slave->slave_num, speed,
 614                                 (duplex == FULL) ?  "full" : "half");
 615         } else {
 616                 printf("link down on port %d\n", slave->slave_num);
 617         }
 618
 619         __raw_writel(mac_control, &slave->sliver->mac_control);
 620         slave->mac_control = mac_control;
 621 }
 622
 623 static int cpsw_update_link(struct cpsw_priv *priv)
 624 {
 625         int link = 0;
 626         for_each_slave(priv, cpsw_slave_update_link, priv, &link);
 627         return link;
 628 }
 629
 630 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 631 {
 632         if (priv->host_port == 0)
 633                 return slave_num + 1;
 634         else
 635                 return slave_num;
 636 }
 637
 638 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 639 {
 640         u32     slave_port;
 641
 642         debug("%s\n", __func__);
 643
 644         soft_reset(&slave->sliver->soft_reset);
 645
 646         /* setup priority mapping */
 647         __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
 648         __raw_writel(0x33221100, &slave->regs->tx_pri_map);
 649
 650         /* setup max packet size, and mac address */
 651         __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
 652         cpsw_set_slave_mac(slave, priv);
 653
 654         slave->mac_control = 0; /* no link yet */
 655
 656         /* enable forwarding */
 657         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 658         cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
 659
 660         cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
 661
 662         priv->data->phy_init(priv->dev->name, slave->data->phy_id);
 663 }
 664
 665 static void cpdma_desc_get(struct cpsw_desc *desc)
 666 {
 667         invalidate_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
 668 }
 669
 670 static void cpdma_desc_put(struct cpsw_desc *desc)
 671 {
 672         flush_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
 673 }
 674
 675 static struct cpsw_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
 676 {
 677         struct cpsw_desc *desc = priv->desc_free;
 678
 679         if (desc) {
 680                 cpdma_desc_get(desc);
 681                 priv->desc_free = desc->next;
 682         }
 683         return desc;
 684 }
 685
 686 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpsw_desc *desc)
 687 {
 688         if (desc) {
 689                 desc_write(desc, hw_next, priv->desc_free->dma_desc);
 690                 cpdma_desc_put(desc);
 691                 desc->next = priv->desc_free;
 692                 priv->desc_free = desc;
 693         }
 694 }
 695 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
 696                         volatile void *buffer, int len)
 697 {
 698         struct cpsw_desc *desc, *prev;
 699         u32 mode;
 700
 701         if (!buffer) {
 702                 printf("ERROR: %s() NULL buffer\n", __func__);
 703                 return -EINVAL;
 704         }
 705
 706         flush_dcache_range((u32)buffer, (u32)buffer + len);
 707
 708         desc = cpdma_desc_alloc(priv);
 709         if (!desc)
 710                 return -ENOMEM;
 711
 712         debug("%s@%d: %cX desc %p DMA %p\n", __func__, __LINE__,
 713                 chan == &priv->rx_chan ? 'R' : 'T', desc, desc->dma_desc);
 714         if (len < PKT_MIN)
 715                 len = PKT_MIN;
 716
 717         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
 718
 719         desc->next = NULL;
 720         desc_write(desc, hw_next,   0);
 721         desc_write(desc, hw_buffer, buffer);
 722         desc_write(desc, hw_len,    len);
 723         desc_write(desc, hw_mode,   mode | len);
 724
 725         desc->sw_buffer = buffer;
 726
 727         cpdma_desc_put(desc);
 728         if (!chan->head) {
 729                 /* simple case - first packet enqueued */
 730                 chan->head = desc;
 731                 chan->tail = desc;
 732                 chan_write(chan, hdp, desc->dma_desc);
 733                 goto done;
 734         }
 735
 736         /* not the first packet - enqueue at the tail */
 737         prev = chan->tail;
 738
 739         prev->next = desc;
 740         cpdma_desc_get(prev);
 741         desc_write(prev, hw_next, desc->dma_desc);
 742         cpdma_desc_put(prev);
 743
 744         chan->tail = desc;
 745
 746         /* next check if EOQ has been triggered already */
 747         if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
 748                 chan_write(chan, hdp, desc->dma_desc);
 749
 750 done:
 751         if (chan->rxfree)
 752                 chan_write(chan, rxfree, 1);
 753         debug("%s@%d\n", __func__, __LINE__);
 754         return 0;
 755 }
 756
 757 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
 758                          volatile void **buffer, int *len)
 759 {
 760         struct cpsw_desc *desc = chan->head;
 761         u32 status;
 762
 763         if (!desc)
 764                 return -ENOENT;
 765
 766         cpdma_desc_get(desc);
 767
 768         status = desc_read(desc, hw_mode);
 769         if (status & CPDMA_DESC_OWNER)
 770                 return -EBUSY;
 771
 772         if (len)
 773                 *len = status & 0x7ff;
 774
 775         if (buffer)
 776                 *buffer = desc->sw_buffer;
 777         debug("%s@%d: buffer=%p\n", __func__, __LINE__, desc->sw_buffer);
 778
 779         chan->head = desc->next;
 780         chan_write(chan, cp, desc->dma_desc);
 781
 782         cpdma_desc_free(priv, desc);
 783         return 0;
 784 }
 785
 786 static int cpsw_init(struct eth_device *dev, bd_t *bis)
 787 {
 788         struct cpsw_priv        *priv = dev->priv;
 789         int i, ret;
 790
 791         debug("%s\n", __func__);
 792
 793         priv->data->control(1);
 794
 795         /* soft reset the controller and initialize priv */
 796         soft_reset(&priv->regs->soft_reset);
 797
 798         /* initialize and reset the address lookup engine */
 799         cpsw_ale_enable(priv, 1);
 800         cpsw_ale_clear(priv, 1);
 801         cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
 802
 803         /* setup host port priority mapping */
 804         __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
 805         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 806
 807         /* disable priority elevation and enable statistics on all ports */
 808         __raw_writel(0, &priv->regs->ptype);
 809
 810         /* enable statistics collection only on the host port */
 811         __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
 812
 813         cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 814
 815         cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port,
 816                            ALE_SECURE);
 817         cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port);
 818
 819         for_each_slave(priv, cpsw_slave_init, priv);
 820
 821         cpsw_update_link(priv);
 822
 823         /* init descriptor pool */
 824         for (i = 0; i < NUM_DESCS; i++) {
 825                 struct cpsw_desc *next_desc = (i < (NUM_DESCS - 1)) ?
 826                         &priv->descs[i + 1] : NULL;
 827
 828                 priv->descs[i].next = next_desc;
 829                 desc_write(&priv->descs[i], hw_next,
 830                         next_desc ? next_desc->dma_desc : 0);
 831                 cpdma_desc_put(&priv->descs[i]);
 832         }
 833         priv->desc_free = &priv->descs[0];
 834
 835         /* initialize channels */
 836         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 837                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 838                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER2;
 839                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER2;
 840                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 841
 842                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 843                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER2;
 844                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER2;
 845         } else {
 846                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 847                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER1;
 848                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER1;
 849                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 850
 851                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 852                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER1;
 853                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER1;
 854         }
 855
 856         /* clear dma state */
 857         soft_reset(priv->dma_regs + CPDMA_SOFTRESET);
 858
 859         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 860                 for (i = 0; i < priv->data->channels; i++) {
 861                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 * i);
 862                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
 863                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 * i);
 864                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 * i);
 865                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 * i);
 866                 }
 867         } else {
 868                 for (i = 0; i < priv->data->channels; i++) {
 869                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 * i);
 870                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
 871                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 * i);
 872                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 * i);
 873                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 * i);
 874
 875                 }
 876         }
 877         __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
 878         __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
 879
 880         /* submit rx descs */
 881         for (i = 0; i < PKTBUFSRX; i++) {
 882                 ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i],
 883                                    PKTSIZE);
 884                 if (ret < 0) {
 885                         printf("error %d submitting rx desc\n", ret);
 886                         break;
 887                 }
 888         }
 889
 890         return ret;
 891 }
 892
 893 static void cpsw_halt(struct eth_device *dev)
 894 {
 895         struct cpsw_priv *priv = dev->priv;
 896
 897         debug("%s\n", __func__);
 898         priv->data->control(0);
 899 }
 900
 901 static int cpsw_send(struct eth_device *dev, volatile void *packet, int length)
 902 {
 903         struct cpsw_priv *priv = dev->priv;
 904         volatile void *buffer;
 905         int len;
 906
 907         debug("%s@%d: sending packet %p..%p\n", __func__, __LINE__,
 908                 packet, packet + length - 1);
 909
 910         if (!priv->data->mac_control && !cpsw_update_link(priv)) {
 911                 printf("%s: Cannot send packet; link is down\n", __func__);
 912                 return -EIO;
 913         }
 914
 915         /* first reap completed packets */
 916         while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0)
 917                 /* NOP */;
 918
 919         return cpdma_submit(priv, &priv->tx_chan, packet, length);
 920 }
 921
 922 static int cpsw_recv(struct eth_device *dev)
 923 {
 924         struct cpsw_priv        *priv = dev->priv;
 925         volatile void *buffer;
 926         int len;
 927
 928         while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) == 0) {
 929                 if (buffer) {
 930                         NetReceive(buffer, len);
 931                         cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
 932                 } else {
 933                         printf("NULL buffer returned from cpdma_process\n");
 934                         return -EIO;
 935                 }
 936         }
 937         return 0;
 938 }
 939
 940 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
 941                             struct cpsw_priv *priv)
 942 {
 943         void                    *regs = priv->regs;
 944         struct cpsw_slave_data  *data = priv->data->slave_data + slave_num;
 945
 946         debug("%s@%d: slave[%d] %p\n", __func__, __LINE__,
 947                 slave_num, slave);
 948         slave->slave_num = slave_num;
 949         slave->data     = data;
 950         slave->regs     = regs + data->slave_reg_ofs;
 951         slave->sliver   = regs + data->sliver_reg_ofs;
 952 }
 953
 954 int cpsw_register(struct cpsw_platform_data *data)
 955 {
 956         struct cpsw_priv        *priv;
 957         void                    *regs = (void *)data->cpsw_base;
 958         struct eth_device       *dev;
 959         int i;
 960
 961         debug("%s@%d\n", __func__, __LINE__);
 962
 963         dev = calloc(sizeof(*dev), 1);
 964         if (!dev)
 965                 return -ENOMEM;
 966
 967         priv = calloc(sizeof(*priv), 1);
 968         if (!priv) {
 969                 free(dev);
 970                 return -ENOMEM;
 971         }
 972
 973         priv->data = data;
 974         priv->dev  = dev;
 975
 976         priv->slaves = calloc(sizeof(struct cpsw_slave), data->slaves);
 977         if (!priv->slaves) {
 978                 free(dev);
 979                 free(priv);
 980                 return -ENOMEM;
 981         }
 982
 983         for (i = 0; i < NUM_DESCS; i++) {
 984                 priv->descs[i].dma_desc = memalign(CONFIG_SYS_CACHELINE_SIZE,
 985                                 sizeof(struct cpsw_desc) * NUM_DESCS);
 986                 if (!priv->descs[i].dma_desc) {
 987                         while (--i >= 0) {
 988                                 free(priv->descs[i].dma_desc);
 989                         }
 990                         free(priv->slaves);
 991                         free(priv);
 992                         free(dev);
 993                         return -ENOMEM;
 994                 }
 995                 debug("DMA desc[%d] allocated @ %p desc_size %u\n",
 996                         i, priv->descs[i].dma_desc,
 997                         sizeof(*priv->descs[i].dma_desc));
 998         }
 999
1000         priv->host_port         = data->host_port_num;
1001         priv->regs              = regs;
1002         priv->host_port_regs    = regs + data->host_port_reg_ofs;
1003         priv->dma_regs          = regs + data->cpdma_reg_ofs;
1004         priv->ale_regs          = regs + data->ale_reg_ofs;
1005
1006         for_each_slave(priv, cpsw_slave_setup, idx, priv);
1007         debug("%s@%d\n", __func__, __LINE__);
1008
1009         strcpy(dev->name, "cpsw");
1010         dev->iobase     = 0;
1011         dev->init       = cpsw_init;
1012         dev->halt       = cpsw_halt;
1013         dev->send       = cpsw_send;
1014         dev->recv       = cpsw_recv;
1015         dev->priv       = priv;
1016
1017         eth_register(dev);
1018
1019         cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
1020
1021         return 1;
1022 }