6 * @brief This file contains Atm types common to a number of Atm components.
9 * IXP400 SW Release version 2.0
11 * -- Copyright Notice --
14 * Copyright 2001-2005, Intel Corporation.
15 * All rights reserved.
18 * SPDX-License-Identifier: BSD-3-Clause
20 * -- End of Copyright Notice --
23 /* ------------------------------------------------------
24 Doxygen group definitions
25 ------------------------------------------------------ */
27 * @defgroup IxAtmTypes IXP400 ATM Types (IxAtmTypes)
29 * @brief The common set of types used in many Atm components
39 * @enum IxAtmLogicalPort
41 * @brief Logical Port Definitions :
43 * Only 1 port is available in SPHY configuration
44 * 12 ports are enabled in MPHY configuration
49 IX_UTOPIA_PORT_0 = 0, /**< Port 0 */
50 #ifdef IX_NPE_MPHYMULTIPORT
51 IX_UTOPIA_PORT_1, /**< Port 1 */
52 IX_UTOPIA_PORT_2, /**< Port 2 */
53 IX_UTOPIA_PORT_3, /**< Port 3 */
54 IX_UTOPIA_PORT_4, /**< Port 4 */
55 IX_UTOPIA_PORT_5, /**< Port 5 */
56 IX_UTOPIA_PORT_6, /**< Port 6 */
57 IX_UTOPIA_PORT_7, /**< Port 7 */
58 IX_UTOPIA_PORT_8, /**< Port 8 */
59 IX_UTOPIA_PORT_9, /**< Port 9 */
60 IX_UTOPIA_PORT_10, /**< Port 10 */
61 IX_UTOPIA_PORT_11, /**< Port 11 */
62 #endif /* IX_NPE_MPHY */
63 IX_UTOPIA_MAX_PORTS /**< Not a port - just a definition for the
64 * maximum possible ports
69 * @def IX_ATM_CELL_PAYLOAD_SIZE
70 * @brief Size of a ATM cell payload
72 #define IX_ATM_CELL_PAYLOAD_SIZE (48)
75 * @def IX_ATM_CELL_SIZE
76 * @brief Size of a ATM cell, including header
78 #define IX_ATM_CELL_SIZE (53)
81 * @def IX_ATM_CELL_SIZE_NO_HEC
82 * @brief Size of a ATM cell, excluding HEC byte
84 #define IX_ATM_CELL_SIZE_NO_HEC (IX_ATM_CELL_SIZE - 1)
87 * @def IX_ATM_OAM_CELL_SIZE_NO_HEC
88 * @brief Size of a OAM cell, excluding HEC byte
90 #define IX_ATM_OAM_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC
93 * @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE
94 * @brief Size of a AAL0 48 Cell payload
96 #define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE
99 * @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE
100 * @brief Size of a AAL5 Cell payload
102 #define IX_ATM_AAL5_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE
105 * @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC
106 * @brief Size of a AAL0 52 Cell, excluding HEC byte
108 #define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC
112 * @def IX_ATM_MAX_VPI
113 * @brief Maximum value of an ATM VPI
115 #define IX_ATM_MAX_VPI 255
118 * @def IX_ATM_MAX_VCI
119 * @brief Maximum value of an ATM VCI
121 #define IX_ATM_MAX_VCI 65535
124 * @def IX_ATM_MAX_NUM_AAL_VCS
125 * @brief Maximum number of active AAL5/AAL0 VCs in the system
127 #define IX_ATM_MAX_NUM_AAL_VCS 32
130 * @def IX_ATM_MAX_NUM_VC
131 * @brief Maximum number of active AAL5/AAL0 VCs in the system
132 * The use of this macro is depreciated, it is retained for
133 * backward compatiblity. For current software release
134 * and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used.
136 #define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS
141 * @def IX_ATM_MAX_NUM_OAM_TX_VCS
142 * @brief Maximum number of active OAM Tx VCs in the system,
145 #define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS
148 * @def IX_ATM_MAX_NUM_OAM_RX_VCS
149 * @brief Maximum number of active OAM Rx VCs in the system,
150 * 1 OAM VC shared accross all ports
152 #define IX_ATM_MAX_NUM_OAM_RX_VCS 1
155 * @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS
156 * @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system
158 #define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS)
161 * @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS
162 * @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system
164 #define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS)
167 * @def IX_ATM_IDLE_CELLS_CONNID
168 * @brief VC Id used to indicate idle cells in the returned schedule table.
170 #define IX_ATM_IDLE_CELLS_CONNID 0
174 * @def IX_ATM_CELL_HEADER_VCI_GET
175 * @brief get the VCI field from a cell header
177 #define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \
178 (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK);
181 * @def IX_ATM_CELL_HEADER_VPI_GET
182 * @brief get the VPI field from a cell header
184 #define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \
185 (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK);
188 * @def IX_ATM_CELL_HEADER_PTI_GET
189 * @brief get the PTI field from a cell header
191 #define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \
192 ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK;
195 * @typedef IxAtmCellHeader
197 * @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A
199 typedef unsigned int IxAtmCellHeader;
203 * @enum IxAtmServiceCategory
205 * @brief Enumerated type representing available ATM service categories.
206 * For more informatoin on these categories, see "Traffic Management
207 * Specification" v4.1, published by the ATM Forum -
208 * http://www.atmforum.com
212 IX_ATM_CBR, /**< Constant Bit Rate */
213 IX_ATM_RTVBR, /**< Real Time Variable Bit Rate */
214 IX_ATM_VBR, /**< Variable Bit Rate */
215 IX_ATM_UBR, /**< Unspecified Bit Rate */
216 IX_ATM_ABR /**< Available Bit Rate (not supported) */
218 } IxAtmServiceCategory;
222 * @enum IxAtmRxQueueId
224 * @brief Rx Queue Type for RX traffic
226 * IxAtmRxQueueId defines the queues involved for receiving data.
228 * There are two queues to facilitate prioritisation handling
229 * and processing the 2 queues with different algorithms and
232 * e.g. : one queue can carry voice (or time-critical traffic), the
233 * other queue can carry non-voice traffic
238 IX_ATM_RX_A = 0, /**< RX queue A */
239 IX_ATM_RX_B, /**< RX queue B */
240 IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */
244 * @brief Structure describing an ATM traffic contract for a Virtual
247 * Structure is used to specify the requested traffic contract for a
248 * VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup
251 * These parameters are defined by the ATM forum working group
252 * (http://www.atmforum.com).
254 * @note Typical values for a voice channel 64 Kbit/s
255 * - atmService @a IX_ATM_RTVBR
256 * - pcr 400 (include IP overhead, and AAL5 trailer)
257 * - cdvt 5000000 (5 ms)
260 * @note Typical values for a data channel 800 Kbit/s
261 * - atmService @a IX_ATM_UBR
262 * - pcr 1962 (include IP overhead, and AAL5 trailer)
263 * - cdvt 5000000 (5 ms)
268 IxAtmServiceCategory atmService; /**< ATM service category */
269 unsigned pcr; /**< Peak Cell Rate - cells per second */
270 unsigned cdvt; /**< Cell Delay Variation Tolerance - in nanoseconds */
271 unsigned scr; /**< Sustained Cell Rate - cells per second */
272 unsigned mbs; /**< Max Burst Size - cells */
273 unsigned mcr; /**< Minimum Cell Rate - cells per second */
274 unsigned mfs; /**< Max Frame Size - cells */
275 } IxAtmTrafficDescriptor;
278 * @typedef IxAtmConnId
280 * @brief ATM VC data connection identifier.
282 * This is is generated by IxAtmdAcc when a successful connection is
283 * made on a VC. The is the ID by which IxAtmdAcc knows an active
284 * VC and should be used in IxAtmdAcc API calls to reference a
287 typedef unsigned int IxAtmConnId;
290 * @typedef IxAtmSchedulerVcId
292 * @brief ATM VC scheduling connection identifier.
294 * This id is generated and used by ATM Tx controller, generally
295 * the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component
296 * will request one of these Ids whenever a data connection on
297 * a Tx VC is requested. This ID will be used in callbacks to
298 * the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a
301 typedef int IxAtmSchedulerVcId;
304 * @typedef IxAtmNpeRxVcId
306 * @brief ATM Rx VC identifier used by the ATM Npe.
308 * This Id is generated by IxAtmdAcc when a successful data connection
309 * is made on a rx VC.
311 typedef unsigned int IxAtmNpeRxVcId;
314 * @brief ATM Schedule Table entry
316 * This IxAtmScheduleTableEntry is used by an ATM scheduler to inform
317 * IxAtmdAcc about the data to transmit (in term of cells per VC)
319 * This structure defines
320 * @li the number of cells to be transmitted (numberOfCells)
321 * @li the VC connection to be used for transmission (connId).
323 * @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the
324 * corresponding number of idle cells will be transmitted to the hardware.
329 IxAtmConnId connId; /**< connection Id
331 * Identifier of VC from which cells are to be transmitted.
332 * When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates
333 * that the system should transmit the specified number
334 * of idle cells. Unknown connIds result in the transmission
337 unsigned int numberOfCells; /**< number of cells to transmit
339 * The number of contiguous cells to schedule from this VC
340 * at this point. The valid range is from 1 to
341 * @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This
342 * number can swap over mbufs and pdus. OverSchduling results
343 * in the transmission of idle cells.
345 } IxAtmScheduleTableEntry;
348 * @brief This structure defines a schedule table which gives details
349 * on which data (from which VCs) should be transmitted for a
350 * forthcoming period of time for a particular port and the
351 * order in which that data should be transmitted.
353 * The schedule table consists of a series of entries each of which
354 * will schedule one or more cells from a particular registered VC.
355 * The total number of cells scheduled and the total number of
356 * entries in the table are also indicated.
361 unsigned tableSize; /**< Number of entries
363 * Indicates the total number of
364 * entries in the table.
366 unsigned totalCellSlots; /**< Number of cells
368 * Indicates the total number of ATM
369 * cells which are scheduled by all the
370 * entries in the table.
372 IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries
374 * Pointer to an array
375 * containing tableSize entries
377 } IxAtmScheduleTable;
379 #endif /* IXATMTYPES_H */
382 * @} defgroup IxAtmTypes